Pub Date : 2023-11-15DOI: 10.1109/OJCAS.2023.3332853
Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari
The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3 $times $ less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47 $times $ compared to prior time-domain accelerators.
{"title":"A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm","authors":"Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari","doi":"10.1109/OJCAS.2023.3332853","DOIUrl":"10.1109/OJCAS.2023.3332853","url":null,"abstract":"The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 compared to prior time-domain accelerators.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10318175","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135710807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-02DOI: 10.1109/OJCAS.2023.3329723
Dimitrios Baxevanakis;Dimitris Nikitas;Paul P. Sotiriadis
This work presents a power stage architecture that combines high–linearity with high–efficiency. The power stage is configured as a push–pull Class–A topology with two buck–converters providing its supply rails. The buck–converters continuously track the stage’s output with a small constant margin, creating a minimum, constant voltage drop on the output devices; thus, the stage’s efficiency is increased and its linearity is improved. Theoretical analysis of the topology and its feedback control are presented, while a design example is implemented and simulated in Cadence Spectre as proof–of–concept.
{"title":"Class–CTA: Concept and Theoretical Analysis of a High Linearity and Efficiency Power Stage Architecture","authors":"Dimitrios Baxevanakis;Dimitris Nikitas;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2023.3329723","DOIUrl":"10.1109/OJCAS.2023.3329723","url":null,"abstract":"This work presents a power stage architecture that combines high–linearity with high–efficiency. The power stage is configured as a push–pull Class–A topology with two buck–converters providing its supply rails. The buck–converters continuously track the stage’s output with a small constant margin, creating a minimum, constant voltage drop on the output devices; thus, the stage’s efficiency is increased and its linearity is improved. Theoretical analysis of the topology and its feedback control are presented, while a design example is implemented and simulated in Cadence Spectre as proof–of–concept.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10305243","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134888124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-02DOI: 10.1109/OJCAS.2023.3328871
Mohammad Oveisi;Seyedali Hosseinisangchi;Payam Heydari
A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized as a primary contributor to spectral regrowth and elevated levels of OOBE, are investigated. Additionally, the impact of filtering and bandwidth (BW) limitation on OOBE is taken into account. Comprehensive simulations verify the accuracy of the analytical study. The results provided throughout this paper can be used to determine the linearity and phase noise requirements of different blocks, such as PLL and power amplifier (PA) within a TX chain to design a system complying with a specific mask emission dictated by a particular standard.
{"title":"A Study of Out-of-Band Emission in Digital Transmitters Due to PLL Phase Noise, Circuit Non-Linearity, and Bandwidth Limitation","authors":"Mohammad Oveisi;Seyedali Hosseinisangchi;Payam Heydari","doi":"10.1109/OJCAS.2023.3328871","DOIUrl":"10.1109/OJCAS.2023.3328871","url":null,"abstract":"A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized as a primary contributor to spectral regrowth and elevated levels of OOBE, are investigated. Additionally, the impact of filtering and bandwidth (BW) limitation on OOBE is taken into account. Comprehensive simulations verify the accuracy of the analytical study. The results provided throughout this paper can be used to determine the linearity and phase noise requirements of different blocks, such as PLL and power amplifier (PA) within a TX chain to design a system complying with a specific mask emission dictated by a particular standard.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10305256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134888134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-04DOI: 10.1109/OJCAS.2023.3302254
Archisman Ghosh;Debayan Das;Shreyas Sen
Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show $sim 5000times $ minimum traces to disclosure (MTD) improvement over the unprotected implementation with $sim 1.25times $ power and $sim 1.2times $ area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows $3.4M$ MTD which is $500times $ greater than the unprotected solution.
{"title":"Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure","authors":"Archisman Ghosh;Debayan Das;Shreyas Sen","doi":"10.1109/OJCAS.2023.3302254","DOIUrl":"10.1109/OJCAS.2023.3302254","url":null,"abstract":"Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show \u0000<inline-formula> <tex-math>$sim 5000times $ </tex-math></inline-formula>\u0000 minimum traces to disclosure (MTD) improvement over the unprotected implementation with \u0000<inline-formula> <tex-math>$sim 1.25times $ </tex-math></inline-formula>\u0000 power and \u0000<inline-formula> <tex-math>$sim 1.2times $ </tex-math></inline-formula>\u0000 area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows \u0000<inline-formula> <tex-math>$3.4M$ </tex-math></inline-formula>\u0000 MTD which is \u0000<inline-formula> <tex-math>$500times $ </tex-math></inline-formula>\u0000 greater than the unprotected solution.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10208218.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43006579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.
{"title":"Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices","authors":"Diptashree Das;Ziyue Xu;Mehdi Nasrollahpour;Isabel Martos-Repath;Mohsen Zaeimbashi;Adam Khalifa;Ankit Mittal;Sydney S. Cash;Nian X. Sun;Aatmesh Shrivastava;Marvin Onabajo","doi":"10.1109/OJCAS.2023.3259233","DOIUrl":"10.1109/OJCAS.2023.3259233","url":null,"abstract":"A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10076793","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41223293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/OJCAS.2023.3245439
Gabriele Manganaro;Nicole Mcfarlane
DEAR readers, happy 2023! I have recently been elected as the Vice President for Publications for the CAS Society for the 2023–2024 term. Because of that I am unable to complete my term as EiC, which would have otherwise elapsed on 31 December 2023. We are lucky to have two outstanding leaders, Alison Burdett and Nicole Mcfarlane, presently serving as Associate Editors-in-Chief (AEiC). The IEEE Circuits and Systems Society (CASS) has formally appointed Nicole Mcfarlane to serve as the IEEE Open Journal of Circuits and Systems (OJCAS) Editor-in-Chief for the 2023 calendar year and I am glad that she accepted to work in this capacity. I have no doubts that Nicole will carry her new appointment flawlessly and I wish her all the best.
{"title":"New Year Editorial 2023","authors":"Gabriele Manganaro;Nicole Mcfarlane","doi":"10.1109/OJCAS.2023.3245439","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3245439","url":null,"abstract":"DEAR readers, happy 2023! I have recently been elected as the Vice President for Publications for the CAS Society for the 2023–2024 term. Because of that I am unable to complete my term as EiC, which would have otherwise elapsed on 31 December 2023. We are lucky to have two outstanding leaders, Alison Burdett and Nicole Mcfarlane, presently serving as Associate Editors-in-Chief (AEiC). The IEEE Circuits and Systems Society (CASS) has formally appointed Nicole Mcfarlane to serve as the IEEE Open Journal of Circuits and Systems (OJCAS) Editor-in-Chief for the 2023 calendar year and I am glad that she accepted to work in this capacity. I have no doubts that Nicole will carry her new appointment flawlessly and I wish her all the best.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10056875.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-04DOI: 10.1109/OJCAS.2023.3234244
Ahmed K. Khamis;Mohammed Agamy
This paper proposes a method of transferring physical continuous and switching/converter circuits working in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) to graph representation, independent of the connection or the number of circuit components, so that machine learning (ML) algorithms and applications can be easily applied. Such methodology is generalized and is applicable to circuits with any number of switches, components, sources and loads, and can be useful in applications such as artificial intelligence (AI) based circuit design automation, layout optimization, circuit synthesis and performance monitoring and control. The proposed circuit representation and feature extraction methodology is applied to seven types of continuous circuits, ranging from second to fourth order and it is also applied to three of the most common converters (Buck, Boost, and Buck-boost) operating in CCM or DCM. A classifier ML task can easily differentiate between circuit types as well as their mode of operation, showing classification accuracy of 97.37% in continuous circuits and 100% in switching circuits.
{"title":"Comprehensive Mapping of Continuous/Switching Circuits in CCM and DCM to Machine Learning Domain Using Homogeneous Graph Neural Networks","authors":"Ahmed K. Khamis;Mohammed Agamy","doi":"10.1109/OJCAS.2023.3234244","DOIUrl":"10.1109/OJCAS.2023.3234244","url":null,"abstract":"This paper proposes a method of transferring physical continuous and switching/converter circuits working in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) to graph representation, independent of the connection or the number of circuit components, so that machine learning (ML) algorithms and applications can be easily applied. Such methodology is generalized and is applicable to circuits with any number of switches, components, sources and loads, and can be useful in applications such as artificial intelligence (AI) based circuit design automation, layout optimization, circuit synthesis and performance monitoring and control. The proposed circuit representation and feature extraction methodology is applied to seven types of continuous circuits, ranging from second to fourth order and it is also applied to three of the most common converters (Buck, Boost, and Buck-boost) operating in CCM or DCM. A classifier ML task can easily differentiate between circuit types as well as their mode of operation, showing classification accuracy of 97.37% in continuous circuits and 100% in switching circuits.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10006651.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46165934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Every EV (Electric Vehicle) comes with limited energy storing capability. After travelling a certain distance, a charging facility is required to recharge the EV batteries, which is easy to be made available in cities. But, in remote locations, charging service is challenging. Therefore, big countries like USA, Canada, China, Russia, India, Australia, and few Arabian countries are planning to provide pillar top solar panels on remote locations for EV charging in emergency situations. To operate in this situation, a special charging adapter is required to extract maximum power from the panel using the MPPT (Maximum Power Point Tracking) technique, monitor the charging current, and safely complete the charging process. In this paper, a single sensor-based economical charging adapter is presented for EVs to fulfil this objective. Moreover, the Single Input Fuzzy Logic tuned Deterministic Optimization (SIFL-DO) algorithm is proposed to accomplish MPPT operation and battery charging management. Because of its low cost and fast response, the single current sensor-based charging adapter is highly economical. Additionally, the SIFL-DO algorithm has very good condition estimation and decision-making capability, which accurately performs MPPT and charging management. In this work, the capability of the developed adapter with the SIFL-DO algorithm is evaluated on Hardware prototype. Also, comparative studies are performed w.r.t. state-of-the-art techniques. Further to determine the industry’s suitability, the developed technique is tested on European Standard EN50530.
{"title":"Adaptive Control Technique for Portable Solar Powered EV Charging Adapter to Operate in Remote Location","authors":"Nishant Kumar;Harshit Kumar Singh;Roland Niwareeba","doi":"10.1109/OJCAS.2023.3247573","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3247573","url":null,"abstract":"Every EV (Electric Vehicle) comes with limited energy storing capability. After travelling a certain distance, a charging facility is required to recharge the EV batteries, which is easy to be made available in cities. But, in remote locations, charging service is challenging. Therefore, big countries like USA, Canada, China, Russia, India, Australia, and few Arabian countries are planning to provide pillar top solar panels on remote locations for EV charging in emergency situations. To operate in this situation, a special charging adapter is required to extract maximum power from the panel using the MPPT (Maximum Power Point Tracking) technique, monitor the charging current, and safely complete the charging process. In this paper, a single sensor-based economical charging adapter is presented for EVs to fulfil this objective. Moreover, the Single Input Fuzzy Logic tuned Deterministic Optimization (SIFL-DO) algorithm is proposed to accomplish MPPT operation and battery charging management. Because of its low cost and fast response, the single current sensor-based charging adapter is highly economical. Additionally, the SIFL-DO algorithm has very good condition estimation and decision-making capability, which accurately performs MPPT and charging management. In this work, the capability of the developed adapter with the SIFL-DO algorithm is evaluated on Hardware prototype. Also, comparative studies are performed w.r.t. state-of-the-art techniques. Further to determine the industry’s suitability, the developed technique is tested on European Standard EN50530.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10050089.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications.
{"title":"Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs","authors":"Shivendra Singh Parihar;Simon Thomann;Girish Pahwa;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/OJCAS.2023.3309478","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3309478","url":null,"abstract":"Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10233878.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3348971
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