Pub Date : 2025-08-27DOI: 10.1109/OJCAS.2025.3592376
Andres Rojas;Gawen Follet;Gordana Jovanovic Dolecek;José M. De La Rosa;Gustavo Liñán-Cembrano
This paper presents a hardware-software deep learning architecture for prediction-based spectrum sensing in Cognitive Radio (CR) applications. A convolutional neural network-based predictor for spectrum occupancy was trained using the band power from I/Q samples acquired by a softwaredefined radio (SDR). Additionally, a second neural engine was trained for radio frequency (RF) frame detection based on spectrograms. We implemented a transfer-learning solution using a You-Only-LookOnce version 8 nano model with a synthetic dataset comprising thousands of wireless signals, including Wi-Fi, Bluetooth, and collision frames. Once trained, the two neural networks were transferred to a Raspberry Pi 5 – an affordable single-board computer – connected to two (one for Rx, one for Tx) ADALM-PLUTO SDR systems for benchmarking using over-the-air signals in the 2.4 GHz band. Together with our methodology and experimental results, the paper also presents an overview of current spectrum prediction proposals and RF frame detectors. Remarkably, to the best of our knowledge, this proposed framework is the first approach towards an Internet of Things-suitable implementation of prediction-based spectrum sensing for CR applications.
针对认知无线电（CR）应用中基于预测的频谱感知，提出了一种硬件-软件深度学习架构。使用软件定义无线电（SDR）获取的I/Q样本的频带功率训练基于卷积神经网络的频谱占用预测器。此外，还训练了第二个神经引擎，用于基于频谱图的射频帧检测。我们使用You-Only-LookOnce版本8纳米模型实现了一个迁移学习解决方案，该模型具有包含数千个无线信号的合成数据集，包括Wi-Fi、蓝牙和碰撞帧。经过训练后，两个神经网络被转移到Raspberry Pi 5上，这是一款价格实惠的单板计算机，连接到两个（一个用于Rx，一个用于Tx） ADALM-PLUTO SDR系统，使用2.4 GHz频段的空中信号进行基准测试。结合我们的方法和实验结果，本文还概述了目前的频谱预测建议和射频帧检测器。值得注意的是，据我们所知，该框架是第一个适合物联网的基于预测的频谱感知CR应用实现方法。
{"title":"Prediction-Based Spectrum Sensing Framework for Cognitive Radio","authors":"Andres Rojas;Gawen Follet;Gordana Jovanovic Dolecek;José M. De La Rosa;Gustavo Liñán-Cembrano","doi":"10.1109/OJCAS.2025.3592376","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3592376","url":null,"abstract":"This paper presents a hardware-software deep learning architecture for prediction-based spectrum sensing in Cognitive Radio (CR) applications. A convolutional neural network-based predictor for spectrum occupancy was trained using the band power from I/Q samples acquired by a softwaredefined radio (SDR). Additionally, a second neural engine was trained for radio frequency (RF) frame detection based on spectrograms. We implemented a transfer-learning solution using a You-Only-LookOnce version 8 nano model with a synthetic dataset comprising thousands of wireless signals, including Wi-Fi, Bluetooth, and collision frames. Once trained, the two neural networks were transferred to a Raspberry Pi 5 – an affordable single-board computer – connected to two (one for Rx, one for Tx) ADALM-PLUTO SDR systems for benchmarking using over-the-air signals in the 2.4 GHz band. Together with our methodology and experimental results, the paper also presents an overview of current spectrum prediction proposals and RF frame detectors. Remarkably, to the best of our knowledge, this proposed framework is the first approach towards an Internet of Things-suitable implementation of prediction-based spectrum sensing for CR applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"313-328"},"PeriodicalIF":2.4,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142737","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/OJCAS.2025.3602678
Chia Jen Cheng;Ethan Chen;Vanessa Chen
The increase of neural networks used in mission-critical applications requires protecting model parameters to maintain correct inferences. While traditional threats like adversarial inputs have been well-studied, recent research in neural network security has explored attacking model weights to degrade prediction accuracy. Many studies focused on developing fault detection methods, and few recovery strategies have been offered. This work proposes combining neural compression technique with modular redundancy to enhance model parameters' fault tolerance against adversarial bit-flips at runtime. The fault tolerance improvement of the proposed method is demonstrated with two model architectures and two datasets. Further, a field programmable gate array realization of the scheme has been implemented to demonstrate a hardware proof of concept.
{"title":"Improving Neural Network Fault Tolerance Against Weight Attack","authors":"Chia Jen Cheng;Ethan Chen;Vanessa Chen","doi":"10.1109/OJCAS.2025.3602678","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3602678","url":null,"abstract":"The increase of neural networks used in mission-critical applications requires protecting model parameters to maintain correct inferences. While traditional threats like adversarial inputs have been well-studied, recent research in neural network security has explored attacking model weights to degrade prediction accuracy. Many studies focused on developing fault detection methods, and few recovery strategies have been offered. This work proposes combining neural compression technique with modular redundancy to enhance model parameters' fault tolerance against adversarial bit-flips at runtime. The fault tolerance improvement of the proposed method is demonstrated with two model architectures and two datasets. Further, a field programmable gate array realization of the scheme has been implemented to demonstrate a hardware proof of concept.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"383-392"},"PeriodicalIF":2.4,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142271","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-25DOI: 10.1109/OJCAS.2025.3602353
Andrew Ash;John Hu
In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.
{"title":"A Proxy ADC Framework for Side-Channel Secure ADC Analysis","authors":"Andrew Ash;John Hu","doi":"10.1109/OJCAS.2025.3602353","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3602353","url":null,"abstract":"In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"401-413"},"PeriodicalIF":2.4,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11138015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-14DOI: 10.1109/OJCAS.2025.3598990
Syed Adil Ali Shah;Young-Gun Pu;Young-Joon Kim;Kang-Yoon Lee
This paper introduces a highly efficient cross-coupled active rectifier with fast switching comparators for wireless power transfer (WPT) system. Wireless power transfer technology is increasingly being utilized in various applications. In our proposed design an active diode switches are introduced at lower side of power MOSFET to minimize the switching delay in power transistors and also reduces reverse leakage current to boost power conversion efficiency. The active diode is constructed from high-speed comparators and CMOS power switches. A cross-coupled technique is applied to the high side PMOS power transistors, in order to minimizing power consumption and optimizing current management. This enhancement not only improves the power efficiency of the cross-coupled active rectifier but also prolongs battery life and boosts the overall Efficiency. The cross-coupled architecture of the proposed rectifier enables high-speed switching, which is necessary for its design. This allows for fast response times and efficient signal processing. The presented cross-coupled active rectifier is designed using $0.18~mu $ m CMOS technology. It delivers 2.77 W of output power using a $1~mu $ F capacitor with a 0.3A load current, and it achieves a power efficiency of 92.4%.
{"title":"A High Efficient Cross-Coupled Active Rectifier by Using High Speed Switching Comparators for Wireless Power Receiver","authors":"Syed Adil Ali Shah;Young-Gun Pu;Young-Joon Kim;Kang-Yoon Lee","doi":"10.1109/OJCAS.2025.3598990","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3598990","url":null,"abstract":"This paper introduces a highly efficient cross-coupled active rectifier with fast switching comparators for wireless power transfer (WPT) system. Wireless power transfer technology is increasingly being utilized in various applications. In our proposed design an active diode switches are introduced at lower side of power MOSFET to minimize the switching delay in power transistors and also reduces reverse leakage current to boost power conversion efficiency. The active diode is constructed from high-speed comparators and CMOS power switches. A cross-coupled technique is applied to the high side PMOS power transistors, in order to minimizing power consumption and optimizing current management. This enhancement not only improves the power efficiency of the cross-coupled active rectifier but also prolongs battery life and boosts the overall Efficiency. The cross-coupled architecture of the proposed rectifier enables high-speed switching, which is necessary for its design. This allows for fast response times and efficient signal processing. The presented cross-coupled active rectifier is designed using <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS technology. It delivers 2.77 W of output power using a <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>F capacitor with a 0.3A load current, and it achieves a power efficiency of 92.4%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"393-400"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3574336
Eric Christie;Jared Marchant;Shea Smith;Long Kong;Chia-Hung Chen;Shiuh-Hua Wood Chiang
Ultra-low-supply-voltage (ULV) analog-to-digital converters (ADCs) operating at 0.21 V or lower are attractive for Internet-of-Things (IoT) and embedded applications due to their extremely low power consumption. This paper surveys state-of-the-art ULV ADCs to evaluate current trends and design strategies. Architectures, circuit implementations, and calibration techniques are analyzed and key trends are identified. Based on the observations, the paper provides recommendations for the circuit designer to make judicious design choices to obtain the desired performance for ULV ADCs. This paper further explores the VCO-based architecture and proposes a new topology to achieve high resolution for ULV ADCs.
{"title":"A Review on Sub-0.21-V Ultra-Low-Supply-Voltage Analog-to-Digital Converters","authors":"Eric Christie;Jared Marchant;Shea Smith;Long Kong;Chia-Hung Chen;Shiuh-Hua Wood Chiang","doi":"10.1109/OJCAS.2025.3574336","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3574336","url":null,"abstract":"Ultra-low-supply-voltage (ULV) analog-to-digital converters (ADCs) operating at 0.21 V or lower are attractive for Internet-of-Things (IoT) and embedded applications due to their extremely low power consumption. This paper surveys state-of-the-art ULV ADCs to evaluate current trends and design strategies. Architectures, circuit implementations, and calibration techniques are analyzed and key trends are identified. Based on the observations, the paper provides recommendations for the circuit designer to make judicious design choices to obtain the desired performance for ULV ADCs. This paper further explores the VCO-based architecture and proposes a new topology to achieve high resolution for ULV ADCs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"228-240"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106915","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3586748
Wenhao Wu;Fei Yuan;Yushi Zhou
This paper presents a sub-threshold all-digital delay-locked loop (DLL) for the generation of the timing signals of low-power low-data-rate successive approximation register analog-to-digital converters. The delay line of the DLL consists of a set of cascaded static inverters with its large per-stage-delay obtained by powering the delay with an exceedingly low supply voltage. The per-stage-delay of the delay line is adjusted by varying the supply voltage provided by a sub-threshold voltage generator. Voltage recovery blocks consisting of cascaded static inverters with different supply voltages are used to recover the low voltage swing of the delay line to the nominal voltage swing of the DLL. High-voltage-threshold pMOS transistors are used to minimize the short-circuit-induced power consumption of voltage-recovering inverters. The proposed DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3v3 device models. Simulation results show the DLL locks to a $0sim 0.6$ V 100 kHz 50% duty cycle external timing reference at FF/0.6V/-$20^{o}$ C, TT/0.6V/$27^{o}$ C, and SS/0.6V/$60^{o}$ C in approximately 7 cycles of the timing reference with no accumulated static phase errors. The DLL occupies an area of 0.00559 mm2, offers 0.35% normalized root-mean-square jitter, and consumes 92 nW.
本文提出了一种用于低功率低数据率逐次逼近寄存器模数转换器时序信号生成的亚阈值全数字锁延环。DLL的延迟线由一组级联的静态逆变器组成，通过极低的供电电压为延迟供电而获得较大的每级延迟。延迟线的每级延迟通过改变由亚阈值电压发生器提供的电源电压来调节。电压恢复模块由具有不同电源电压的级联静态逆变器组成，用于将延迟线的低电压摆幅恢复到DLL的标称电压摆幅。采用高压阈值pMOS晶体管来降低电压恢复逆变器的短路引起的功耗。该DLL采用台积电130 nm 1.2 V CMOS技术设计，电源电压降低至0.6 V，并使用Spectre与BSIM3v3器件模型进行分析。仿真结果表明，DLL在大约7个周期内锁定到FF/0.6V/- $20^{o}$ C、TT/0.6V/ $27^{o}$ C和SS/0.6V/ $60^{o}$ C的$0sim /0.6 $ V 100 kHz 50%占空比外部定时基准，且无累积静态相位误差。DLL占地0.00559 mm2，提供0.35%的标准化均方根抖动，消耗92 nW。
{"title":"Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC","authors":"Wenhao Wu;Fei Yuan;Yushi Zhou","doi":"10.1109/OJCAS.2025.3586748","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3586748","url":null,"abstract":"This paper presents a sub-threshold all-digital delay-locked loop (DLL) for the generation of the timing signals of low-power low-data-rate successive approximation register analog-to-digital converters. The delay line of the DLL consists of a set of cascaded static inverters with its large per-stage-delay obtained by powering the delay with an exceedingly low supply voltage. The per-stage-delay of the delay line is adjusted by varying the supply voltage provided by a sub-threshold voltage generator. Voltage recovery blocks consisting of cascaded static inverters with different supply voltages are used to recover the low voltage swing of the delay line to the nominal voltage swing of the DLL. High-voltage-threshold pMOS transistors are used to minimize the short-circuit-induced power consumption of voltage-recovering inverters. The proposed DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3v3 device models. Simulation results show the DLL locks to a <inline-formula> <tex-math>$0sim 0.6$ </tex-math></inline-formula> V 100 kHz 50% duty cycle external timing reference at FF/0.6V/-<inline-formula> <tex-math>$20^{o}$ </tex-math></inline-formula>C, TT/0.6V/<inline-formula> <tex-math>$27^{o}$ </tex-math></inline-formula>C, and SS/0.6V/<inline-formula> <tex-math>$60^{o}$ </tex-math></inline-formula>C in approximately 7 cycles of the timing reference with no accumulated static phase errors. The DLL occupies an area of 0.00559 mm2, offers 0.35% normalized root-mean-square jitter, and consumes 92 nW.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"270-282"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106517","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3583268
Masoud Askariraad;Stefano Gregori
This paper presents static and dynamic models for linear and exponential integrated charge pumps in both step-up and step-down modes. The static models are used to compare the slow-switching and fast-switching output resistance of various configurations, considering optimized and non-optimized capacitors and switches. In the dynamic models, the self-loading capacitance is determined using a simpler approach than previous works, allowing for a more straightforward comparison of the start-up time and charging efficiency. To highlight the differences between linear and exponential charge pumps, the working voltages of capacitors and switches are calculated, with these expressions guiding the selection of the most appropriate devices for each configuration. Additionally, parasitic capacitances and leakage currents are modeled and analyzed across the circuit configurations, and their impact on overall efficiency is assessed. The procedure for optimally sizing capacitors and switches using different device types is then discussed. Finally, two design examples in 65-nm CMOS technology are presented to validate the models, demonstrate design procedures, and highlight the advantages and limitations of practical implementations of each circuit.
{"title":"Comparison and Design of Linear and Exponential Integrated Charge Pumps","authors":"Masoud Askariraad;Stefano Gregori","doi":"10.1109/OJCAS.2025.3583268","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3583268","url":null,"abstract":"This paper presents static and dynamic models for linear and exponential integrated charge pumps in both step-up and step-down modes. The static models are used to compare the slow-switching and fast-switching output resistance of various configurations, considering optimized and non-optimized capacitors and switches. In the dynamic models, the self-loading capacitance is determined using a simpler approach than previous works, allowing for a more straightforward comparison of the start-up time and charging efficiency. To highlight the differences between linear and exponential charge pumps, the working voltages of capacitors and switches are calculated, with these expressions guiding the selection of the most appropriate devices for each configuration. Additionally, parasitic capacitances and leakage currents are modeled and analyzed across the circuit configurations, and their impact on overall efficiency is assessed. The procedure for optimally sizing capacitors and switches using different device types is then discussed. Finally, two design examples in 65-nm CMOS technology are presented to validate the models, demonstrate design procedures, and highlight the advantages and limitations of practical implementations of each circuit.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"295-312"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106932","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3565921
Fei Yuan
This paper provides a critical review and the classification of comparators in low-power low-data-rate (1 kS/s~1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs). Both voltage-domain and time-domain comparators are studied and their pros and cons are examined. The architecture, comparison time, and power consumption of five widely used voltage-domain dynamic comparators are studied first. It is followed with an investigation of kickback in comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converters (DACs) of SAR ADCs arising from the different resistances of DAC switches gives rise to a differential clock kickback that occurs earlier than output kickback with more strength hence dictating kickback in dynamic comparators. If the strength and duration of clock kickback are sufficiently large, the comparator will yield an erroneous output. The dependence of clock kickback on the input of SAR ADCs in the least significant bit (LSB) conversion is also investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are investigated, and the minimum tuning bits of digitally tuned offset compensation capacitor arrays is obtained. The noise of dynamic comparators is also investigated and design trade-offs between noise, power consumption, kickback, and the loading of the comparator on DAC are examined. The extensive simulation results of the comparators designed in a TSMC 130 nm 1.2 V CMOS technologies with reduced supply voltages and analyzed using Spectre from Cadence Design Systems with BSIM 3.3 device models are provided.
{"title":"A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC","authors":"Fei Yuan","doi":"10.1109/OJCAS.2025.3565921","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3565921","url":null,"abstract":"This paper provides a critical review and the classification of comparators in low-power low-data-rate (1 kS/s~1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs). Both voltage-domain and time-domain comparators are studied and their pros and cons are examined. The architecture, comparison time, and power consumption of five widely used voltage-domain dynamic comparators are studied first. It is followed with an investigation of kickback in comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converters (DACs) of SAR ADCs arising from the different resistances of DAC switches gives rise to a differential clock kickback that occurs earlier than output kickback with more strength hence dictating kickback in dynamic comparators. If the strength and duration of clock kickback are sufficiently large, the comparator will yield an erroneous output. The dependence of clock kickback on the input of SAR ADCs in the least significant bit (LSB) conversion is also investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are investigated, and the minimum tuning bits of digitally tuned offset compensation capacitor arrays is obtained. The noise of dynamic comparators is also investigated and design trade-offs between noise, power consumption, kickback, and the loading of the comparator on DAC are examined. The extensive simulation results of the comparators designed in a TSMC 130 nm 1.2 V CMOS technologies with reduced supply voltages and analyzed using Spectre from Cadence Design Systems with BSIM 3.3 device models are provided.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"241-256"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3585654
Sai Sanjeet;Sanchari Das;Shiuh-Hua Wood Chiang;Masahiro Fujita;Bibhu Datta Datta
The deployment of digitally-trained analog Spiking Neural Networks (SNNs) presents a promising approach for energy-efficient edge computing. However, training such networks is not trivial, and discrepancies between digital training models and their continuous-time analog implementations pose challenges in validation and performance verification. This paper aims to bridge the gap between the design of analog neuron models and training SNNs with the neuron model, along with a time-domain verification framework that enables circuit designers to validate their analog SNN implementations in a simulation environment resembling industry-standard EDA tools such as Cadence and Synopsys while offering significantly faster execution. This work focuses on a ring oscillator-based neuron model, which realizes the leaky integrate-and-fire (LIF) neuron. The design of the ring oscillator-based neuron is discussed, and the neuron model is digitized using the bilinear transform to enable training. The trained network is used to classify the MNIST dataset with an accuracy of 97.35% and the Iris dataset with an accuracy of 93.33%. We further introduce a time-domain verification framework based on Simulink to validate the trained networks. We verify our approach by comparing digitally-trained PyTorch models against analog implementations simulated using our framework on the Iris dataset, revealing accuracy discrepancies between the analog and digital counterparts, along with insights into the cause of such discrepancies, which would have been difficult to simulate with SPICE simulators. Additionally, we verify the generated Simulink models against Verilog-A models simulated in Cadence Spectre, demonstrating that our framework produces identical outputs while achieving an order-of-magnitude speedup. By providing an efficient, accurate, and accessible verification platform, our framework bridges the gap between digital training and analog hardware verification, facilitating the development of robust, high-performance SNNs for edge applications.
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Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3549442
Seyedmohamadjavad Motaman;Sarah S. Sharif;Yaser M. Banad
Enhancing power efficiency and performance in neuromorphic computing systems is critical for next-generation artificial intelligence applications. We propose the Nanoscale Side-contacted Field Effect Diode (S-FED)—a novel solution that significantly lowers power usage and improves circuit speed—enabling efficient neuron circuit design. Our proposed integrate-and-fire (IF) neuron model demonstrates remarkable performance metrics: 44 nW power consumption (85% lower than current designs), 0.964 fJ energy per spike (36% improvement over state-of-the-art), and a spiking frequency ranging from 20 to 100 MHz. Moreover, we show how to bias the circuit to enable both deterministic and stochastic operation, mimicking key computational features of biological neurons. The stochastic behavior can be precisely controlled through reference voltage modulation, achieving firing probabilities from 0% to 100% and enabling probabilistic computing capabilities. The architecture exhibits robust stability across process (channel length and doping)-voltage-temperature (PVT) variations, maintaining consistent performance with less than 7% spike amplitude variation for channel lengths from 7.5nm to 15nm, doping from $5times 10{^{{20}}}$ cm${}^ - 3 $ to $1times 10{^{{2}}} {^{{1}}}$ cm${}^ - 3 $ , supply voltages from 0.8V to 1.2V, and temperatures spanning −40°C to 120°C. The model features tunable thresholds (0.8V to 1.4V) and reliable operation across input spike pulse widths from 0.5 ns to 2 ns. This advancement in neuromorphic hardware paves the way for more efficient brain-inspired computing systems.
提高神经形态计算系统的功率效率和性能对于下一代人工智能应用至关重要。我们提出了纳米级侧接触场效应二极管（S-FED），这是一种新颖的解决方案，可显着降低功耗并提高电路速度，从而实现高效的神经元电路设计。我们提出的IF神经元模型展示了卓越的性能指标：44 nW功耗（比当前设计低85%），每尖峰能量0.964 fJ（比最先进的技术提高36%），尖峰频率范围从20到100 MHz。此外，我们展示了如何偏置电路以实现确定性和随机操作，模拟生物神经元的关键计算特征。通过参考电压调制可以精确控制随机行为，实现从0%到100%的发射概率，并实现概率计算能力。该架构在整个过程（通道长度和掺杂）电压温度（PVT）变化中表现出强大的稳定性，在通道长度从7.5nm到15nm，掺杂从$5乘以10{^{{20}}}$ cm ${}^ - 3 $到$1乘以10{^{{2}}}{^{{1}}}$ cm ${}}^ - 3 $，电源电压从0.8V到1.2V，温度范围从- 40°C到120°C时，保持稳定的性能，峰值幅度变化小于7%。该模型具有可调阈值（0.8V至1.4V）和可靠的工作跨越输入尖峰脉冲宽度从0.5 ns到2 ns。神经形态硬件的这一进步为更高效的大脑启发计算系统铺平了道路。
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