Pub Date : 2025-06-30DOI: 10.1109/ICJECE.2025.3572936
Krishna Velmajala;Srinivasa Rao Sandepudi
This article introduces a high step-up interleaved p-type nonisolated dc–dc converter that achieves fault-tolerant operation without relying on redundant switches. The proposed converter design offers several advantages, including high voltage gain, improved efficiency, lower voltage stress on components, lower peak-to-peak input current, mitigates voltage oscillations across switches, and inherent common grounding making it suitable for a wide range of applications. The converter ensures uniform current sharing across its inductors and improves its reliability. Its scalable nature allows for the addition of stages to meet higher voltage and power requirements. The controller is designed to reduce transients during steady state and fault conditions to ensure stable operation. To achieve fault tolerance without extra switches, the design integrates a fuse-MOSFET combination for effective short-circuit protection. A 400-W prototype has been designed, built, and tested successfully demonstrating the converter functionality under normal and fault conditions.
{"title":"A High Step-Up Interleaved p-Type Nonisolated DC–DC Converter With Reconfiguration Capability","authors":"Krishna Velmajala;Srinivasa Rao Sandepudi","doi":"10.1109/ICJECE.2025.3572936","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3572936","url":null,"abstract":"This article introduces a high step-up interleaved p-type nonisolated dc–dc converter that achieves fault-tolerant operation without relying on redundant switches. The proposed converter design offers several advantages, including high voltage gain, improved efficiency, lower voltage stress on components, lower peak-to-peak input current, mitigates voltage oscillations across switches, and inherent common grounding making it suitable for a wide range of applications. The converter ensures uniform current sharing across its inductors and improves its reliability. Its scalable nature allows for the addition of stages to meet higher voltage and power requirements. The controller is designed to reduce transients during steady state and fault conditions to ensure stable operation. To achieve fault tolerance without extra switches, the design integrates a fuse-MOSFET combination for effective short-circuit protection. A 400-W prototype has been designed, built, and tested successfully demonstrating the converter functionality under normal and fault conditions.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"192-203"},"PeriodicalIF":2.1,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144606209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-16DOI: 10.1109/ICJECE.2025.3566877
{"title":"IEEE Canadian Journal of Electrical and Computer Engineering","authors":"","doi":"10.1109/ICJECE.2025.3566877","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3566877","url":null,"abstract":"","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 2","pages":"C2-C2"},"PeriodicalIF":2.1,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11037607","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144299213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-13DOI: 10.1109/ICJECE.2025.3570443
Shailendra Yadav;Brajesh Kumar Kaushik;Amita Giri
The CMOS-based neuromorphic computing system (NCS) face significant challenges, such as increasing energy usage and vast area footprints, surpassing the efficiency of biological brains. Spin transfer torque magnetic tunnel junction (STT-MTJ), a type of spin device, offers convenient benefits, including nonvolatility, increased energy efficiency, increased speed of operation, and compatibility with CMOS, making them ideal for energy-efficient spiking NCSs that exhibit neuronal behavior. However, the high energy consumption in spintronic-based NCS, primarily due to the high write current required for MTJ switching, remains a significant challenge as neurons in these systems tend to stay active longer than necessary. To address this challenge, we introduce a novel hybrid STT-MTJ/CMOS write terminate circuit (SM-WTC) that efficiently terminates the MTJ current efficiently after MTJ-state switches, significantly improving energy consumption and speed by $2.6times $ and $2.3times $ , compared to conventional NCSs. The proposed SM-WTC technique achieves energy consumption reductions of 52.7%, 58.3%, and 62.18% compared to prior work in real-time sensing (RTS) circuit, common-mode tracking and terminating circuit (CM-TTC), and conventional-NCS, respectively. A Cadence Virtuoso simulation using 65-nm CMOS technology has been used to evaluate the proposed circuit. Furthermore, SM-WTC-based NCS achieves a 67.2% improvement in energy-delay product (EDP) over conventional NCS for image edge detection. These advancements position SM-WTC as a commercially viable solution for next-generation artificial intelligence (AI) accelerators and brain-inspired computing architecture.
{"title":"Energy-Efficient Hybrid STT-MTJ/CMOS Circuit for Machine Learning-Assisted Neuromorphic Computing Applications","authors":"Shailendra Yadav;Brajesh Kumar Kaushik;Amita Giri","doi":"10.1109/ICJECE.2025.3570443","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3570443","url":null,"abstract":"The CMOS-based neuromorphic computing system (NCS) face significant challenges, such as increasing energy usage and vast area footprints, surpassing the efficiency of biological brains. Spin transfer torque magnetic tunnel junction (STT-MTJ), a type of spin device, offers convenient benefits, including nonvolatility, increased energy efficiency, increased speed of operation, and compatibility with CMOS, making them ideal for energy-efficient spiking NCSs that exhibit neuronal behavior. However, the high energy consumption in spintronic-based NCS, primarily due to the high write current required for MTJ switching, remains a significant challenge as neurons in these systems tend to stay active longer than necessary. To address this challenge, we introduce a novel hybrid STT-MTJ/CMOS write terminate circuit (SM-WTC) that efficiently terminates the MTJ current efficiently after MTJ-state switches, significantly improving energy consumption and speed by <inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.3times $ </tex-math></inline-formula>, compared to conventional NCSs. The proposed SM-WTC technique achieves energy consumption reductions of 52.7%, 58.3%, and 62.18% compared to prior work in real-time sensing (RTS) circuit, common-mode tracking and terminating circuit (CM-TTC), and conventional-NCS, respectively. A Cadence Virtuoso simulation using 65-nm CMOS technology has been used to evaluate the proposed circuit. Furthermore, SM-WTC-based NCS achieves a 67.2% improvement in energy-delay product (EDP) over conventional NCS for image edge detection. These advancements position SM-WTC as a commercially viable solution for next-generation artificial intelligence (AI) accelerators and brain-inspired computing architecture.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"184-191"},"PeriodicalIF":2.1,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144481833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/ICJECE.2025.3567092
Rishabh Bansal;Rushiv Bansal;Mayank Kumar
In this article, a novel bidirectional boost-side interleaved switched boost (BBSISB) multiport converter is proposed. The boost-side interleaving (BSI) of the converter improves its performance in terms of input current ripple and reliability in medium-power applications. The BSI reduces the input current ripple (i.e., zero at 50% of duty ratio), and it also provides an open circuit (OC) switch fault-tolerance index (FTI) of 100% at the load end. The switched-boost action topology uses time multiplexing of boost and buck switches to produce regulated voltage at output ports, whereas the boost-side phase interleaving provides the paralleling of large input boost current with reduced current ripple. The bidirectional capability of the converter enables the power flow from the battery to the load end in the absence of an input supply. The performance analysis of the proposed converter with respect to switching loss, conduction loss, FTI, current ripple, and cost is performed and compared with similar converters. An experimental setup of the BBSISB multiport converter is developed in the laboratory with a constant-current, constant-voltage (CC-CV) mode of charging of the battery to verify the derived analytical results.
{"title":"Improved Reliability and Performance Evaluation of Switched-Boost Multiport Converter Using Time-Multiplexing Control","authors":"Rishabh Bansal;Rushiv Bansal;Mayank Kumar","doi":"10.1109/ICJECE.2025.3567092","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3567092","url":null,"abstract":"In this article, a novel bidirectional boost-side interleaved switched boost (BBSISB) multiport converter is proposed. The boost-side interleaving (BSI) of the converter improves its performance in terms of input current ripple and reliability in medium-power applications. The BSI reduces the input current ripple (i.e., zero at 50% of duty ratio), and it also provides an open circuit (OC) switch fault-tolerance index (FTI) of 100% at the load end. The switched-boost action topology uses time multiplexing of boost and buck switches to produce regulated voltage at output ports, whereas the boost-side phase interleaving provides the paralleling of large input boost current with reduced current ripple. The bidirectional capability of the converter enables the power flow from the battery to the load end in the absence of an input supply. The performance analysis of the proposed converter with respect to switching loss, conduction loss, FTI, current ripple, and cost is performed and compared with similar converters. An experimental setup of the BBSISB multiport converter is developed in the laboratory with a constant-current, constant-voltage (CC-CV) mode of charging of the battery to verify the derived analytical results.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"167-175"},"PeriodicalIF":2.1,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144308520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/ICJECE.2025.3568042
Bandi Narasimha Rao;Anuradha Sundru
The classical orthogonal frequency division multiplexing (OFDM) systems gained significant new dimensions with the introduction of index modulation (IM) schemes. However, reduced data rates are the drawback in IM-based systems when implemented using higher-order modulation techniques. Hence, to improve the data rate, we proposed a new OFDM-IM system by varying the inactive subcarriers in in-phase and quadrature-phase in every subblock, namely, a dual-mode homogenous OFDM-IM (DMH OFDM-IM) system. Furthermore, we introduce a novel noise power and signal-to-noise ratio (SNR) estimation algorithm for the proposed system, which operates over a Nakagami-m fading channel. The proposed estimation algorithm makes use of nulled subcarriers available in every subblock of the proposed system to estimate noise power. The introduced estimator is both spectral and energy efficient as it uses inactive subcarriers that carry no energy. Simulation results emphasize that the developed estimator achieves lower noise power and estimates the SNR at an ideal value in contrast to the existing estimators of OFDM system. Moreover, differential noise power (DNP) is determined for the proposed system (DMH OFDM-IM) to track channel variations effectively.
{"title":"A Spectral and Energy Efficient Noise Variance and SNR Estimator for DMH OFDM-IM Systems","authors":"Bandi Narasimha Rao;Anuradha Sundru","doi":"10.1109/ICJECE.2025.3568042","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3568042","url":null,"abstract":"The classical orthogonal frequency division multiplexing (OFDM) systems gained significant new dimensions with the introduction of index modulation (IM) schemes. However, reduced data rates are the drawback in IM-based systems when implemented using higher-order modulation techniques. Hence, to improve the data rate, we proposed a new OFDM-IM system by varying the inactive subcarriers in in-phase and quadrature-phase in every subblock, namely, a dual-mode homogenous OFDM-IM (DMH OFDM-IM) system. Furthermore, we introduce a novel noise power and signal-to-noise ratio (SNR) estimation algorithm for the proposed system, which operates over a Nakagami-m fading channel. The proposed estimation algorithm makes use of nulled subcarriers available in every subblock of the proposed system to estimate noise power. The introduced estimator is both spectral and energy efficient as it uses inactive subcarriers that carry no energy. Simulation results emphasize that the developed estimator achieves lower noise power and estimates the SNR at an ideal value in contrast to the existing estimators of OFDM system. Moreover, differential noise power (DNP) is determined for the proposed system (DMH OFDM-IM) to track channel variations effectively.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"176-183"},"PeriodicalIF":2.1,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144308521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-05DOI: 10.1109/ICJECE.2025.3538581
Nhlanhla Mbuli
The relationship between the impedances of the paths in which power flows determines the amount of power flowing in those paths. The distributed series impedances (DSIs) are devices that can inject impedance in these paths, enabling power flow control to achieve many positive objectives. This article presents the results of a comprehensive literature review on using DSIs in smart grids. A bibliometric assessment is performed for the publications included in the review, covering the annual number of publications, the top five most cited journals, and the top five most cited publications. Moreover, the research is summarized into three main themes: developing DSI technology, using DSIs to solve various power system problems, and optimizing DSI installations. After this, research trends addressing how the research foci have evolved, and areas, where no or little research has been done, are discussed. Finally, the proposed areas for future research are presented.
{"title":"A Comprehensive Literature Review on the Use of Distributed Series Impedance in Smart Grids","authors":"Nhlanhla Mbuli","doi":"10.1109/ICJECE.2025.3538581","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3538581","url":null,"abstract":"The relationship between the impedances of the paths in which power flows determines the amount of power flowing in those paths. The distributed series impedances (DSIs) are devices that can inject impedance in these paths, enabling power flow control to achieve many positive objectives. This article presents the results of a comprehensive literature review on using DSIs in smart grids. A bibliometric assessment is performed for the publications included in the review, covering the annual number of publications, the top five most cited journals, and the top five most cited publications. Moreover, the research is summarized into three main themes: developing DSI technology, using DSIs to solve various power system problems, and optimizing DSI installations. After this, research trends addressing how the research foci have evolved, and areas, where no or little research has been done, are discussed. Finally, the proposed areas for future research are presented.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"143-154"},"PeriodicalIF":2.1,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144281235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Inverter-based resources (IBRs) play a crucial role in microgrid operation due to their ability to provide power conversion and control functions. Ensuring compliance with standard and grid codes, however, poses a significant challenge in IBR-dominated microgrids. This challenge is exacerbated by the lack of a comprehensive set of instructions tailored specifically for IBR-dominated microgrids, which ideally should consolidate all requirements into a single, centralized document. This article focuses on Canadian grid codes, specifically those in Ontario, due to the growing integration of renewable energy sources and the regulatory framework guiding microgrid development in the region. By analyzing Ontario grid codes, this study aims to provide insights relevant to IBR-dominated microgrid projects within similar regulatory contexts worldwide. A comprehensive analysis of the pertinent standards and grid code provisions is conducted, highlighting the required and recommended protection schemes. Additionally, a case study is presented to demonstrate the practical implementation of protection plan design in compliance with Ontario grid codes. Through this study, insights are provided into the complex interplay between standard and grid code compliance, as well as protection plan design considerations in IBR-dominated microgrids.
{"title":"Canadian Grid Codes and Standards Compliance for Designing Protection Plan in IBR-Dominated Microgrids","authors":"Saeed Sanati;Innocent Kamwa;Bo Cao;Bo Sheng;Xu Minghui;Majid Arabahmadi","doi":"10.1109/ICJECE.2025.3530764","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3530764","url":null,"abstract":"Inverter-based resources (IBRs) play a crucial role in microgrid operation due to their ability to provide power conversion and control functions. Ensuring compliance with standard and grid codes, however, poses a significant challenge in IBR-dominated microgrids. This challenge is exacerbated by the lack of a comprehensive set of instructions tailored specifically for IBR-dominated microgrids, which ideally should consolidate all requirements into a single, centralized document. This article focuses on Canadian grid codes, specifically those in Ontario, due to the growing integration of renewable energy sources and the regulatory framework guiding microgrid development in the region. By analyzing Ontario grid codes, this study aims to provide insights relevant to IBR-dominated microgrid projects within similar regulatory contexts worldwide. A comprehensive analysis of the pertinent standards and grid code provisions is conducted, highlighting the required and recommended protection schemes. Additionally, a case study is presented to demonstrate the practical implementation of protection plan design in compliance with Ontario grid codes. Through this study, insights are provided into the complex interplay between standard and grid code compliance, as well as protection plan design considerations in IBR-dominated microgrids.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"131-142"},"PeriodicalIF":2.1,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144281234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-02DOI: 10.1109/ICJECE.2025.3566465
Meisam Mahdavi;Pierluigi Siano
Altering the flow of power along branch reconfiguration of radial distribution feeders and mitigating the reactive power component through optimal shunt capacitor placement are proven methods for reducing energy losses in distribution systems. However, it is crucial to recognize that variations in load demand can significantly impact the magnitude of these energy losses and reactive power installation costs, potentially influencing the optimal placement of capacitors and the strategy for branch switching. Therefore, accounting for fluctuations in power demand when reconfiguring the network and positioning capacitors is of paramount importance. Nevertheless, incorporating changes in power demand while simultaneously optimizing branch configurations and addressing reactive power in radial feeders can complicate the computational aspects of the problem, leading to increased processing times. Conversely, disregarding the consumption patterns on the demand side can result in inaccurate calculations of distribution losses and related costs. Consequently, this study delves into the influence of demand patterns on the problem of network topology modification and capacitor assignment considering capacitor and switches investment. It aims to determine whether taking into account load variability is merely an option or an indispensable factor in minimizing the cost of energy losses, switching expenses, and reactive power installation budget via the placement of capacitors and altering the topology of the network. The analysis was carried out on multiple distribution grids using a classical optimization means known as a mathematical programming language (AMPL).
{"title":"Impact of Demand-Side Behavior on Line Switching and Reactive Power Management Considering Reconfiguration and Capacitor Costs","authors":"Meisam Mahdavi;Pierluigi Siano","doi":"10.1109/ICJECE.2025.3566465","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3566465","url":null,"abstract":"Altering the flow of power along branch reconfiguration of radial distribution feeders and mitigating the reactive power component through optimal shunt capacitor placement are proven methods for reducing energy losses in distribution systems. However, it is crucial to recognize that variations in load demand can significantly impact the magnitude of these energy losses and reactive power installation costs, potentially influencing the optimal placement of capacitors and the strategy for branch switching. Therefore, accounting for fluctuations in power demand when reconfiguring the network and positioning capacitors is of paramount importance. Nevertheless, incorporating changes in power demand while simultaneously optimizing branch configurations and addressing reactive power in radial feeders can complicate the computational aspects of the problem, leading to increased processing times. Conversely, disregarding the consumption patterns on the demand side can result in inaccurate calculations of distribution losses and related costs. Consequently, this study delves into the influence of demand patterns on the problem of network topology modification and capacitor assignment considering capacitor and switches investment. It aims to determine whether taking into account load variability is merely an option or an indispensable factor in minimizing the cost of energy losses, switching expenses, and reactive power installation budget via the placement of capacitors and altering the topology of the network. The analysis was carried out on multiple distribution grids using a classical optimization means known as a mathematical programming language (AMPL).","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"155-166"},"PeriodicalIF":2.1,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144281295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-18DOI: 10.1109/ICJECE.2024.3469216
Najwa Nasuha Mahzan;Mohammad Lutfi Othman;Noor Izzri Abdul Wahab;Veerapandiyan Veerasamy;Nur Ashida Salim;Aidil Azwin Zainul Abidin;Syed Zahurul Islam
High impedance faults (HIFs) present significant challenges in power systems, particularly when an electrical wire contacts a high-resistance material, leading to low currents that are difficult for traditional relays to detect. With the increasing integration of photovoltaic (PV) systems, these challenges are exacerbated due to the complex behavior of PV-generated signals. This study aims to enhance the detection of HIFs in PV-integrated systems using advanced machine learning techniques. The approach employs various classifiers, including artificial neural networks, support vector machines (SVMs), decision trees, and random forest (RF) to improve fault identification accuracy. A MATLAB/SIMULINK simulation was conducted on an IEEE 13-bus system with a 300-kW solar PV plant. The discrete wavelet transform (DWT) with the db4 wavelet was used for feature extraction, focusing on phase energy values. The classifiers were evaluated under different scenarios, such as normal operation, load switching (LS), capacitor switching (CS), HIF, and line-to-ground (LG) faults. The RF classifier outperformed others, achieving a fault detection accuracy of 99.4083%, demonstrating its robustness in adapting to various fault conditions. The Naive Bayes (NB), multilayer perceptron (MLP), and logistic regression (LR) classifiers achieved lower accuracies of 78.6982%, 76.9231%, and 80.4734%, respectively. These results indicate a significant improvement in fault detection capability, enhancing the stability, reliability, and resilience of electrical grids integrated with PV systems. The findings suggest that the RF classifier is highly effective for HIF detection, which is crucial for the protection and efficient operation of modern power grids with high renewable energy penetration.
{"title":"Performance Analysis of Intelligent Classifiers for High Impedance Fault Detection in a PV-Integrated IEEE-13 Bus System","authors":"Najwa Nasuha Mahzan;Mohammad Lutfi Othman;Noor Izzri Abdul Wahab;Veerapandiyan Veerasamy;Nur Ashida Salim;Aidil Azwin Zainul Abidin;Syed Zahurul Islam","doi":"10.1109/ICJECE.2024.3469216","DOIUrl":"https://doi.org/10.1109/ICJECE.2024.3469216","url":null,"abstract":"High impedance faults (HIFs) present significant challenges in power systems, particularly when an electrical wire contacts a high-resistance material, leading to low currents that are difficult for traditional relays to detect. With the increasing integration of photovoltaic (PV) systems, these challenges are exacerbated due to the complex behavior of PV-generated signals. This study aims to enhance the detection of HIFs in PV-integrated systems using advanced machine learning techniques. The approach employs various classifiers, including artificial neural networks, support vector machines (SVMs), decision trees, and random forest (RF) to improve fault identification accuracy. A MATLAB/SIMULINK simulation was conducted on an IEEE 13-bus system with a 300-kW solar PV plant. The discrete wavelet transform (DWT) with the db4 wavelet was used for feature extraction, focusing on phase energy values. The classifiers were evaluated under different scenarios, such as normal operation, load switching (LS), capacitor switching (CS), HIF, and line-to-ground (LG) faults. The RF classifier outperformed others, achieving a fault detection accuracy of 99.4083%, demonstrating its robustness in adapting to various fault conditions. The Naive Bayes (NB), multilayer perceptron (MLP), and logistic regression (LR) classifiers achieved lower accuracies of 78.6982%, 76.9231%, and 80.4734%, respectively. These results indicate a significant improvement in fault detection capability, enhancing the stability, reliability, and resilience of electrical grids integrated with PV systems. The findings suggest that the RF classifier is highly effective for HIF detection, which is crucial for the protection and efficient operation of modern power grids with high renewable energy penetration.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 2","pages":"98-108"},"PeriodicalIF":2.1,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/ICJECE.2025.3550383
Liang-Bi Chen;Xiang-Rui Huang;Hsin-Yu Chen
In this article, a handwriting teaching system based on artificial intelligence (AI) edge computing technology is proposed. The proposed system combines gesture tracking, gesture recognition, and other related AI technologies. Additionally, the development platform for AI edge computing in this system is developed to teach handwriting and practice drawing. The proposed system is composed of a teacher-end teaching host and several student-end AI edge computing smart devices. The student-end AI edge computing smart device incorporates virtual drawing and writing, finger digital computing teaching, a virtual keyboard, virtual sliding, and sleep prevention warnings. The teacher-end teaching host allows the teacher to conduct a teaching course. Moreover, the teacher-end teaching host and the student smart device can simultaneously display images on a large screen to facilitate teaching demonstrations. Furthermore, this system has a comprehensive data storage cloud platform, which can record the data uploaded by each student to a storage cloud platform to facilitate teaching evaluations. This work differs from traditional handwriting and painting technique studies in the classroom, and the AI virtual drawing technology proposed in this work can produce impressive visual effects for visual media, including animation, graphics, and text.
{"title":"An Intelligent Handwriting and Painting Teaching System Based on Artificial Intelligence Edge Computing Technology","authors":"Liang-Bi Chen;Xiang-Rui Huang;Hsin-Yu Chen","doi":"10.1109/ICJECE.2025.3550383","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3550383","url":null,"abstract":"In this article, a handwriting teaching system based on artificial intelligence (AI) edge computing technology is proposed. The proposed system combines gesture tracking, gesture recognition, and other related AI technologies. Additionally, the development platform for AI edge computing in this system is developed to teach handwriting and practice drawing. The proposed system is composed of a teacher-end teaching host and several student-end AI edge computing smart devices. The student-end AI edge computing smart device incorporates virtual drawing and writing, finger digital computing teaching, a virtual keyboard, virtual sliding, and sleep prevention warnings. The teacher-end teaching host allows the teacher to conduct a teaching course. Moreover, the teacher-end teaching host and the student smart device can simultaneously display images on a large screen to facilitate teaching demonstrations. Furthermore, this system has a comprehensive data storage cloud platform, which can record the data uploaded by each student to a storage cloud platform to facilitate teaching evaluations. This work differs from traditional handwriting and painting technique studies in the classroom, and the AI virtual drawing technology proposed in this work can produce impressive visual effects for visual media, including animation, graphics, and text.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 2","pages":"87-97"},"PeriodicalIF":2.1,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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