Pub Date : 2025-07-18DOI: 10.1109/ICJECE.2025.3578984
Luis Cisneros-Villalobos;José Gerardo Vera-Dimas;David Martínez-Martínez;Outmane Oubram;Roy López-Sesenes
This article presents research on the phenomenon of sympathetic inrush current triggered by the energization of a third transformer in parallel with two others already connected, considering the impact of circuit-breaker grading capacitance, which is an emerging in the literature on the subject. The aim is to propose recommendations to mitigate the intensity of this phenomenon to reduce the risk of outages or system failures during transformer energization. The study focuses on a common configuration in the central Mexican electrical grid, which may include power transformers connected in parallel, which can be energized through their 230 or 85 kV windings. The research employs electrical power system modeling using the Alternative Transients Program software to simulate typical scenarios involving substation switch operations during grid activity. It incorporates transformer models with manufacturer-specified saturation characteristics and a certain level of remanent magnetization. With the results obtained, it is inferred that the magnitude, waveform, and duration of the sympathetic inrush currents can cause imbalances and affect the normal operation of the system. Transformer outages can occur due to malfunctioning of its differential and overcurrent relays, as well as power quality problems. Remanent magnetization is not a determining factor for the appearance of the phenomenon. However, the magnitude of the sympathetic inrush current is strongly related to the closing time of the circuit breaker. Furthermore, the findings indicate that a higher capacitance makes the sympathetic inrush current phenomenon more evident.
{"title":"Influence of Grading Capacitance on Sympathetic Inrush Current of Parallel Power Transformers Influence de la capacité de répartition sur le courant d’enclenchement sympathique des transformateurs de puissance en parallèle","authors":"Luis Cisneros-Villalobos;José Gerardo Vera-Dimas;David Martínez-Martínez;Outmane Oubram;Roy López-Sesenes","doi":"10.1109/ICJECE.2025.3578984","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3578984","url":null,"abstract":"This article presents research on the phenomenon of sympathetic inrush current triggered by the energization of a third transformer in parallel with two others already connected, considering the impact of circuit-breaker grading capacitance, which is an emerging in the literature on the subject. The aim is to propose recommendations to mitigate the intensity of this phenomenon to reduce the risk of outages or system failures during transformer energization. The study focuses on a common configuration in the central Mexican electrical grid, which may include power transformers connected in parallel, which can be energized through their 230 or 85 kV windings. The research employs electrical power system modeling using the Alternative Transients Program software to simulate typical scenarios involving substation switch operations during grid activity. It incorporates transformer models with manufacturer-specified saturation characteristics and a certain level of remanent magnetization. With the results obtained, it is inferred that the magnitude, waveform, and duration of the sympathetic inrush currents can cause imbalances and affect the normal operation of the system. Transformer outages can occur due to malfunctioning of its differential and overcurrent relays, as well as power quality problems. Remanent magnetization is not a determining factor for the appearance of the phenomenon. However, the magnitude of the sympathetic inrush current is strongly related to the closing time of the circuit breaker. Furthermore, the findings indicate that a higher capacitance makes the sympathetic inrush current phenomenon more evident.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"246-255"},"PeriodicalIF":2.1,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144695485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Satellite terrestrial edge computing network (STECN) has significant potential application deploying mobile edge computing (MEC) in offloading the computational tasks by the heterogeneous Internet of Thing (IoT) terminals under terrestrial network (TN). In this article, we present a methodological approach toward modeling the simulation environment for a novel multitier multiconstellation STECN where the IoT user equipment (UE) from both aviation space and ground will offload computing tasks into the edge satellite network for processing. We designed a network model, a communication and coverage time model and a computing model under the proposed STECN. We proposed two algorithms with three offloading schemes addressing variability in latency tolerance by heterogeneous UEs. We optimized the allocation of communication and computing resources by the satellites under the model by adopting a deep deterministic policy gradient (DDPG) algorithm with an actor-critic network for training and learning. We approached simulation modeling by designing and developing relevant modules, simulation architecture, and workflow. We incorporated techniques to fine tune the training system under specific evaluation matrices so that our simulation model can be followed by others in the domain.
{"title":"Approach Toward Simulation Modeling With Reinforced Offloading for Heterogeneous IoT Terminals Under a Novel STECN","authors":"Kaushik Sarker;Rongke Liu;Shenzhan Xu;Hangyu Zhang","doi":"10.1109/ICJECE.2025.3574344","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3574344","url":null,"abstract":"Satellite terrestrial edge computing network (STECN) has significant potential application deploying mobile edge computing (MEC) in offloading the computational tasks by the heterogeneous Internet of Thing (IoT) terminals under terrestrial network (TN). In this article, we present a methodological approach toward modeling the simulation environment for a novel multitier multiconstellation STECN where the IoT user equipment (UE) from both aviation space and ground will offload computing tasks into the edge satellite network for processing. We designed a network model, a communication and coverage time model and a computing model under the proposed STECN. We proposed two algorithms with three offloading schemes addressing variability in latency tolerance by heterogeneous UEs. We optimized the allocation of communication and computing resources by the satellites under the model by adopting a deep deterministic policy gradient (DDPG) algorithm with an actor-critic network for training and learning. We approached simulation modeling by designing and developing relevant modules, simulation architecture, and workflow. We incorporated techniques to fine tune the training system under specific evaluation matrices so that our simulation model can be followed by others in the domain.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"234-245"},"PeriodicalIF":2.1,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144687662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-08DOI: 10.1109/ICJECE.2025.3572410
Cheng-Ying Yang;Yi-Nan Lin;Victor R. L. Shen;Frank H. C. Shen;Wun-Siang Jheng
Correct use of home appliances is intended to avoid property damage and life unsafety. Also, serious fire accidents can affect the safety of one’s neighborhood. Therefore, this study uses the Internet of Things (IoT) platform to build an intelligent system that aims to detect the temperature rise of home appliances. It is employed to monitor the usage states of home appliances in real time. Hereby, the microcontroller, node microcontrol unit (NodeMCU-32S), is used to develop an IoT platform combined with sensors for measuring ac voltage, current, and ambient temperature so that the electrical power and temperature rise of load (e.g., electric motor) can be detected. Meanwhile, the smart measurement system is integrated with mobile devices to upload the detected datasets to the Google cloud database system. Moreover, the verification of feasibility and soundness of a system model is performed by using the Petri net tool, WoPeD, for the purpose of eliminating the improper states to optimize the system performance. Finally, the experimental results show that the proposed IoT-enabled system has a promising precision of 94.17% and a recall of 92.26%, which obviously outperforms other existing state-of-the-art systems.
{"title":"A Novel IoT-Enabled System for Real-Time Monitoring Home Appliances Using Petri Nets","authors":"Cheng-Ying Yang;Yi-Nan Lin;Victor R. L. Shen;Frank H. C. Shen;Wun-Siang Jheng","doi":"10.1109/ICJECE.2025.3572410","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3572410","url":null,"abstract":"Correct use of home appliances is intended to avoid property damage and life unsafety. Also, serious fire accidents can affect the safety of one’s neighborhood. Therefore, this study uses the Internet of Things (IoT) platform to build an intelligent system that aims to detect the temperature rise of home appliances. It is employed to monitor the usage states of home appliances in real time. Hereby, the microcontroller, node microcontrol unit (NodeMCU-32S), is used to develop an IoT platform combined with sensors for measuring ac voltage, current, and ambient temperature so that the electrical power and temperature rise of load (e.g., electric motor) can be detected. Meanwhile, the smart measurement system is integrated with mobile devices to upload the detected datasets to the Google cloud database system. Moreover, the verification of feasibility and soundness of a system model is performed by using the Petri net tool, WoPeD, for the purpose of eliminating the improper states to optimize the system performance. Finally, the experimental results show that the proposed IoT-enabled system has a promising precision of 94.17% and a recall of 92.26%, which obviously outperforms other existing state-of-the-art systems.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"204-215"},"PeriodicalIF":2.1,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144634683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-08DOI: 10.1109/ICJECE.2025.3573736
Shivateja Manala;Jeevanand Seshadrinath
Stator interturn fault (ITF) is the most common failure in electrical machines; if no prompt detection is implemented, it can cause catastrophic results. This work proposes a novel method in permanent magnet synchronous machine (PMSM) drives to detect the ITF, which is insular to speed and load variations. The proposed ITF technique is based on negative-sequence instantaneous reactive power (IRP) distortions. The sensorless control of the PMSM drive, while using field-oriented technique, uses the voltage and current information for rotor position estimation. This serves the dual purpose of controlling the drive and also in developing the diagnostic technique. The IRP distortion is calculated from dq-reference frame voltage distortions, which are estimated using Luenberger observer and dq-reference frame current distortions. The novel fault indicator is calculated based on the vector magnitude of dc components obtained from negative-sequence IRP distortions, which is insular to various speed and load conditions of the drive. The proposed ITF detection technique is experimentally validated under varying load and speed conditions of the sensorless field-oriented controlled (FOC) PMSM drive. Further, a comparison of the proposed ITF detection scheme with the dq-reference frame current residuals technique shows the superiority of the proposed ITF detection scheme under various speed and load conditions of the PMSM drive scheme; furthermore, the reliability of the proposed ITF detection technique under various noise conditions is also verified.
{"title":"Interturn Fault Diagnosis in Sensorless PMSM Drive Based on Negative-Sequence Reactive Power Distortions","authors":"Shivateja Manala;Jeevanand Seshadrinath","doi":"10.1109/ICJECE.2025.3573736","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3573736","url":null,"abstract":"Stator interturn fault (ITF) is the most common failure in electrical machines; if no prompt detection is implemented, it can cause catastrophic results. This work proposes a novel method in permanent magnet synchronous machine (PMSM) drives to detect the ITF, which is insular to speed and load variations. The proposed ITF technique is based on negative-sequence instantaneous reactive power (IRP) distortions. The sensorless control of the PMSM drive, while using field-oriented technique, uses the voltage and current information for rotor position estimation. This serves the dual purpose of controlling the drive and also in developing the diagnostic technique. The IRP distortion is calculated from dq-reference frame voltage distortions, which are estimated using Luenberger observer and dq-reference frame current distortions. The novel fault indicator is calculated based on the vector magnitude of dc components obtained from negative-sequence IRP distortions, which is insular to various speed and load conditions of the drive. The proposed ITF detection technique is experimentally validated under varying load and speed conditions of the sensorless field-oriented controlled (FOC) PMSM drive. Further, a comparison of the proposed ITF detection scheme with the dq-reference frame current residuals technique shows the superiority of the proposed ITF detection scheme under various speed and load conditions of the PMSM drive scheme; furthermore, the reliability of the proposed ITF detection technique under various noise conditions is also verified.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"216-225"},"PeriodicalIF":2.1,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144634682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-08DOI: 10.1109/ICJECE.2025.3578113
Ayaz Ahmad;Jayanta Mukherjee
In this work, a meander line (ML) periodic leaky wave antenna (LWA) is proposed with gain improvement and broadside scanning capability. A longer ML length is taken in a fixed unit cell period to improve the gain. A longer ML brings more space harmonics (SHs) in the radiation region. Therefore, the geometry of the ML is modified to obtain impedance matching at SHs transition frequencies at 8.35 and 10.45 GHz. The antenna covers the frequency range from 8 to 11 GHz in the X-band with the optimized broadside frequency ($f_{B}$ ) at 9.4 GHz. A maximum gain of 15.5 dBi is achieved in $6.25lambda _{0}$ antenna length. This antenna is a potential candidate for use in modern wireless communication where high gain is required in a small footprint area.
{"title":"Modified Meander Line Broadside Scanning Periodic Leaky Wave Antenna With Gain Enhancement","authors":"Ayaz Ahmad;Jayanta Mukherjee","doi":"10.1109/ICJECE.2025.3578113","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3578113","url":null,"abstract":"In this work, a meander line (ML) periodic leaky wave antenna (LWA) is proposed with gain improvement and broadside scanning capability. A longer ML length is taken in a fixed unit cell period to improve the gain. A longer ML brings more space harmonics (SHs) in the radiation region. Therefore, the geometry of the ML is modified to obtain impedance matching at SHs transition frequencies at 8.35 and 10.45 GHz. The antenna covers the frequency range from 8 to 11 GHz in the X-band with the optimized broadside frequency (<inline-formula> <tex-math>$f_{B}$ </tex-math></inline-formula>) at 9.4 GHz. A maximum gain of 15.5 dBi is achieved in <inline-formula> <tex-math>$6.25lambda _{0}$ </tex-math></inline-formula> antenna length. This antenna is a potential candidate for use in modern wireless communication where high gain is required in a small footprint area.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"226-233"},"PeriodicalIF":2.1,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144634723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-30DOI: 10.1109/ICJECE.2025.3572936
Krishna Velmajala;Srinivasa Rao Sandepudi
This article introduces a high step-up interleaved p-type nonisolated dc–dc converter that achieves fault-tolerant operation without relying on redundant switches. The proposed converter design offers several advantages, including high voltage gain, improved efficiency, lower voltage stress on components, lower peak-to-peak input current, mitigates voltage oscillations across switches, and inherent common grounding making it suitable for a wide range of applications. The converter ensures uniform current sharing across its inductors and improves its reliability. Its scalable nature allows for the addition of stages to meet higher voltage and power requirements. The controller is designed to reduce transients during steady state and fault conditions to ensure stable operation. To achieve fault tolerance without extra switches, the design integrates a fuse-MOSFET combination for effective short-circuit protection. A 400-W prototype has been designed, built, and tested successfully demonstrating the converter functionality under normal and fault conditions.
{"title":"A High Step-Up Interleaved p-Type Nonisolated DC–DC Converter With Reconfiguration Capability","authors":"Krishna Velmajala;Srinivasa Rao Sandepudi","doi":"10.1109/ICJECE.2025.3572936","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3572936","url":null,"abstract":"This article introduces a high step-up interleaved p-type nonisolated dc–dc converter that achieves fault-tolerant operation without relying on redundant switches. The proposed converter design offers several advantages, including high voltage gain, improved efficiency, lower voltage stress on components, lower peak-to-peak input current, mitigates voltage oscillations across switches, and inherent common grounding making it suitable for a wide range of applications. The converter ensures uniform current sharing across its inductors and improves its reliability. Its scalable nature allows for the addition of stages to meet higher voltage and power requirements. The controller is designed to reduce transients during steady state and fault conditions to ensure stable operation. To achieve fault tolerance without extra switches, the design integrates a fuse-MOSFET combination for effective short-circuit protection. A 400-W prototype has been designed, built, and tested successfully demonstrating the converter functionality under normal and fault conditions.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"192-203"},"PeriodicalIF":2.1,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144606209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-16DOI: 10.1109/ICJECE.2025.3566877
{"title":"IEEE Canadian Journal of Electrical and Computer Engineering","authors":"","doi":"10.1109/ICJECE.2025.3566877","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3566877","url":null,"abstract":"","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 2","pages":"C2-C2"},"PeriodicalIF":2.1,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11037607","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144299213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-13DOI: 10.1109/ICJECE.2025.3570443
Shailendra Yadav;Brajesh Kumar Kaushik;Amita Giri
The CMOS-based neuromorphic computing system (NCS) face significant challenges, such as increasing energy usage and vast area footprints, surpassing the efficiency of biological brains. Spin transfer torque magnetic tunnel junction (STT-MTJ), a type of spin device, offers convenient benefits, including nonvolatility, increased energy efficiency, increased speed of operation, and compatibility with CMOS, making them ideal for energy-efficient spiking NCSs that exhibit neuronal behavior. However, the high energy consumption in spintronic-based NCS, primarily due to the high write current required for MTJ switching, remains a significant challenge as neurons in these systems tend to stay active longer than necessary. To address this challenge, we introduce a novel hybrid STT-MTJ/CMOS write terminate circuit (SM-WTC) that efficiently terminates the MTJ current efficiently after MTJ-state switches, significantly improving energy consumption and speed by $2.6times $ and $2.3times $ , compared to conventional NCSs. The proposed SM-WTC technique achieves energy consumption reductions of 52.7%, 58.3%, and 62.18% compared to prior work in real-time sensing (RTS) circuit, common-mode tracking and terminating circuit (CM-TTC), and conventional-NCS, respectively. A Cadence Virtuoso simulation using 65-nm CMOS technology has been used to evaluate the proposed circuit. Furthermore, SM-WTC-based NCS achieves a 67.2% improvement in energy-delay product (EDP) over conventional NCS for image edge detection. These advancements position SM-WTC as a commercially viable solution for next-generation artificial intelligence (AI) accelerators and brain-inspired computing architecture.
{"title":"Energy-Efficient Hybrid STT-MTJ/CMOS Circuit for Machine Learning-Assisted Neuromorphic Computing Applications","authors":"Shailendra Yadav;Brajesh Kumar Kaushik;Amita Giri","doi":"10.1109/ICJECE.2025.3570443","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3570443","url":null,"abstract":"The CMOS-based neuromorphic computing system (NCS) face significant challenges, such as increasing energy usage and vast area footprints, surpassing the efficiency of biological brains. Spin transfer torque magnetic tunnel junction (STT-MTJ), a type of spin device, offers convenient benefits, including nonvolatility, increased energy efficiency, increased speed of operation, and compatibility with CMOS, making them ideal for energy-efficient spiking NCSs that exhibit neuronal behavior. However, the high energy consumption in spintronic-based NCS, primarily due to the high write current required for MTJ switching, remains a significant challenge as neurons in these systems tend to stay active longer than necessary. To address this challenge, we introduce a novel hybrid STT-MTJ/CMOS write terminate circuit (SM-WTC) that efficiently terminates the MTJ current efficiently after MTJ-state switches, significantly improving energy consumption and speed by <inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.3times $ </tex-math></inline-formula>, compared to conventional NCSs. The proposed SM-WTC technique achieves energy consumption reductions of 52.7%, 58.3%, and 62.18% compared to prior work in real-time sensing (RTS) circuit, common-mode tracking and terminating circuit (CM-TTC), and conventional-NCS, respectively. A Cadence Virtuoso simulation using 65-nm CMOS technology has been used to evaluate the proposed circuit. Furthermore, SM-WTC-based NCS achieves a 67.2% improvement in energy-delay product (EDP) over conventional NCS for image edge detection. These advancements position SM-WTC as a commercially viable solution for next-generation artificial intelligence (AI) accelerators and brain-inspired computing architecture.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"184-191"},"PeriodicalIF":2.1,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144481833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/ICJECE.2025.3567092
Rishabh Bansal;Rushiv Bansal;Mayank Kumar
In this article, a novel bidirectional boost-side interleaved switched boost (BBSISB) multiport converter is proposed. The boost-side interleaving (BSI) of the converter improves its performance in terms of input current ripple and reliability in medium-power applications. The BSI reduces the input current ripple (i.e., zero at 50% of duty ratio), and it also provides an open circuit (OC) switch fault-tolerance index (FTI) of 100% at the load end. The switched-boost action topology uses time multiplexing of boost and buck switches to produce regulated voltage at output ports, whereas the boost-side phase interleaving provides the paralleling of large input boost current with reduced current ripple. The bidirectional capability of the converter enables the power flow from the battery to the load end in the absence of an input supply. The performance analysis of the proposed converter with respect to switching loss, conduction loss, FTI, current ripple, and cost is performed and compared with similar converters. An experimental setup of the BBSISB multiport converter is developed in the laboratory with a constant-current, constant-voltage (CC-CV) mode of charging of the battery to verify the derived analytical results.
{"title":"Improved Reliability and Performance Evaluation of Switched-Boost Multiport Converter Using Time-Multiplexing Control","authors":"Rishabh Bansal;Rushiv Bansal;Mayank Kumar","doi":"10.1109/ICJECE.2025.3567092","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3567092","url":null,"abstract":"In this article, a novel bidirectional boost-side interleaved switched boost (BBSISB) multiport converter is proposed. The boost-side interleaving (BSI) of the converter improves its performance in terms of input current ripple and reliability in medium-power applications. The BSI reduces the input current ripple (i.e., zero at 50% of duty ratio), and it also provides an open circuit (OC) switch fault-tolerance index (FTI) of 100% at the load end. The switched-boost action topology uses time multiplexing of boost and buck switches to produce regulated voltage at output ports, whereas the boost-side phase interleaving provides the paralleling of large input boost current with reduced current ripple. The bidirectional capability of the converter enables the power flow from the battery to the load end in the absence of an input supply. The performance analysis of the proposed converter with respect to switching loss, conduction loss, FTI, current ripple, and cost is performed and compared with similar converters. An experimental setup of the BBSISB multiport converter is developed in the laboratory with a constant-current, constant-voltage (CC-CV) mode of charging of the battery to verify the derived analytical results.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"167-175"},"PeriodicalIF":2.1,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144308520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/ICJECE.2025.3568042
Bandi Narasimha Rao;Anuradha Sundru
The classical orthogonal frequency division multiplexing (OFDM) systems gained significant new dimensions with the introduction of index modulation (IM) schemes. However, reduced data rates are the drawback in IM-based systems when implemented using higher-order modulation techniques. Hence, to improve the data rate, we proposed a new OFDM-IM system by varying the inactive subcarriers in in-phase and quadrature-phase in every subblock, namely, a dual-mode homogenous OFDM-IM (DMH OFDM-IM) system. Furthermore, we introduce a novel noise power and signal-to-noise ratio (SNR) estimation algorithm for the proposed system, which operates over a Nakagami-m fading channel. The proposed estimation algorithm makes use of nulled subcarriers available in every subblock of the proposed system to estimate noise power. The introduced estimator is both spectral and energy efficient as it uses inactive subcarriers that carry no energy. Simulation results emphasize that the developed estimator achieves lower noise power and estimates the SNR at an ideal value in contrast to the existing estimators of OFDM system. Moreover, differential noise power (DNP) is determined for the proposed system (DMH OFDM-IM) to track channel variations effectively.
{"title":"A Spectral and Energy Efficient Noise Variance and SNR Estimator for DMH OFDM-IM Systems","authors":"Bandi Narasimha Rao;Anuradha Sundru","doi":"10.1109/ICJECE.2025.3568042","DOIUrl":"https://doi.org/10.1109/ICJECE.2025.3568042","url":null,"abstract":"The classical orthogonal frequency division multiplexing (OFDM) systems gained significant new dimensions with the introduction of index modulation (IM) schemes. However, reduced data rates are the drawback in IM-based systems when implemented using higher-order modulation techniques. Hence, to improve the data rate, we proposed a new OFDM-IM system by varying the inactive subcarriers in in-phase and quadrature-phase in every subblock, namely, a dual-mode homogenous OFDM-IM (DMH OFDM-IM) system. Furthermore, we introduce a novel noise power and signal-to-noise ratio (SNR) estimation algorithm for the proposed system, which operates over a Nakagami-m fading channel. The proposed estimation algorithm makes use of nulled subcarriers available in every subblock of the proposed system to estimate noise power. The introduced estimator is both spectral and energy efficient as it uses inactive subcarriers that carry no energy. Simulation results emphasize that the developed estimator achieves lower noise power and estimates the SNR at an ideal value in contrast to the existing estimators of OFDM system. Moreover, differential noise power (DNP) is determined for the proposed system (DMH OFDM-IM) to track channel variations effectively.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"48 3","pages":"176-183"},"PeriodicalIF":2.1,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144308521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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