Pub Date : 2022-11-09DOI: 10.1109/ICJECE.2022.3211760
Hossam Hassanein;Shahrokh Valaee
Welcome to a Special Issue of the IEEE Canadian Journal of Electrical and Computer Engineering (IEEE-CJECE), which presents articles in the research areas of the Journal’s Former Area Editor, Dr. Sameh Sourour, in his memorial. Sameh Sorour was with the School of Computing at Queen’s University, Kingston, ON, Canada, where he was leading research in mobile edge computing, edge learning and autonomous vehicles with funding from federal, provincial and industry sources. He received his B.Sc. and M.Sc. degrees from Alexandria University, Alexandria, Egypt, in 2002 and 2006, respectively, and the Ph.D. from the University of Toronto, Toronto, ON, Canada, in 2011. His Ph.D. thesis was nominated for the Governor General’s Gold Medal Award. After his graduation, he held a MITACS industrial postdoctoral fellowship with Siradel Canada and the University of Toronto. Prior to moving to Queen’s University in 2019, he held another postdoctoral fellowship at the King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia, a Lecturer position at the King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, Saudi Arabia, and an Assistant Professor position at the University of Idaho, Moscow, ID, USA. During his Ph.D. degree and postdoctoral fellowships, he led several research projects with industrial partners and government agencies, such as LG Korea, the European Space Agency, the Canadian National Institute for the Blind (CNIB), and Siradel France. Dr. Sorour was a Senior Member of the IEEE and an Editor for IEEE Communications Letters. Also, he was an Area Editor in the IEEE-CJECE. His research and educational interests lied in the broad areas of advanced computing, learning, and networking technologies for cyber-physical and autonomous systems. The Guest Editors of this issue are 1) Prof. Hossam Hassanein, Director of School of Computing, Queen’s University, where Dr. Sorour held his last academic title; 2) Prof. Shahrokh Valaee, the Ph.D. advisor of Dr. Sourour at the University of Toronto.
{"title":"Guest Editorial Special Edition of the IEEE-CJECE","authors":"Hossam Hassanein;Shahrokh Valaee","doi":"10.1109/ICJECE.2022.3211760","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3211760","url":null,"abstract":"Welcome to a Special Issue of the IEEE Canadian Journal of Electrical and Computer Engineering (IEEE-CJECE), which presents articles in the research areas of the Journal’s Former Area Editor, Dr. Sameh Sourour, in his memorial. Sameh Sorour was with the School of Computing at Queen’s University, Kingston, ON, Canada, where he was leading research in mobile edge computing, edge learning and autonomous vehicles with funding from federal, provincial and industry sources. He received his B.Sc. and M.Sc. degrees from Alexandria University, Alexandria, Egypt, in 2002 and 2006, respectively, and the Ph.D. from the University of Toronto, Toronto, ON, Canada, in 2011. His Ph.D. thesis was nominated for the Governor General’s Gold Medal Award. After his graduation, he held a MITACS industrial postdoctoral fellowship with Siradel Canada and the University of Toronto. Prior to moving to Queen’s University in 2019, he held another postdoctoral fellowship at the King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia, a Lecturer position at the King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, Saudi Arabia, and an Assistant Professor position at the University of Idaho, Moscow, ID, USA. During his Ph.D. degree and postdoctoral fellowships, he led several research projects with industrial partners and government agencies, such as LG Korea, the European Space Agency, the Canadian National Institute for the Blind (CNIB), and Siradel France. Dr. Sorour was a Senior Member of the IEEE and an Editor for IEEE Communications Letters. Also, he was an Area Editor in the IEEE-CJECE. His research and educational interests lied in the broad areas of advanced computing, learning, and networking technologies for cyber-physical and autonomous systems. The Guest Editors of this issue are 1) Prof. Hossam Hassanein, Director of School of Computing, Queen’s University, where Dr. Sorour held his last academic title; 2) Prof. Shahrokh Valaee, the Ph.D. advisor of Dr. Sourour at the University of Toronto.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"191-191"},"PeriodicalIF":0.0,"publicationDate":"2022-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9349829/9944186/09944387.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-07DOI: 10.1109/ICJECE.2022.3195957
Ahmed Wagdy Shaban;Mohamed Seif;Tamer Khattab;Amr El-Keyi;Mohammed Nafie;Nizar Zorba
The coexistence of communication and sensing services in the next wireless communication systems, i.e., beyond 5G and 6G systems, revive the central role of interference management techniques such as interference alignment, coordinated multipoint transmission, and cell-free massive multiple-input–multiple-output (MIMO), in defeating interference and achieving the network capacity. In this article, we consider the <inline-formula> <tex-math>$K$ </tex-math></inline-formula> -user single-input–single-output (SISO) X-channel and its variants ( <inline-formula> <tex-math>$2 times K$ </tex-math></inline-formula> and <inline-formula> <tex-math>$K times 2$ </tex-math></inline-formula> ) in fast-fading environments. This can theoretically model many practical use cases for beyond 5G and 6G networks. For instance, it can model the case of having <inline-formula> <tex-math>$K$ </tex-math></inline-formula> cars communicating with another <inline-formula> <tex-math>$K$ </tex-math></inline-formula> cars, while former cars are sensing environment using the latter ones (in a cooperative, bistatic, and active approach) over the same time and frequency resources. We assume that the transmitters have access to synergistic alternating channel state information at the transmitter (CSIT) where it alternates between three states: perfect (P), delayed (D), and no-CSIT (N), and these states are associated with fractions of time denoted by <inline-formula> <tex-math>$lambda _{P}$ </tex-math></inline-formula> , <inline-formula> <tex-math>$lambda _{D}$ </tex-math></inline-formula> , and <inline-formula> <tex-math>$lambda _{N}$ </tex-math></inline-formula> , respectively. We develop novel degree-of-freedom (DoF) achievability schemes that exploit the synergy of the instantaneous CSIT and the delayed CSIT to retrospectively align interference in the subsequent channel uses. In particular, we show that the sum DoF of the <inline-formula> <tex-math>$K$ </tex-math></inline-formula> -user SISO X-channel is at least <inline-formula> <tex-math>${2K}/{K + 1}$ </tex-math></inline-formula> , using a two-phase transmission scheme over finite symbols channel extension and under a certain distribution of the CSIT availability of <inline-formula> <tex-math>$Lambda (lambda _{P}=({1}/{3}), lambda _{D}= ({1}/{3}), lambda _{N}=({1}/{3}))$ </tex-math></inline-formula> . This achievability result can be considered as a tight lower bound where it coincides with the best lower bound known for the same network but with partial output feedback instead of alternating CSIT. In addition, it shows that the role of synergistically alternating CSIT with distribution <inline-formula> <tex-math>$Lambda ({1}/{3},{1}/{3},{1}/{3})$ </tex-math></inline-formula> is equivalent to the one of the partial output feedback. Moreover, we show the optimality of the proposed two-phase-based scheme using a simple combinatorial proof. This establishes a DoF lower bound, which is strictly better than the bes
{"title":"On the DoF of X-Networks With Synergistic Alternating CSIT: A Step Towards Integrated Communication and Sensing","authors":"Ahmed Wagdy Shaban;Mohamed Seif;Tamer Khattab;Amr El-Keyi;Mohammed Nafie;Nizar Zorba","doi":"10.1109/ICJECE.2022.3195957","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3195957","url":null,"abstract":"The coexistence of communication and sensing services in the next wireless communication systems, i.e., beyond 5G and 6G systems, revive the central role of interference management techniques such as interference alignment, coordinated multipoint transmission, and cell-free massive multiple-input–multiple-output (MIMO), in defeating interference and achieving the network capacity. In this article, we consider the \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000-user single-input–single-output (SISO) X-channel and its variants (\u0000<inline-formula> <tex-math>$2 times K$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$K times 2$ </tex-math></inline-formula>\u0000) in fast-fading environments. This can theoretically model many practical use cases for beyond 5G and 6G networks. For instance, it can model the case of having \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000 cars communicating with another \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000 cars, while former cars are sensing environment using the latter ones (in a cooperative, bistatic, and active approach) over the same time and frequency resources. We assume that the transmitters have access to synergistic alternating channel state information at the transmitter (CSIT) where it alternates between three states: perfect (P), delayed (D), and no-CSIT (N), and these states are associated with fractions of time denoted by \u0000<inline-formula> <tex-math>$lambda _{P}$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$lambda _{D}$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$lambda _{N}$ </tex-math></inline-formula>\u0000, respectively. We develop novel degree-of-freedom (DoF) achievability schemes that exploit the synergy of the instantaneous CSIT and the delayed CSIT to retrospectively align interference in the subsequent channel uses. In particular, we show that the sum DoF of the \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000-user SISO X-channel is at least \u0000<inline-formula> <tex-math>${2K}/{K + 1}$ </tex-math></inline-formula>\u0000, using a two-phase transmission scheme over finite symbols channel extension and under a certain distribution of the CSIT availability of \u0000<inline-formula> <tex-math>$Lambda (lambda _{P}=({1}/{3}), lambda _{D}= ({1}/{3}), lambda _{N}=({1}/{3}))$ </tex-math></inline-formula>\u0000. This achievability result can be considered as a tight lower bound where it coincides with the best lower bound known for the same network but with partial output feedback instead of alternating CSIT. In addition, it shows that the role of synergistically alternating CSIT with distribution \u0000<inline-formula> <tex-math>$Lambda ({1}/{3},{1}/{3},{1}/{3})$ </tex-math></inline-formula>\u0000 is equivalent to the one of the partial output feedback. Moreover, we show the optimality of the proposed two-phase-based scheme using a simple combinatorial proof. This establishes a DoF lower bound, which is strictly better than the bes","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"199-214"},"PeriodicalIF":0.0,"publicationDate":"2022-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9349829/9944186/09940485.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/ICJECE.2022.3200146
Syed Sabir Hussain Bukhari;Madad Ali Shah;Jorge Rodas;Mohit Bajaj;Jong-Suk Ro
This article aims to realize a self-excited wound rotor synchronous machine (WRSM) topology established while considering the subharmonic field excitation scheme. Unlike the conventional subharmonic-based brushless WRSMs that require a dual-inverter configuration, the proposed topology uses a single inverter and a dual-armature winding pattern. The employed dual-armature winding configuration involves a four-pole main armature winding (ABC) and a two-pole open winding (X). The ABC winding is supplied with a three-phase current from a single customary current source inverter (CSI), whereas the X winding carries no current due to its open winding pattern and is responsible for generating subharmonic magnetomotive force (MMF) in the air gap along with the fundamental-harmonic MMF. The fundamental-harmonic MMF is utilized to create a four-pole stator field, while the subharmonic MMF is used to induce the harmonic current in the two-pole harmonic winding of the rotor. The generated harmonic current is rectified to energize the rotor field winding and develop a four-pole rotor field. The electromagnetic interaction of the four-pole stator and rotor fields generates torque. As the proposed subharmonic-based self-excited brushless WRSM employs a single inverter for its brushless operation, this makes it cost-effective compared to the conventional dual-inverter subharmonic-based brushless WRSM topologies. The proposed self-excited brushless WRSM topology is validated through the finite-element analysis (FEA). JMAG-Designer tool is employed to carry out FEA for a four-pole, 24-slot (4p24s) machine. The quantitative relative performance evaluation of the proposed self-excited WRSM topology with the recently developed dual-inverter-controlled subharmonic-based brushless WRSM topology is presented to show its better performance in terms of average, maximum, and minimum torques and torque ripple.
{"title":"Novel Sub-Harmonic-Based Self-Excited Brushless Wound Rotor Synchronous Machine","authors":"Syed Sabir Hussain Bukhari;Madad Ali Shah;Jorge Rodas;Mohit Bajaj;Jong-Suk Ro","doi":"10.1109/ICJECE.2022.3200146","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3200146","url":null,"abstract":"This article aims to realize a self-excited wound rotor synchronous machine (WRSM) topology established while considering the subharmonic field excitation scheme. Unlike the conventional subharmonic-based brushless WRSMs that require a dual-inverter configuration, the proposed topology uses a single inverter and a dual-armature winding pattern. The employed dual-armature winding configuration involves a four-pole main armature winding (ABC) and a two-pole open winding (X). The ABC winding is supplied with a three-phase current from a single customary current source inverter (CSI), whereas the X winding carries no current due to its open winding pattern and is responsible for generating subharmonic magnetomotive force (MMF) in the air gap along with the fundamental-harmonic MMF. The fundamental-harmonic MMF is utilized to create a four-pole stator field, while the subharmonic MMF is used to induce the harmonic current in the two-pole harmonic winding of the rotor. The generated harmonic current is rectified to energize the rotor field winding and develop a four-pole rotor field. The electromagnetic interaction of the four-pole stator and rotor fields generates torque. As the proposed subharmonic-based self-excited brushless WRSM employs a single inverter for its brushless operation, this makes it cost-effective compared to the conventional dual-inverter subharmonic-based brushless WRSM topologies. The proposed self-excited brushless WRSM topology is validated through the finite-element analysis (FEA). JMAG-Designer tool is employed to carry out FEA for a four-pole, 24-slot (4p24s) machine. The quantitative relative performance evaluation of the proposed self-excited WRSM topology with the recently developed dual-inverter-controlled subharmonic-based brushless WRSM topology is presented to show its better performance in terms of average, maximum, and minimum torques and torque ripple.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 4","pages":"365-374"},"PeriodicalIF":0.0,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68030717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-13DOI: 10.1109/ICJECE.2022.3199227
Shady Younan;Mervat Abu-Elkheir
Tracking human daily activities is a useful functionality supported in many applications, especially with the pervasive use of wearable devices. State-of-the-art human activity recognition (HAR) uses machine or deep learning techniques to identify activities based on sensor readings. However, these models represent patterns from standardized experiment setups, with limited diversity when it comes to the individuals involved in data collection. This leads to limited success of HAR in real deployment scenarios, where individuals perform the same activity in different ways. Training models from scratch on real-time data streams is challenging due to the computational complexity of machine and deep learning architectures. In this article, we propose an incremental learning model for HAR that tweaks a deep learning model pretrained on a standardized HAR dataset and incrementally trains on newly generated individuals personalized data on their personal devices. The proposed solution promotes the preservation of data privacy, improves the model performance in terms of accuracy and efficiency without having to retrain from scratch, and tweaks the model according to personalized activity patterns. Extensive experiments show improvement of the base model’s accuracy up to 19% after incrementally training the model on filtered users’ datasets for the standing, walking, and running activities.
{"title":"Deep Incremental Learning for Personalized Human Activity Recognition on Edge Devices","authors":"Shady Younan;Mervat Abu-Elkheir","doi":"10.1109/ICJECE.2022.3199227","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3199227","url":null,"abstract":"Tracking human daily activities is a useful functionality supported in many applications, especially with the pervasive use of wearable devices. State-of-the-art human activity recognition (HAR) uses machine or deep learning techniques to identify activities based on sensor readings. However, these models represent patterns from standardized experiment setups, with limited diversity when it comes to the individuals involved in data collection. This leads to limited success of HAR in real deployment scenarios, where individuals perform the same activity in different ways. Training models from scratch on real-time data streams is challenging due to the computational complexity of machine and deep learning architectures. In this article, we propose an incremental learning model for HAR that tweaks a deep learning model pretrained on a standardized HAR dataset and incrementally trains on newly generated individuals personalized data on their personal devices. The proposed solution promotes the preservation of data privacy, improves the model performance in terms of accuracy and efficiency without having to retrain from scratch, and tweaks the model according to personalized activity patterns. Extensive experiments show improvement of the base model’s accuracy up to 19% after incrementally training the model on filtered users’ datasets for the standing, walking, and running activities.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"215-221"},"PeriodicalIF":0.0,"publicationDate":"2022-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents, a mutual coupling reduction technique between a very closely spaced (1.8 mm) two-element microstrip-based multiple-input multiple-output (MIMO) antennas using a modified inverted-fork-shaped decoupling (m-IFSD) structure. The m-IFSD structure consists of an inverted fork and a cross-shaped structure with a shorted via. The combined effect of inverted-fork and shorted cross-shaped structure results in mutual coupling reduction below −35 dB between adjacent antenna elements. The decoupling technique is analyzed using an approximate transmission-line model and field distribution. Furthermore, the two-element MIMO antenna design is extended to an eight-element MIMO configuration to improve the MIMO diversity. To verify the proposed isolation technique a two-element MIMO antenna prototype is fabricated and measured. The proposed MIMO antenna exhibits a low mutual coupling (<−35 dB) with good impedance matching (<−10 dB) at 5.45 GHz. The MIMO antenna provided a total active reflection coefficient (TARC) less than −10 dB and envelop correlation coefficient (ECC) (for isotropic propagation scenario) less than 0.5. Finally, the ECC of the proposed MIMO antenna system is analyzed for a realistic Gaussian/uniform propagation scenario for various incidence angles and angular spreads to better understand the effect of the mutual coupling reduction technique.
{"title":"MIMO Antenna Mutual Coupling Reduction Using Modified Inverted-Fork Shaped Structure","authors":"Jogesh Chandra Dash;Shilpa Kharche;G. Shrikanth Reddy","doi":"10.1109/ICJECE.2022.3201054","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3201054","url":null,"abstract":"This article presents, a mutual coupling reduction technique between a very closely spaced (1.8 mm) two-element microstrip-based multiple-input multiple-output (MIMO) antennas using a modified inverted-fork-shaped decoupling (m-IFSD) structure. The m-IFSD structure consists of an inverted fork and a cross-shaped structure with a shorted via. The combined effect of inverted-fork and shorted cross-shaped structure results in mutual coupling reduction below −35 dB between adjacent antenna elements. The decoupling technique is analyzed using an approximate transmission-line model and field distribution. Furthermore, the two-element MIMO antenna design is extended to an eight-element MIMO configuration to improve the MIMO diversity. To verify the proposed isolation technique a two-element MIMO antenna prototype is fabricated and measured. The proposed MIMO antenna exhibits a low mutual coupling (<−35 dB) with good impedance matching (<−10 dB) at 5.45 GHz. The MIMO antenna provided a total active reflection coefficient (TARC) less than −10 dB and envelop correlation coefficient (ECC) (for isotropic propagation scenario) less than 0.5. Finally, the ECC of the proposed MIMO antenna system is analyzed for a realistic Gaussian/uniform propagation scenario for various incidence angles and angular spreads to better understand the effect of the mutual coupling reduction technique.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 4","pages":"375-382"},"PeriodicalIF":0.0,"publicationDate":"2022-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68030718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-12DOI: 10.1109/ICJECE.2022.3206393
Mhd Saria Allahham;Amr Mohamed;Aiman Erbad;Mohsen Guizani
Mobile edge learning (MEL) is a learning paradigm that enables distributed training of machine learning (ML) models over heterogeneous edge devices (e.g., IoT devices). Multiorchestrator MEL refers to the coexistence of multiple learning tasks with different datasets, each of which being governed by an orchestrator to facilitate the distributed training process. In MEL, the training performance deteriorates without the availability of sufficient training data or computing resources. Therefore, it is crucial to motivate edge devices to become learners and offer their computing resources, and either offer their private data or receive the needed data from the orchestrator and participate in the training process of a learning task. In this work, we propose an incentive mechanism, where we formulate the orchestrators-learners’ interactions as a 2-round Stackelberg game to motivate the participation of the learners. In the first round, the learners decide which learning task to get engaged in, and then in the second round, the training parameters and the amount of data for training in case of participation such that their utility is maximized. We then study the training round analytically and derive the learners’ optimal strategy. Finally, numerical experiments have been conducted to evaluate the performance of the proposed incentive mechanism.
{"title":"Motivating Learners in Multiorchestrator Mobile Edge Learning: A Stackelberg Game Approach","authors":"Mhd Saria Allahham;Amr Mohamed;Aiman Erbad;Mohsen Guizani","doi":"10.1109/ICJECE.2022.3206393","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3206393","url":null,"abstract":"Mobile edge learning (MEL) is a learning paradigm that enables distributed training of machine learning (ML) models over heterogeneous edge devices (e.g., IoT devices). Multiorchestrator MEL refers to the coexistence of multiple learning tasks with different datasets, each of which being governed by an orchestrator to facilitate the distributed training process. In MEL, the training performance deteriorates without the availability of sufficient training data or computing resources. Therefore, it is crucial to motivate edge devices to become learners and offer their computing resources, and either offer their private data or receive the needed data from the orchestrator and participate in the training process of a learning task. In this work, we propose an incentive mechanism, where we formulate the orchestrators-learners’ interactions as a 2-round Stackelberg game to motivate the participation of the learners. In the first round, the learners decide which learning task to get engaged in, and then in the second round, the training parameters and the amount of data for training in case of participation such that their utility is maximized. We then study the training round analytically and derive the learners’ optimal strategy. Finally, numerical experiments have been conducted to evaluate the performance of the proposed incentive mechanism.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"46 1","pages":"69-76"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68038580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-12DOI: 10.1109/ICJECE.2022.3199563
Christopher DeSantis;Ahmed Refaey Hussein
Speech classification acceleration using field-programmable gate arrays (FPGAs) is a well-studied field and enables the potential to gain both speed and better energy efficiency over other processor-intensive classifiers. System-on-chip (SoC) architecture allows for an integrated system between programmable logic and processor and for increased bandwidth communications to on- chip peripherals and memory. This article serves as an investigation of the utility of an edge-based support-vector machine (SVM) implemented onto a Zynq-XC7Z020 multiprocessor system on a chip (MPSoC) for the acceleration of three speech class pairs. The system allows for a parallelized structure, which yielded a faster classifier model. The results were found to be an acceleration factor of $2.08times $ . This appears to have come at the cost of a decrease in prediction accuracy, lowering from 92.5% to 83.5% positive prediction percentage likely due to decreased data resolution. The resolution used in this model was a 16-bit fixed-point format for the hardware interpretation and a floating-point format for the software benchmark. The resource usage of the FPGA was also analyzed for both overlays and can yield a 21% reduction in CPU usage. Résumé—L’accélération de la classification de la parole à l’aide de réseaux de portes programmables par l’utilisateur (FPGAs) est un domaine bien étudié et offre la possibilité de gagner à la fois en vitesse et en efficacité énergétique par rapport à d’autres classificateurs nécessitant un processeur. L’architecture système sur une puce (SoC) permet un système intégré entre la logique programmable et le processeur et une augmentation de la bande passante des communications vers les périphériques sur la puce et la mémoire. Cet article est une étude de l’utilité d’une machine à vecteur de support (SVM) basée sur les périphéries et mise en œuvre sur un système multiprocesseur Zynq-XC7Z020 sur une puce (MPSoC) pour l’accélération de trois paires de classes vocales. Le système permet une structure parallélisée, ce qui permet d’obtenir un modèle de classification plus rapide. Les résultats se sont révélés être un facteur d’accélération de 2, $08times $ . Cela semble s’être fait au prix d’une diminution de la précision de prédiction, passant de 92,5 % à 83,5 % de pourcentage de prédiction positive, probablement en raison de la diminution de la résolution des données. La résolution utilisée dans ce modèle était un format à virgule fixe de 16 bits pour l’interprétation matérielle et un format à virgule flottante pour le benchmark logiciel. L’utilisation des ressources du FPGA a également été analysée pour les deux superpositions et permet de réduire de 21 % l’utilisation du CPU.
{"title":"AI SoC-Based Accelerator for Speech Classification Accélérateur de classification de la parole basé sur un AI SoC","authors":"Christopher DeSantis;Ahmed Refaey Hussein","doi":"10.1109/ICJECE.2022.3199563","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3199563","url":null,"abstract":"Speech classification acceleration using field-programmable gate arrays (FPGAs) is a well-studied field and enables the potential to gain both speed and better energy efficiency over other processor-intensive classifiers. System-on-chip (SoC) architecture allows for an integrated system between programmable logic and processor and for increased bandwidth communications to on- chip peripherals and memory. This article serves as an investigation of the utility of an edge-based support-vector machine (SVM) implemented onto a Zynq-XC7Z020 multiprocessor system on a chip (MPSoC) for the acceleration of three speech class pairs. The system allows for a parallelized structure, which yielded a faster classifier model. The results were found to be an acceleration factor of \u0000<inline-formula> <tex-math>$2.08times $ </tex-math></inline-formula>\u0000. This appears to have come at the cost of a decrease in prediction accuracy, lowering from 92.5% to 83.5% positive prediction percentage likely due to decreased data resolution. The resolution used in this model was a 16-bit fixed-point format for the hardware interpretation and a floating-point format for the software benchmark. The resource usage of the FPGA was also analyzed for both overlays and can yield a 21% reduction in CPU usage. Résumé—L’accélération de la classification de la parole à l’aide de réseaux de portes programmables par l’utilisateur (FPGAs) est un domaine bien étudié et offre la possibilité de gagner à la fois en vitesse et en efficacité énergétique par rapport à d’autres classificateurs nécessitant un processeur. L’architecture système sur une puce (SoC) permet un système intégré entre la logique programmable et le processeur et une augmentation de la bande passante des communications vers les périphériques sur la puce et la mémoire. Cet article est une étude de l’utilité d’une machine à vecteur de support (SVM) basée sur les périphéries et mise en œuvre sur un système multiprocesseur Zynq-XC7Z020 sur une puce (MPSoC) pour l’accélération de trois paires de classes vocales. Le système permet une structure parallélisée, ce qui permet d’obtenir un modèle de classification plus rapide. Les résultats se sont révélés être un facteur d’accélération de 2,\u0000<inline-formula> <tex-math>$08times $ </tex-math></inline-formula>\u0000. Cela semble s’être fait au prix d’une diminution de la précision de prédiction, passant de 92,5 % à 83,5 % de pourcentage de prédiction positive, probablement en raison de la diminution de la résolution des données. La résolution utilisée dans ce modèle était un format à virgule fixe de 16 bits pour l’interprétation matérielle et un format à virgule flottante pour le benchmark logiciel. L’utilisation des ressources du FPGA a également été analysée pour les deux superpositions et permet de réduire de 21 % l’utilisation du CPU.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"222-231"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-12DOI: 10.1109/ICJECE.2022.3200075
Riadul Islam
At leading technology nodes, the industry is facing a stiff challenge to make profitable integrated circuits (ICs). One of the primary issues is the design rule checking (DRC) violation. This research cohort with the DARPA IDEA program aims for “no-human-in-the-loop” and 24-h turnaround time to implement an IC from design specifications. In order to reduce human effort, this work introduces the ensemble random forest, gradient boosting, and Adaboost algorithms to predict DRC violations before detailed routing, which is considered the most time-consuming step in an IC design flow. In addition, this work identifies the features that critically impact DRC violations. The proposed algorithm has a 2% better F1-score compared to the existing support-vector machine (SVM) classifiers. The proposed ensemble approach has up to an area-under-the-curve–receiver operating characteristics (AUC–ROC) curve mean of 0.940 with ± 0.011 standard deviation compared to the state-of-the-art SVM classifier with an AUC–ROC curve mean of 0.854 with ± 0.01 standard deviation. The proposed ensemble approach exhibits up to 28.7% better DRC violation prediction rate compared to those using SVM algorithms on the test data. In addition, the proposed gradient boosting algorithm requires $37.5times $ lower average training time and $50times $ lower average testing time compared to the existing SVM methodologies.
{"title":"Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms","authors":"Riadul Islam","doi":"10.1109/ICJECE.2022.3200075","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3200075","url":null,"abstract":"At leading technology nodes, the industry is facing a stiff challenge to make profitable integrated circuits (ICs). One of the primary issues is the design rule checking (DRC) violation. This research cohort with the DARPA IDEA program aims for “no-human-in-the-loop” and 24-h turnaround time to implement an IC from design specifications. In order to reduce human effort, this work introduces the ensemble random forest, gradient boosting, and Adaboost algorithms to predict DRC violations before detailed routing, which is considered the most time-consuming step in an IC design flow. In addition, this work identifies the features that critically impact DRC violations. The proposed algorithm has a 2% better F1-score compared to the existing support-vector machine (SVM) classifiers. The proposed ensemble approach has up to an area-under-the-curve–receiver operating characteristics (AUC–ROC) curve mean of 0.940 with ± 0.011 standard deviation compared to the state-of-the-art SVM classifier with an AUC–ROC curve mean of 0.854 with ± 0.01 standard deviation. The proposed ensemble approach exhibits up to 28.7% better DRC violation prediction rate compared to those using SVM algorithms on the test data. In addition, the proposed gradient boosting algorithm requires \u0000<inline-formula> <tex-math>$37.5times $ </tex-math></inline-formula>\u0000 lower average training time and \u0000<inline-formula> <tex-math>$50times $ </tex-math></inline-formula>\u0000 lower average testing time compared to the existing SVM methodologies.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 4","pages":"354-364"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68030715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/ICJECE.2022.3178749
Bruno Moraes Rocha;Gabriel S. Vieira;Afonso U. Fonseca;Naiane M. Sousa;Helio Pedrini;Fabrizzio Soares
Sugarcane is one of the main crops in the world due to its economic value promoted by the sale of its derivatives, such as bioethanol and sugar. In order to achieve greater economic performance and productivity in the sugarcane field, several digital image processing studies have been conducted on sugarcane field images. However, mapping and measuring gaps in the planting rows are still being performed manually on-site to determine whether to replant the entire area or only the gaps. High cost of time and manpower is required to perform the manual measurement. Based on that, the aim of this study is to present a novel method to detect crop rows and measure gaps in crop fields. Our method is also able to deal with curved crop rows, which is a real problem and substantially limits numerous solutions in practical applications. The proposed method is evaluated using a mosaic of real scene image that was prepared with the support of a small remotely piloted aircraft. Experimental tests showed a low relative error of approximately 1.65% compared to manual mapping in the planting regions, even for regions with gaps in the curved crop rows. It means that our proposal can identify and measure crop rows accurately, which enables automated inspections with high-precision measurements.
{"title":"Detection of Curved Rows and Gaps in Aerial Images of Sugarcane Field Using Image Processing Techniques","authors":"Bruno Moraes Rocha;Gabriel S. Vieira;Afonso U. Fonseca;Naiane M. Sousa;Helio Pedrini;Fabrizzio Soares","doi":"10.1109/ICJECE.2022.3178749","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3178749","url":null,"abstract":"Sugarcane is one of the main crops in the world due to its economic value promoted by the sale of its derivatives, such as bioethanol and sugar. In order to achieve greater economic performance and productivity in the sugarcane field, several digital image processing studies have been conducted on sugarcane field images. However, mapping and measuring gaps in the planting rows are still being performed manually on-site to determine whether to replant the entire area or only the gaps. High cost of time and manpower is required to perform the manual measurement. Based on that, the aim of this study is to present a novel method to detect crop rows and measure gaps in crop fields. Our method is also able to deal with curved crop rows, which is a real problem and substantially limits numerous solutions in practical applications. The proposed method is evaluated using a mosaic of real scene image that was prepared with the support of a small remotely piloted aircraft. Experimental tests showed a low relative error of approximately 1.65% compared to manual mapping in the planting regions, even for regions with gaps in the curved crop rows. It means that our proposal can identify and measure crop rows accurately, which enables automated inspections with high-precision measurements.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"303-310"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-09DOI: 10.1109/ICJECE.2022.3192312
Ali Mastanabadi;Gholamreza Aghajani;Davar Mirabbasi
Nowadays, with the increasing expansion of the power grid and the use of wind energy systems, the issue of frequency control of the power system in their presence is very important. In traditional power systems, the control of frequency is generally performed by hydroelectric power plants that are the slack bus of the grid. They usually have fast dynamic responses, capable of changing the power output rapidly. This can be difficult in cases such as drought, lack of large hydropower plants, or the expansion of the power grid. In this article, a new topology and control system for a wind farm connected to a four-area grid through an high voltage dc (HVdc) link is presented, which can participate in the issue of frequency control of the power system. The proposed system is based on maximum power point tracking (MPPT) and fine tune control of the permanent magnet synchronous generator (PMSG)-based wind farm. The simulation results were evaluated on a four-area power grid, they were compared with the absence of wind farm in frequency control, and the desired results with appropriate and acceptable dynamic responses were achieved. The simulation results were performed on the MATLAB/Simulink environment.
{"title":"Wind Farm Fast Response Contribution in Power Frequency Control, Using a New Configuration and Control System Based on MPPT and Fine Tune Power Algorithm","authors":"Ali Mastanabadi;Gholamreza Aghajani;Davar Mirabbasi","doi":"10.1109/ICJECE.2022.3192312","DOIUrl":"https://doi.org/10.1109/ICJECE.2022.3192312","url":null,"abstract":"Nowadays, with the increasing expansion of the power grid and the use of wind energy systems, the issue of frequency control of the power system in their presence is very important. In traditional power systems, the control of frequency is generally performed by hydroelectric power plants that are the slack bus of the grid. They usually have fast dynamic responses, capable of changing the power output rapidly. This can be difficult in cases such as drought, lack of large hydropower plants, or the expansion of the power grid. In this article, a new topology and control system for a wind farm connected to a four-area grid through an high voltage dc (HVdc) link is presented, which can participate in the issue of frequency control of the power system. The proposed system is based on maximum power point tracking (MPPT) and fine tune control of the permanent magnet synchronous generator (PMSG)-based wind farm. The simulation results were evaluated on a four-area power grid, they were compared with the absence of wind farm in frequency control, and the desired results with appropriate and acceptable dynamic responses were achieved. The simulation results were performed on the MATLAB/Simulink environment.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"339-348"},"PeriodicalIF":0.0,"publicationDate":"2022-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68033563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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