Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723085
S. Xia, R. Sridhar, P. Scott, C. Bandera
A foveal image sensor chip that uses a standard CMOS process is presented. A new photo charge normalization scheme and its associated circuitry for use with active pixel sensors has been developed. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision. A proof-of-concept chip has been fabricated and tested.
{"title":"An all CMOS foveal image sensor chip","authors":"S. Xia, R. Sridhar, P. Scott, C. Bandera","doi":"10.1109/ASIC.1998.723085","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723085","url":null,"abstract":"A foveal image sensor chip that uses a standard CMOS process is presented. A new photo charge normalization scheme and its associated circuitry for use with active pixel sensors has been developed. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision. A proof-of-concept chip has been fabricated and tested.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123989895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722901
T. Tsang, B. Rodriguez, G. Haag, H. Crafts
This paper covers the motivations for and the advantages of using an embedded DRAM compiler technology within a standard deep submicron logic process for System-on-a-Chip (SoC). We also discuss the bit cell design and the memory architecture, as well as the automation software and methodology used in the construction of the DRAM compiler. Silicon results from the test chips are favorable. This approach makes economical and time-to-market sense, therefore it can be a viable high-performance and area-efficient option in the embedded DRAM technology.
{"title":"A proven embedded DRAM compiler for deep submicron logic processes and system-on-a-chip ASIC designs","authors":"T. Tsang, B. Rodriguez, G. Haag, H. Crafts","doi":"10.1109/ASIC.1998.722901","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722901","url":null,"abstract":"This paper covers the motivations for and the advantages of using an embedded DRAM compiler technology within a standard deep submicron logic process for System-on-a-Chip (SoC). We also discuss the bit cell design and the memory architecture, as well as the automation software and methodology used in the construction of the DRAM compiler. Silicon results from the test chips are favorable. This approach makes economical and time-to-market sense, therefore it can be a viable high-performance and area-efficient option in the embedded DRAM technology.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128951065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722789
T. Matsukawa, M. Mizoguchi, K. Takeuchi
We have developed a Mitsubishi precision scale controller ASIC using a cell based IC. This scale is a position detector applied to industrial machines. The newly developed controller is manufactured using a 0.35 /spl mu/m process and operates at 140 MHz. It can improve the resolution of a scale by 10 times.
{"title":"Development of Mitsubishi precision scale controller","authors":"T. Matsukawa, M. Mizoguchi, K. Takeuchi","doi":"10.1109/ASIC.1998.722789","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722789","url":null,"abstract":"We have developed a Mitsubishi precision scale controller ASIC using a cell based IC. This scale is a position detector applied to industrial machines. The newly developed controller is manufactured using a 0.35 /spl mu/m process and operates at 140 MHz. It can improve the resolution of a scale by 10 times.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130747344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723033
L. Kiss, E. Hanssens, K. Adriaensen, M. Huysmans, C. Gendarme, E. Van Beylen, H. Van De Weghe
From Time domain to Atm domain, the complete digital signal processing required by ADSL technology has been integrated onto a single device called SACHEM. High programmability along with flexible architecture enable the device to serve for both network and line termination. Mapping on a 0.35 /spl mu/m standard digital CMOS technology makes SACHEM a cost effective solution as well as a low power device, consuming only 800 mW at 3.3 V.
{"title":"A customizable DSP for DMT-based ADSL modem","authors":"L. Kiss, E. Hanssens, K. Adriaensen, M. Huysmans, C. Gendarme, E. Van Beylen, H. Van De Weghe","doi":"10.1109/ASIC.1998.723033","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723033","url":null,"abstract":"From Time domain to Atm domain, the complete digital signal processing required by ADSL technology has been integrated onto a single device called SACHEM. High programmability along with flexible architecture enable the device to serve for both network and line termination. Mapping on a 0.35 /spl mu/m standard digital CMOS technology makes SACHEM a cost effective solution as well as a low power device, consuming only 800 mW at 3.3 V.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127672741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723091
A. Kahng, S. Muddut
DSM interconnects have a dominant impact on the achievable performance of integrated circuits. A broad spectrum of issues must be dealt with by design tools and methodologies to achieve successful outcomes. This tutorial develops the fundamentals of DSM interconnect modeling and analysis, starting with the underlying process technology and design methodology contexts, and continuing with interconnect performance and reliability analyses, frontend interconnect metrics and models, and modeling for interconnect synthesis and optimization. The tutorial’s intended audience consists of ASIC designers, design tool users, and CAD developers. The material will be presented in a form (slides, pseudocode fragments, reference lists) that attendees can take away and immediately use.
{"title":"Dsm Interconnect Modeling And Analysis For Performance And Reliability","authors":"A. Kahng, S. Muddut","doi":"10.1109/ASIC.1998.723091","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723091","url":null,"abstract":"DSM interconnects have a dominant impact on the achievable performance of integrated circuits. A broad spectrum of issues must be dealt with by design tools and methodologies to achieve successful outcomes. This tutorial develops the fundamentals of DSM interconnect modeling and analysis, starting with the underlying process technology and design methodology contexts, and continuing with interconnect performance and reliability analyses, frontend interconnect metrics and models, and modeling for interconnect synthesis and optimization. The tutorial’s intended audience consists of ASIC designers, design tool users, and CAD developers. The material will be presented in a form (slides, pseudocode fragments, reference lists) that attendees can take away and immediately use.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122336502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722785
S. Salomão, V. Alves, E. Filho
Data security is an important issue in today's computer networks. This paper presents the HiPCrypto chip, which implements the IDEA cryptographic algorithm. HiPCrypto is oriented towards computer network applications demanding high throughput. Its architecture exploits both the spatial and the temporal parallelism available in the IDEA algorithm. When operating at a 53 MHz clock, HiPCrypto can encrypt/decrypt at data rates up to 3.4 Gbps.
{"title":"HiPCrypto: a high-performance VLSI cryptographic chip","authors":"S. Salomão, V. Alves, E. Filho","doi":"10.1109/ASIC.1998.722785","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722785","url":null,"abstract":"Data security is an important issue in today's computer networks. This paper presents the HiPCrypto chip, which implements the IDEA cryptographic algorithm. HiPCrypto is oriented towards computer network applications demanding high throughput. Its architecture exploits both the spatial and the temporal parallelism available in the IDEA algorithm. When operating at a 53 MHz clock, HiPCrypto can encrypt/decrypt at data rates up to 3.4 Gbps.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722820
J. Chickanosky, R. Frye
The first two papers discuss novel buffer designs. One driver uses a capacitance feedback to control the output slew, reducing the power noise. The other buffer design utilizes a new CMOS logic circuit with a unique delay propagation characteristic that makes it much faster than conventional CMOS logic. There are two papers on SRAM circuit techniques. One paper presents a new approach based on current-mode to reduce energy and improve the speed of write and read access in multi-port SRAMS. The other SRAM paper presents a new currentmode sense amplifier design which can be used in the design of a low-voltage low power SRAM for ASIC applications.
{"title":"Novel Devices And Circuits","authors":"J. Chickanosky, R. Frye","doi":"10.1109/ASIC.1998.722820","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722820","url":null,"abstract":"The first two papers discuss novel buffer designs. One driver uses a capacitance feedback to control the output slew, reducing the power noise. The other buffer design utilizes a new CMOS logic circuit with a unique delay propagation characteristic that makes it much faster than conventional CMOS logic. There are two papers on SRAM circuit techniques. One paper presents a new approach based on current-mode to reduce energy and improve the speed of write and read access in multi-port SRAMS. The other SRAM paper presents a new currentmode sense amplifier design which can be used in the design of a low-voltage low power SRAM for ASIC applications.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722890
R. Auletta, Mely Chen Chi
Computer-aided design is central to ASIC design, supporting the design process from specification to implementation. The papers presented in this year’s CAD session reflect the broad importance of CAD in the ASIC design process, with papers addressing both the application of ASIC EDA tools, complete tool suites, and the algorithms they use. The session opens with a case study by Alcatel and Toshiba on CAD design methods for million gate systems. The session then addresses the application of CAD tools for the design of a Fast Discrete Cosine Transform and an embedded DRAM compiler for systems on a chip. Automatic layout synthesis and power estimation are covered in the next two papers. The first describes automatic layout of dynamic CMOS circuits and the second describes architectural estimation of power dissipation in processor control units. Finally the session closes with the presentation of papers on CAD algorithms, including a paper on incremental rerouting of mapped FPGA circuits and two papers on VLSI circuit partitioning. The first applies TABU intelligent problem solving to bipafl itioning, while the second reports on improved wirelengths by relaxing the traditional bisection constraint.
{"title":"Asic Cad Applications And Algorithms","authors":"R. Auletta, Mely Chen Chi","doi":"10.1109/ASIC.1998.722890","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722890","url":null,"abstract":"Computer-aided design is central to ASIC design, supporting the design process from specification to implementation. The papers presented in this year’s CAD session reflect the broad importance of CAD in the ASIC design process, with papers addressing both the application of ASIC EDA tools, complete tool suites, and the algorithms they use. The session opens with a case study by Alcatel and Toshiba on CAD design methods for million gate systems. The session then addresses the application of CAD tools for the design of a Fast Discrete Cosine Transform and an embedded DRAM compiler for systems on a chip. Automatic layout synthesis and power estimation are covered in the next two papers. The first describes automatic layout of dynamic CMOS circuits and the second describes architectural estimation of power dissipation in processor control units. Finally the session closes with the presentation of papers on CAD algorithms, including a paper on incremental rerouting of mapped FPGA circuits and two papers on VLSI circuit partitioning. The first applies TABU intelligent problem solving to bipafl itioning, while the second reports on improved wirelengths by relaxing the traditional bisection constraint.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128683009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722911
A. Caldwell, A. Kahng, I. Markov
Recent work of Simon and Teng (1997) observes that the recursive bisection (i.e., bipartitioning with equal partition target areas, and minimum possible allowed deviation from targets) heuristic for k-way minimum-cut graph partitioning can have unbounded error, but that relaxing the balance constraints in each call to the bipartitioning engine can result in k-way net cuts within a small (O(logk)) factor of optimal. Motivated by this result, we experimentally determine whether relaxing the traditional exact bisection constraint in a top-down partitioning-based placement tool can improve the resulting cutsizes, and hence total wirelength, of the placement solution. We find that this simple change reduces total wirelength by up to several percent, with no change in placement uniformity and under 10% runtime penalty. Finally, we observe that the stability (predictability) of the placement process appears unimpaired by this modification: both wirelength stability, and stability of Rent parameter based wirelength and wireability estimates, appear to be preserved.
{"title":"Relaxed partitioning balance constraints in top-down placement","authors":"A. Caldwell, A. Kahng, I. Markov","doi":"10.1109/ASIC.1998.722911","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722911","url":null,"abstract":"Recent work of Simon and Teng (1997) observes that the recursive bisection (i.e., bipartitioning with equal partition target areas, and minimum possible allowed deviation from targets) heuristic for k-way minimum-cut graph partitioning can have unbounded error, but that relaxing the balance constraints in each call to the bipartitioning engine can result in k-way net cuts within a small (O(logk)) factor of optimal. Motivated by this result, we experimentally determine whether relaxing the traditional exact bisection constraint in a top-down partitioning-based placement tool can improve the resulting cutsizes, and hence total wirelength, of the placement solution. We find that this simple change reduces total wirelength by up to several percent, with no change in placement uniformity and under 10% runtime penalty. Finally, we observe that the stability (predictability) of the placement process appears unimpaired by this modification: both wirelength stability, and stability of Rent parameter based wirelength and wireability estimates, appear to be preserved.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114147502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722809
L. Hebrand, J. Blonde, C. Colledani, G. Clauss
A new CMOS low-power mixed A/D ASIC for radiation detector readout front ends is presented. First, we recall the principle of radiation detection system before describing the whole architecture of the circuit. The discussion is then focused on the low-power issue. By means of an innovative 128:1 analog multiplexer, we show how we drastically reduced the mean power consumption without sacrificing constraining specifications such as the input range and the readout rate. Testing mixed A/D, but strongly analog IC is also a big issue which is addressed here. Specific built-in test analog sub-circuits have been implemented in the ASIC, along with a JTAG module used to choose the type of test to perform. This module is also used to control and tune the biasing currents of the circuit. Finally, test results are presented and show that all the specifications are satisfied.
{"title":"Design and test of a CMOS low-power mixed-analog/digital ASIC for radiation detector readout front ends","authors":"L. Hebrand, J. Blonde, C. Colledani, G. Clauss","doi":"10.1109/ASIC.1998.722809","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722809","url":null,"abstract":"A new CMOS low-power mixed A/D ASIC for radiation detector readout front ends is presented. First, we recall the principle of radiation detection system before describing the whole architecture of the circuit. The discussion is then focused on the low-power issue. By means of an innovative 128:1 analog multiplexer, we show how we drastically reduced the mean power consumption without sacrificing constraining specifications such as the input range and the readout rate. Testing mixed A/D, but strongly analog IC is also a big issue which is addressed here. Specific built-in test analog sub-circuits have been implemented in the ASIC, along with a JTAG module used to choose the type of test to perform. This module is also used to control and tune the biasing currents of the circuit. Finally, test results are presented and show that all the specifications are satisfied.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114186036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：