Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722889
B. Austin, X. Tang, J. Meindl, M. Dennen, W. Richards
A closed-form analytical threshold voltage roll-off model (/spl Delta/V/sub T/) for bulk accumulation MOSFETs, namely, buried channel accumulation (BCA) and surface channel accumulation (SCA), has been derived. Results show that scaling of BCA/SCA devices to the L=0.1 /spl mu/m range while maintaining performance is feasible for devices with very shallow tubs and source/drain junctions. It is also observed that for such devices, the SGA /spl Delta/V/sub T/ can be substantially smaller than the conventional surface channel inversion MOSFET /spl Delta/V/sub T/.
{"title":"Threshold voltage roll-off model for low power bulk accumulation MOSFETs","authors":"B. Austin, X. Tang, J. Meindl, M. Dennen, W. Richards","doi":"10.1109/ASIC.1998.722889","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722889","url":null,"abstract":"A closed-form analytical threshold voltage roll-off model (/spl Delta/V/sub T/) for bulk accumulation MOSFETs, namely, buried channel accumulation (BCA) and surface channel accumulation (SCA), has been derived. Results show that scaling of BCA/SCA devices to the L=0.1 /spl mu/m range while maintaining performance is feasible for devices with very shallow tubs and source/drain junctions. It is also observed that for such devices, the SGA /spl Delta/V/sub T/ can be substantially smaller than the conventional surface channel inversion MOSFET /spl Delta/V/sub T/.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127912850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722912
Mely Chen Chi, J. Tseng, C.Y. Lee, S. Huang
To shorten design time, it is very important to correctly supply the wire load of nets to the synthesis tool before layout. In this paper, a procedure to create wire load models for a specific processing technology and design flow is presented. Also a physical to logical hierarchy mapping procedure is proposed such that the correct wire load model may be applied to drive synthesis before layout. We apply these methodologies to our company's products of 0.6 /spl mu/m technology as illustrations.
{"title":"A practical interconnect driven ASIC design procedure","authors":"Mely Chen Chi, J. Tseng, C.Y. Lee, S. Huang","doi":"10.1109/ASIC.1998.722912","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722912","url":null,"abstract":"To shorten design time, it is very important to correctly supply the wire load of nets to the synthesis tool before layout. In this paper, a procedure to create wire load models for a specific processing technology and design flow is presented. Also a physical to logical hierarchy mapping procedure is proposed such that the correct wire load model may be applied to drive synthesis before layout. We apply these methodologies to our company's products of 0.6 /spl mu/m technology as illustrations.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123770938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723011
A. Sagahyroon, J. Placer, M. Burmood, M. Massoumi
Recently, power dissipation has become a major design constraint for complex VLSI circuits. Designers need tools that rapidly, but accurately, estimate power dissipation in a given design. Two categories of tools are useful for this purpose: (1) power optimization tools and algorithms tightly integrated with logic optimization, and (2) an analysis tool for estimating the power consumption in an existing netlist. This work addresses the latter issue by employing a VHDL-based approach for analysis of power consumption in static CMOS combinational logic designs. The circuits under test will be either the result of logic synthesis with various optimization constraints or hand designs done through schematic capture. The proposed approach will also be used to analyze various known architectures of the same network for power consumption, such as various forms of adders. The work presented in this article consists of three phases: (1) designing smart VHDL simulation models that first measure transition activity at each node of the netlist and then estimate the power based on this activity and on fanout at each node, (2) the generation of smart input stimuli that achieve an upper bound on transition activity and hence power consumption, and (3) analysis of different topologies of the same circuit. The estimates produced by this analysis may provide useful feedback to designers or synthesis tools, allowing for better exploration of the design space.
{"title":"A VHDL-based simulation methodology for estimating switching activity in static CMOS circuits","authors":"A. Sagahyroon, J. Placer, M. Burmood, M. Massoumi","doi":"10.1109/ASIC.1998.723011","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723011","url":null,"abstract":"Recently, power dissipation has become a major design constraint for complex VLSI circuits. Designers need tools that rapidly, but accurately, estimate power dissipation in a given design. Two categories of tools are useful for this purpose: (1) power optimization tools and algorithms tightly integrated with logic optimization, and (2) an analysis tool for estimating the power consumption in an existing netlist. This work addresses the latter issue by employing a VHDL-based approach for analysis of power consumption in static CMOS combinational logic designs. The circuits under test will be either the result of logic synthesis with various optimization constraints or hand designs done through schematic capture. The proposed approach will also be used to analyze various known architectures of the same network for power consumption, such as various forms of adders. The work presented in this article consists of three phases: (1) designing smart VHDL simulation models that first measure transition activity at each node of the netlist and then estimate the power based on this activity and on fanout at each node, (2) the generation of smart input stimuli that achieve an upper bound on transition activity and hence power consumption, and (3) analysis of different topologies of the same circuit. The estimates produced by this analysis may provide useful feedback to designers or synthesis tools, allowing for better exploration of the design space.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122461562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722909
S. Lodha, D. Bhatia
VLSI circuit partitioning is an extensively studied problem. Various iterative improvement based heuristics have been, proposed for obtaining reasonably good solutions. In this paper we explore the applicability of TABU search for partitioning of electrical circuits. We briefly describe the TABU search and its application to circuit or graph partitioning. We have generated experimental results on a variety of standard benchmark circuits. Our results match in quality, and at times improve, the tightest known results in the partitioning literature. We have shown extensive comparison with at least six very well known methods for circuit partitioning.
{"title":"Bipartitioning circuits using TABU search","authors":"S. Lodha, D. Bhatia","doi":"10.1109/ASIC.1998.722909","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722909","url":null,"abstract":"VLSI circuit partitioning is an extensively studied problem. Various iterative improvement based heuristics have been, proposed for obtaining reasonably good solutions. In this paper we explore the applicability of TABU search for partitioning of electrical circuits. We briefly describe the TABU search and its application to circuit or graph partitioning. We have generated experimental results on a variety of standard benchmark circuits. Our results match in quality, and at times improve, the tightest known results in the partitioning literature. We have shown extensive comparison with at least six very well known methods for circuit partitioning.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133925282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723032
M. Langhammer
Division is required for many applications in graphics and signal processing. Often, algorithms are changed to avoid using division, as current division methods are seen to be large and slow. In this paper, a new division algorithm is presented that is relatively straightforward, easily scaleable, and approximately one half the size of common approaches. Implementation examples are also given.
{"title":"Improved subtractive division algorithm","authors":"M. Langhammer","doi":"10.1109/ASIC.1998.723032","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723032","url":null,"abstract":"Division is required for many applications in graphics and signal processing. Often, algorithms are changed to avoid using division, as current division methods are seen to be large and slow. In this paper, a new division algorithm is presented that is relatively straightforward, easily scaleable, and approximately one half the size of common approaches. Implementation examples are also given.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130342769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723056
F. Chávez, A. Olmos, C. Azeredo-Leme, E. Charry
This work presents a temperature compensation subsystem for a piezoresistive pressure microsensor system operating between 0-50 kPa for medical purposes. Different full scale span and offset voltage can be compensated easily against temperature effects with a CMOS circuit that generates two temperature dependent voltages with 64 possible settings of temperature coefficients: the drive voltage of the active bridge and the reference voltage of the offset cancellation DAC. The subsystem showed a total power dissipation of approximately 3 mW working with 3 volts of power supply.
{"title":"A temperature compensation subsystem for an IMEMS CMOS pressure sensor","authors":"F. Chávez, A. Olmos, C. Azeredo-Leme, E. Charry","doi":"10.1109/ASIC.1998.723056","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723056","url":null,"abstract":"This work presents a temperature compensation subsystem for a piezoresistive pressure microsensor system operating between 0-50 kPa for medical purposes. Different full scale span and offset voltage can be compensated easily against temperature effects with a CMOS circuit that generates two temperature dependent voltages with 64 possible settings of temperature coefficients: the drive voltage of the active bridge and the reference voltage of the offset cancellation DAC. The subsystem showed a total power dissipation of approximately 3 mW working with 3 volts of power supply.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117262043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723037
R. Secareanu, E. Friedman
A High Speed High-Drive (HD) CMOS buffer is described in this paper which is an alternative to the widely used CMOS tapered buffer. The paper introduces the principle of operation of the HD buffer and compares it with a tapered buffer. Depending upon the capacitive load, the HD buffer as compared to an equivalent tapered buffer can provide increased speed (up to 2.2/spl times/) or multiple speed/power/area trade-offs. Clock distribution networks, large data buses, and I/O buffers are some possible applications of this buffer structure.
{"title":"A high speed CMOS buffer for driving large capacitive loads in digital ASICs","authors":"R. Secareanu, E. Friedman","doi":"10.1109/ASIC.1998.723037","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723037","url":null,"abstract":"A High Speed High-Drive (HD) CMOS buffer is described in this paper which is an alternative to the widely used CMOS tapered buffer. The paper introduces the principle of operation of the HD buffer and compares it with a tapered buffer. Depending upon the capacitive load, the HD buffer as compared to an equivalent tapered buffer can provide increased speed (up to 2.2/spl times/) or multiple speed/power/area trade-offs. Clock distribution networks, large data buses, and I/O buffers are some possible applications of this buffer structure.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116261268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722982
J.A. Huang, C.-i.H. Chen, J. Romera
Carry lookahead adders have been, over the years, an integral part of microprocessor architecture. Structures and levels of adders vary depending on the carry output. In this paper, analysis and optimization processes are first performed on a testable convergent tree adder. It is shown that the structure of the tree provides for a high fanout with an imbalanced tree structure which contributes to a racing effect and increases the timing delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder the optimization in 1.2 /spl mu/m CMOS produces a 6.37% increase in speed of the critical path while only losing 2.16% in area. The full testability of the circuit is maintained in the optimized adder design.
{"title":"Timing optimization for testable convergent tree adders","authors":"J.A. Huang, C.-i.H. Chen, J. Romera","doi":"10.1109/ASIC.1998.722982","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722982","url":null,"abstract":"Carry lookahead adders have been, over the years, an integral part of microprocessor architecture. Structures and levels of adders vary depending on the carry output. In this paper, analysis and optimization processes are first performed on a testable convergent tree adder. It is shown that the structure of the tree provides for a high fanout with an imbalanced tree structure which contributes to a racing effect and increases the timing delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder the optimization in 1.2 /spl mu/m CMOS produces a 6.37% increase in speed of the critical path while only losing 2.16% in area. The full testability of the circuit is maintained in the optimized adder design.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121607831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722822
Zheng Zhu, B. Carlson
We present experimental results for a new CMOS logic family: Critical Voltage Transition Logic (CVTL). It has a different structure and different operating characteristic compared to existing CMOS logic circuit families. Its novel delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Measurements show that the CVTL buffer is four to eight times faster than the static counterpart. Although it consumes more energy, the energy-delay product is significantly smaller compared with a static CMOS buffer.
{"title":"Analysis and experimental results of a CVTL buffer design","authors":"Zheng Zhu, B. Carlson","doi":"10.1109/ASIC.1998.722822","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722822","url":null,"abstract":"We present experimental results for a new CMOS logic family: Critical Voltage Transition Logic (CVTL). It has a different structure and different operating characteristic compared to existing CMOS logic circuit families. Its novel delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Measurements show that the CVTL buffer is four to eight times faster than the static counterpart. Although it consumes more energy, the energy-delay product is significantly smaller compared with a static CMOS buffer.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123893877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723085
S. Xia, R. Sridhar, P. Scott, C. Bandera
A foveal image sensor chip that uses a standard CMOS process is presented. A new photo charge normalization scheme and its associated circuitry for use with active pixel sensors has been developed. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision. A proof-of-concept chip has been fabricated and tested.
{"title":"An all CMOS foveal image sensor chip","authors":"S. Xia, R. Sridhar, P. Scott, C. Bandera","doi":"10.1109/ASIC.1998.723085","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723085","url":null,"abstract":"A foveal image sensor chip that uses a standard CMOS process is presented. A new photo charge normalization scheme and its associated circuitry for use with active pixel sensors has been developed. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision. A proof-of-concept chip has been fabricated and tested.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123989895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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