Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722791
D. Pnevmatikatos, G. Kornaros, G. Kalokerinos, C. Xanthaki
We present the overall structure of ATLAS I, emphasizing the memory use and requirements. We categorize these requirements in functionality and bandwidth and present the solutions we used in the first implementation of ATLAS I in a 0.35 /spl mu/ CMOS technology. This implementation can serve as a starting point in the design of future switches with functionality similar to ATLAS I.
{"title":"The memory structures of ATLAS I, a high-performance, 16/spl times/16 ATM switch supporting backpressure","authors":"D. Pnevmatikatos, G. Kornaros, G. Kalokerinos, C. Xanthaki","doi":"10.1109/ASIC.1998.722791","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722791","url":null,"abstract":"We present the overall structure of ATLAS I, emphasizing the memory use and requirements. We categorize these requirements in functionality and bandwidth and present the solutions we used in the first implementation of ATLAS I in a 0.35 /spl mu/ CMOS technology. This implementation can serve as a starting point in the design of future switches with functionality similar to ATLAS I.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131736277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723014
Denis Dohler, K. Hering, W. Spruth
Logic simulation is a crucial verification task in processor design. Aiming at significant acceleration of system simulation we have parallelized IBM's cycle-based simulator TEXSIM. The resulting parallelTEXSIM has already been employed successfully in simulating S/390 architectures on IBM SP systems. Here we present parallelTEXSIM together with its model partitioning environment.
{"title":"Cycle-based simulation on loosely-coupled systems","authors":"Denis Dohler, K. Hering, W. Spruth","doi":"10.1109/ASIC.1998.723014","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723014","url":null,"abstract":"Logic simulation is a crucial verification task in processor design. Aiming at significant acceleration of system simulation we have parallelized IBM's cycle-based simulator TEXSIM. The resulting parallelTEXSIM has already been employed successfully in simulating S/390 architectures on IBM SP systems. Here we present parallelTEXSIM together with its model partitioning environment.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722783
J.C. Kim, S. Lee, D. Lee, J.H. Lee, W. Jeong, H.J. Park, I. Mok
A single-chip 32-bit microcontroller was designed for a motor drive; the architecture and the implementation issues such as the clock distribution and the chip test results including the power dissipation are presented in this paper. The microcontroller includes the SPARC processor a FPU, a memory controller, an interrupt controller and peripheral devices in a single-chip. The microcontroller was optimized for vector controlled motor drives demanding high performance number crunching capabilities. The microcontroller chip was fabricated using a 0.8 /spl mu/m DLM N-well. CMOS technology. The chip contained about 562,000 transistors, the chip size was 12.8 mm/spl times/12.7 mm and the power consumption was 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz.
{"title":"Single-chip implementation of a 32-bit microcontroller for motor drive","authors":"J.C. Kim, S. Lee, D. Lee, J.H. Lee, W. Jeong, H.J. Park, I. Mok","doi":"10.1109/ASIC.1998.722783","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722783","url":null,"abstract":"A single-chip 32-bit microcontroller was designed for a motor drive; the architecture and the implementation issues such as the clock distribution and the chip test results including the power dissipation are presented in this paper. The microcontroller includes the SPARC processor a FPU, a memory controller, an interrupt controller and peripheral devices in a single-chip. The microcontroller was optimized for vector controlled motor drives demanding high performance number crunching capabilities. The microcontroller chip was fabricated using a 0.8 /spl mu/m DLM N-well. CMOS technology. The chip contained about 562,000 transistors, the chip size was 12.8 mm/spl times/12.7 mm and the power consumption was 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115641886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722800
D. Wisland, T. Saether, T. Lande, M. Høvin
This paper presents a novel technique for center-frequency tuning of phase-locked loops (PLL) by exposing the circuit to UV-light. No external biasing is required, and the tuning procedure is automatic due to the feedback in the PLL. The main purpose with the technique is to compensate for process variations in loops with low VCO-gain. A 433 MHz charge-pump PLL has been designed, and measured results are presented.
{"title":"PLL center-frequency tuning using floating-gates","authors":"D. Wisland, T. Saether, T. Lande, M. Høvin","doi":"10.1109/ASIC.1998.722800","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722800","url":null,"abstract":"This paper presents a novel technique for center-frequency tuning of phase-locked loops (PLL) by exposing the circuit to UV-light. No external biasing is required, and the tuning procedure is automatic due to the feedback in the PLL. The main purpose with the technique is to compensate for process variations in loops with low VCO-gain. A 433 MHz charge-pump PLL has been designed, and measured results are presented.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123675016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723088
F. Mavaddat
Formal verification questions are often formulated in one of two forms. First, called “property check”, is between a property p and a model M of a design, and is posed as “Is p true of M?” Second, called “implementation check”, is between models MI and M2 of two designs and is posed as “Is M2 an implementation of MI?’ employs one of three techniques, namely: theorem proving, model checking, and equivalence checking. Theorem proving is the most general of these techniques, has a steep learning curve, and its use in hardware verification is still
{"title":"Formal Hardware Verification: A Users' View Summary","authors":"F. Mavaddat","doi":"10.1109/ASIC.1998.723088","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723088","url":null,"abstract":"Formal verification questions are often formulated in one of two forms. First, called “property check”, is between a property p and a model M of a design, and is posed as “Is p true of M?” Second, called “implementation check”, is between models MI and M2 of two designs and is posed as “Is M2 an implementation of MI?’ employs one of three techniques, namely: theorem proving, model checking, and equivalence checking. Theorem proving is the most general of these techniques, has a steep learning curve, and its use in hardware verification is still","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124762209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723029
Lihong Jia, Yonghong Gao, J. Isoaho, H. Tenhunen
In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 /spl mu/m-3.3 V triple-metal CMOS process.
{"title":"A new VLSI-oriented FFT algorithm and implementation","authors":"Lihong Jia, Yonghong Gao, J. Isoaho, H. Tenhunen","doi":"10.1109/ASIC.1998.723029","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723029","url":null,"abstract":"In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 /spl mu/m-3.3 V triple-metal CMOS process.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129010212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723041
V. Adler, Eby G. Friedman
One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a global optimization algorithm for inserting repeaters into RC trees. The timing model predicts results generally within 10% of SPICE. The global optimization method exhibits total delay improvements of up to 86% over typical cascaded buffer insertion methods. The repeater timing model, global insertion methodology and algorithm, and software implementation are summarized in this paper.
{"title":"Optimizing RC tree delay in high speed ASICs through repeater insertion","authors":"V. Adler, Eby G. Friedman","doi":"10.1109/ASIC.1998.723041","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723041","url":null,"abstract":"One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a global optimization algorithm for inserting repeaters into RC trees. The timing model predicts results generally within 10% of SPICE. The global optimization method exhibits total delay improvements of up to 86% over typical cascaded buffer insertion methods. The repeater timing model, global insertion methodology and algorithm, and software implementation are summarized in this paper.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"15 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124537502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722994
R. Hossain, J.C. Herbert, J. Gouger, R. Bechade
This paper describes the use of a datapath library in the design of a high performance, pipelined floating point unit (FPU) macrocell. The existence of the intellectual property (IP) library allowed the rapid completion of the FPU within the context of a high performance structured custom design flow. The 165000 transistor floating point unit was completed in 25 man months from initial customer specification to final physical assembly. The macrocell occupies 2.45 mm/spl times/2.55 mm in a 0.35 /spl mu/m, 4 metal CMOS process and has a simulated cycle time of 5.2 ns at 3.3 V and 85/spl deg/C.
{"title":"Datapath library reuse in the design of a high performance floating point unit","authors":"R. Hossain, J.C. Herbert, J. Gouger, R. Bechade","doi":"10.1109/ASIC.1998.722994","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722994","url":null,"abstract":"This paper describes the use of a datapath library in the design of a high performance, pipelined floating point unit (FPU) macrocell. The existence of the intellectual property (IP) library allowed the rapid completion of the FPU within the context of a high performance structured custom design flow. The 165000 transistor floating point unit was completed in 25 man months from initial customer specification to final physical assembly. The macrocell occupies 2.45 mm/spl times/2.55 mm in a 0.35 /spl mu/m, 4 metal CMOS process and has a simulated cycle time of 5.2 ns at 3.3 V and 85/spl deg/C.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122520052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722897
E. Torbey, J. Knight
This paper presents architectural trade-offs of a time-shared implementation of a modified fast discrete cosine transform algorithm using a high-level synthesis tool. The architecture presented here allows time-sharing of operators in different stages. The overhead in control and multiplexing is minimal. A full implementation of an 8/spl times/8 2-D DCT outperforms the original pipelined architecture and a hand-crafted time-shared architecture by reducing the required area by up to 50%. It also improves the latency by up to 70%. It achieves these improvements maintaining the throughput for a 5% decrease in the required critical path timing. The complexity of the 2-D DCT used is higher than the traditional benchmarks for high-level synthesis. This paper shows the effectiveness of the synthesis tool used for large, practical algorithms.
{"title":"Implementation and trade-offs of a DCT architecture using high-level synthesis","authors":"E. Torbey, J. Knight","doi":"10.1109/ASIC.1998.722897","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722897","url":null,"abstract":"This paper presents architectural trade-offs of a time-shared implementation of a modified fast discrete cosine transform algorithm using a high-level synthesis tool. The architecture presented here allows time-sharing of operators in different stages. The overhead in control and multiplexing is minimal. A full implementation of an 8/spl times/8 2-D DCT outperforms the original pipelined architecture and a hand-crafted time-shared architecture by reducing the required area by up to 50%. It also improves the latency by up to 70%. It achieves these improvements maintaining the throughput for a 5% decrease in the required critical path timing. The complexity of the 2-D DCT used is higher than the traditional benchmarks for high-level synthesis. This paper shows the effectiveness of the synthesis tool used for large, practical algorithms.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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