Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722907
J. Emmert, D. Bhatia
In this paper we present algorithms for incrementally routing circuits mapped to field-programmable gate arrays (FPGAs). The algorithms work well for ripping up and rerouting nets connected to small numbers of displaced logic blocks. Additionally the algorithms are sequential and compact, therefore making them ideal for embedding in hardware. Given an FPGA with a readable as well as writable configuration memory, these algorithms require no prior knowledge of the mapped circuit's netlist. Experimental results indicate our router works well for fault tolerance and other applications.
{"title":"Incremental routing in FPGAs","authors":"J. Emmert, D. Bhatia","doi":"10.1109/ASIC.1998.722907","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722907","url":null,"abstract":"In this paper we present algorithms for incrementally routing circuits mapped to field-programmable gate arrays (FPGAs). The algorithms work well for ripping up and rerouting nets connected to small numbers of displaced logic blocks. Additionally the algorithms are sequential and compact, therefore making them ideal for embedding in hardware. Given an FPGA with a readable as well as writable configuration memory, these algorithms require no prior knowledge of the mapped circuit's netlist. Experimental results indicate our router works well for fault tolerance and other applications.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130419476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722894
S. Gastaldello, G. Traverso, R. Kase
Reusability of basic building blocks is an important and effective goal in ASIC design: it speeds up the design, it minimizes the overall bug probability, it eases documentation and maintenance of core functions. Nevertheless, this approach means also a "black box" management, requiring some extra efforts in the implementation phase. Alcatel and Toshiba proved a solution to cope with the lack of knowledge and control of re-used blocks. This methodology seems to be effective, especially for million gates designs in deep submicron technologies. This paper discusses a real ASIC design case, where classical issues were combined: tough schedule; large glue logic (800 K netlist gates), with high connectivity; many clock domains (65 clocks), with many interactions; 50% reuse of old building blocks, many from netlist. The proposed flow improves by shortening design time, achieving high synthesis efficiency without usage of time consuming CRWC methodology, achieving high layout efficiency bypassing time consuming (and sometimes misleading) floorplanning /hierarchical methodologies.
{"title":"800 K gates of random logic in four months: discussion on design methodologies based on \"IDEFIX\" ASIC experience","authors":"S. Gastaldello, G. Traverso, R. Kase","doi":"10.1109/ASIC.1998.722894","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722894","url":null,"abstract":"Reusability of basic building blocks is an important and effective goal in ASIC design: it speeds up the design, it minimizes the overall bug probability, it eases documentation and maintenance of core functions. Nevertheless, this approach means also a \"black box\" management, requiring some extra efforts in the implementation phase. Alcatel and Toshiba proved a solution to cope with the lack of knowledge and control of re-used blocks. This methodology seems to be effective, especially for million gates designs in deep submicron technologies. This paper discusses a real ASIC design case, where classical issues were combined: tough schedule; large glue logic (800 K netlist gates), with high connectivity; many clock domains (65 clocks), with many interactions; 50% reuse of old building blocks, many from netlist. The proposed flow improves by shortening design time, achieving high synthesis efficiency without usage of time consuming CRWC methodology, achieving high layout efficiency bypassing time consuming (and sometimes misleading) floorplanning /hierarchical methodologies.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114247915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723089
V. P. Raghavan
The objective of this Workshop is to introduce and give hands on experience on how to apply behavioral synthesis techniques successfully on 2 real life applications using Synopsys Behavioral Compiler. The following topics will be addressed using lecture and lab exercises: Behavioral Compiler Concepts, Behavioral Partitioning Methodology, Application1 : NPort Network Switch (involves control flow & Memory I/O Inferencing) and Application-2 : Alpha Blender for Video Mixing (Real Time Data requiring Pipelining).
{"title":"Designing Real-Life Applications Using Synopsys Behavioral Compiler","authors":"V. P. Raghavan","doi":"10.1109/ASIC.1998.723089","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723089","url":null,"abstract":"The objective of this Workshop is to introduce and give hands on experience on how to apply behavioral synthesis techniques successfully on 2 real life applications using Synopsys Behavioral Compiler. The following topics will be addressed using lecture and lab exercises: Behavioral Compiler Concepts, Behavioral Partitioning Methodology, Application1 : NPort Network Switch (involves control flow & Memory I/O Inferencing) and Application-2 : Alpha Blender for Video Mixing (Real Time Data requiring Pipelining).","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124713630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722801
J. Egerer, T. Desel, Popken, J. Boxho, D. Macq, J. Cornil
For an HDSL analog front end, a low distortion 5/sup th/ order R-MOSFET-C Bessel filter was designed in a 0.5 /spl mu/m, 3.3 V CMOS technology. The filter is linearly tunable around cutoff frequencies of 488 kHz and 335 kHz by an on-chip tuning circuit. The fabricated prototypes show linear tuning and a THD<-75 dB for a 100 kHz signal.
针对HDSL模拟前端，采用0.5 /spl mu/m、3.3 V CMOS技术设计了低失真5/sup /阶R-MOSFET-C贝塞尔滤波器。该滤波器通过片上调谐电路在488 kHz和335 kHz的截止频率附近线性可调。制造的原型显示线性调谐和THD<-75 dB的100 kHz信号。
{"title":"A low distortion linear-tunable continuous-time 488 kHz fifth-order Bessel filter","authors":"J. Egerer, T. Desel, Popken, J. Boxho, D. Macq, J. Cornil","doi":"10.1109/ASIC.1998.722801","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722801","url":null,"abstract":"For an HDSL analog front end, a low distortion 5/sup th/ order R-MOSFET-C Bessel filter was designed in a 0.5 /spl mu/m, 3.3 V CMOS technology. The filter is linearly tunable around cutoff frequencies of 488 kHz and 335 kHz by an on-chip tuning circuit. The fabricated prototypes show linear tuning and a THD<-75 dB for a 100 kHz signal.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126873742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722818
T. Okamura, Y. Kinoshita, H. Yoshida, D. Yamane
As technology advances offer small size and light weight in mobile telecommunication equipment, low power techniques become important elements. This paper describes the design techniques for very low power consumption, solving hardware implementation issues. Basically they were applied to the speech codec in a personal digital cellular phone and their effectiveness was verified.
{"title":"Low power design for speech codec","authors":"T. Okamura, Y. Kinoshita, H. Yoshida, D. Yamane","doi":"10.1109/ASIC.1998.722818","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722818","url":null,"abstract":"As technology advances offer small size and light weight in mobile telecommunication equipment, low power techniques become important elements. This paper describes the design techniques for very low power consumption, solving hardware implementation issues. Basically they were applied to the speech codec in a personal digital cellular phone and their effectiveness was verified.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723042
P. Lee, C. Anagnopoulis
As the Application Specific Integrated Circuit (ASIC) technology pushes towards realizing electronic system-on-a-chip, it becomes apparent that there is a need for incorporating the interface between electronics and the external physical world. These interfaces or transducers take physical parameters such as light intensity, pressure and temperature and turn them into electrical signals which can be acted on in the electronic domain of the ASIC’s. This sessions deals with 2 emerging areas of Micro-Electronical-Mechanical systems (MEMS) and image sensors where integration with CMOS ASlC are being pursued.
{"title":"Mems/cmos Integration & Image Sensors","authors":"P. Lee, C. Anagnopoulis","doi":"10.1109/ASIC.1998.723042","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723042","url":null,"abstract":"As the Application Specific Integrated Circuit (ASIC) technology pushes towards realizing electronic system-on-a-chip, it becomes apparent that there is a need for incorporating the interface between electronics and the external physical world. These interfaces or transducers take physical parameters such as light intensity, pressure and temperature and turn them into electrical signals which can be acted on in the electronic domain of the ASIC’s. This sessions deals with 2 emerging areas of Micro-Electronical-Mechanical systems (MEMS) and image sensors where integration with CMOS ASlC are being pursued.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128642312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722813
Y. Berg, T. Lande
In this paper we present both novel current-mirrors and a novel pseudo differential pairs using floating-gate transistors available in standard double-poly CMOS. The circuits are modeled and simulated down to 50 mV supply voltage. Wide dynamic range combined with high linearity is achieved with Early effect compensation using minimum transistors.
{"title":"Ultra low-voltage current mirrors and pseudo differential pairs","authors":"Y. Berg, T. Lande","doi":"10.1109/ASIC.1998.722813","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722813","url":null,"abstract":"In this paper we present both novel current-mirrors and a novel pseudo differential pairs using floating-gate transistors available in standard double-poly CMOS. The circuits are modeled and simulated down to 50 mV supply voltage. Wide dynamic range combined with high linearity is achieved with Early effect compensation using minimum transistors.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125051219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723057
G. Klisnick, Y. Hu, F. Voisin, M. Redon, A. Gaugue, A. Kreisler
YBaCuO thin films have shown their attractiveness for infrared and far-infrared sensors working at the superconducting transition temperature (/spl ap/85 K). We present a cryogenic CMOS preamplifier designed for working close to such a sensor at the same temperature. This preamplifier has been tested from room temperature (300 K) down to liquid nitrogen temperature (77 K). Simulation results show that an equivalent input noise of 2.7 nV//spl radic/Hz at 10 kHz can be obtained at room temperature, whereas measurement results are 3.2 nV//spl radic/Hz at 300 K and 2 nV//spl radic/Hz at 77 K. When coupled to the YBaCuO sensor, an improvement of the overall noise level of the detector, by cooling the preamplifier, could be observed.
{"title":"A low noise cryogenic CMOS preamplifier for high critical temperature superconducting IR and FIR sensors","authors":"G. Klisnick, Y. Hu, F. Voisin, M. Redon, A. Gaugue, A. Kreisler","doi":"10.1109/ASIC.1998.723057","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723057","url":null,"abstract":"YBaCuO thin films have shown their attractiveness for infrared and far-infrared sensors working at the superconducting transition temperature (/spl ap/85 K). We present a cryogenic CMOS preamplifier designed for working close to such a sensor at the same temperature. This preamplifier has been tested from room temperature (300 K) down to liquid nitrogen temperature (77 K). Simulation results show that an equivalent input noise of 2.7 nV//spl radic/Hz at 10 kHz can be obtained at room temperature, whereas measurement results are 3.2 nV//spl radic/Hz at 300 K and 2 nV//spl radic/Hz at 77 K. When coupled to the YBaCuO sensor, an improvement of the overall noise level of the detector, by cooling the preamplifier, could be observed.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126368671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723087
J. Henkel, F. Vahid
The growth in integration capacity allows to integrate complete systems on one single chip (SOC: systems-on-a-chip). Since traditional design tools can not keep pace with this rapid growth, so-called core-based design methodologies become more and more important for today’s system designer. In this context, a core can be a microprocessor, a controller, a multimedia application, etc. Distinguished are often three levels of cores: soft, firm and hard cores. Whereas a soft core is a non-synthesized, often technology independent HDL description of a circuit, a hard core is readily synthesized and verified. A f i core is somewhere between and owns some peculiarities of soft cores and some of hard cores. By composing a system of a mixture of soft, f i and hard cores, the system designer is enabled to achieve the best compromise between parameterization, customization and re-usability. As a result, the time-to-market as well as system costs can be drastically reduced. In this four-hour tutorial the authors will give an overview of core-based design methodologies while mainly focussing on the following decisive design aspects: Integration of cores on a chip: a) Integration is the process of adapting various cores to each other according to given design goals and afterwards synthesizing these cores (if applicable) in order to obtain a singlechip-solution. Among other steps, this procedure involves the selection of appropriate interfaces since this matter is directly related to design goalslconstraints like system performance, total chip area, system power dissipation, system costs, etc. Whereas intra-chip interfaces (between the SOC and the environment, for example), is limited to standard interfaces. The tutorial will give some examples for the integration procedure with emphasize on interface selection for different design goalskonstraints. Frank Vahid Department of Computer Science University of Califbrnia Riverside Riverside, California 9252 1-0304, USA vahid(ii,cs.ucr.edu
集成能力的增长允许在单个芯片上集成完整的系统(SOC:片上系统)。由于传统的设计工具无法跟上这种快速增长的步伐，所谓的基于核心的设计方法对今天的系统设计师来说变得越来越重要。在这种情况下，核心可以是微处理器、控制器、多媒体应用程序等。核心通常分为三个层次:软核、硬核和硬核。软核是一种非合成的、通常与技术无关的电路HDL描述，而硬核是很容易合成和验证的。f核介于软核和硬核之间，具有软核和硬核的一些特性。通过将软核、软核和硬核混合组成系统，系统设计者能够在参数化、定制化和可重用性之间实现最佳折衷。因此，上市时间和系统成本可以大大减少。在这个四小时的教程中，作者将概述基于核心的设计方法，同时主要关注以下决定性的设计方面:芯片上的核心集成:a)集成是根据给定的设计目标使各种核心相互适应的过程，然后综合这些核心(如果适用)，以获得单芯片解决方案。在其他步骤中，这个过程包括选择合适的接口，因为这个问题直接关系到设计目标的限制，如系统性能、芯片总面积、系统功耗、系统成本等。而芯片内接口(例如，在SOC和环境之间)则仅限于标准接口。本教程将给出一些集成过程的示例，重点介绍针对不同设计目标和约束的接口选择。Frank Vahid美国加州大学河滨分校计算机科学系，加州河滨分校9252 -0304,USA Vahid (ii, c.c.ucr.edu
{"title":"Core-based Design Of Systems On A Chip","authors":"J. Henkel, F. Vahid","doi":"10.1109/ASIC.1998.723087","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723087","url":null,"abstract":"The growth in integration capacity allows to integrate complete systems on one single chip (SOC: systems-on-a-chip). Since traditional design tools can not keep pace with this rapid growth, so-called core-based design methodologies become more and more important for today’s system designer. In this context, a core can be a microprocessor, a controller, a multimedia application, etc. Distinguished are often three levels of cores: soft, firm and hard cores. Whereas a soft core is a non-synthesized, often technology independent HDL description of a circuit, a hard core is readily synthesized and verified. A f i core is somewhere between and owns some peculiarities of soft cores and some of hard cores. By composing a system of a mixture of soft, f i and hard cores, the system designer is enabled to achieve the best compromise between parameterization, customization and re-usability. As a result, the time-to-market as well as system costs can be drastically reduced. In this four-hour tutorial the authors will give an overview of core-based design methodologies while mainly focussing on the following decisive design aspects: Integration of cores on a chip: a) Integration is the process of adapting various cores to each other according to given design goals and afterwards synthesizing these cores (if applicable) in order to obtain a singlechip-solution. Among other steps, this procedure involves the selection of appropriate interfaces since this matter is directly related to design goalslconstraints like system performance, total chip area, system power dissipation, system costs, etc. Whereas intra-chip interfaces (between the SOC and the environment, for example), is limited to standard interfaces. The tutorial will give some examples for the integration procedure with emphasize on interface selection for different design goalskonstraints. Frank Vahid Department of Computer Science University of Califbrnia Riverside Riverside, California 9252 1-0304, USA vahid(ii,cs.ucr.edu","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132862118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.723034
P. Nagvajara, T.R. Damarla, J. Wang, S. Chansilp
A design of a pipeline architecture for a phase coherent numerically controlled oscillator (NCO) is presented. The NCO synchronously generates sampled sinusoidal waveforms A cos(2/spl pi/ft+/spl phi/) and A sin(2/spl pi/ft+/spl phi/), as 16-bit signed integer values. The pipeline architecture includes multipliers, adders, and a 64K/spl times/16 embedded ROM. The proposed NCO provides waveform phase coherency relative to the time reference over varying frequencies, which is essential for coherent radar seekers using stepped frequency in Doppler synthesis.
{"title":"A phase-coherent numerically controlled oscillator based on pipeline architecture","authors":"P. Nagvajara, T.R. Damarla, J. Wang, S. Chansilp","doi":"10.1109/ASIC.1998.723034","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723034","url":null,"abstract":"A design of a pipeline architecture for a phase coherent numerically controlled oscillator (NCO) is presented. The NCO synchronously generates sampled sinusoidal waveforms A cos(2/spl pi/ft+/spl phi/) and A sin(2/spl pi/ft+/spl phi/), as 16-bit signed integer values. The pipeline architecture includes multipliers, adders, and a 64K/spl times/16 embedded ROM. The proposed NCO provides waveform phase coherency relative to the time reference over varying frequencies, which is essential for coherent radar seekers using stepped frequency in Doppler synthesis.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124588265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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