Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722808
Tianruo Yang, Zebo Peng
This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on the other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.
{"title":"Integrated scheduling and allocation of high-level test synthesis","authors":"Tianruo Yang, Zebo Peng","doi":"10.1109/ASIC.1998.722808","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722808","url":null,"abstract":"This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on the other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722990
M. Schutti, M. Pfaff, R. Hagelauer
Driven by the recent advances in VLSI technology, long-standing controller architectures have experienced a revival. The fast emerging IP (Intellectual Property) market is demanding embedded soft cores of well-established microcontrollers such as the 8051 and 68HC11. "System on a chip" technologies enable hardware designers to integrate their board designs, existing of several separate chips, into a single ASIC. For this transition a pool of adequate high level building blocks favorably implemented as technology-independent VHDL or Verilog descriptions is required.
{"title":"VHDL design of embedded processor cores: the industry-standard microcontroller 8051 and 68HC11","authors":"M. Schutti, M. Pfaff, R. Hagelauer","doi":"10.1109/ASIC.1998.722990","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722990","url":null,"abstract":"Driven by the recent advances in VLSI technology, long-standing controller architectures have experienced a revival. The fast emerging IP (Intellectual Property) market is demanding embedded soft cores of well-established microcontrollers such as the 8051 and 68HC11. \"System on a chip\" technologies enable hardware designers to integrate their board designs, existing of several separate chips, into a single ASIC. For this transition a pool of adequate high level building blocks favorably implemented as technology-independent VHDL or Verilog descriptions is required.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125323159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722986
Y. Kojima, N. Akiyama, T. Oouchi, M. Amishiro, M. Nemoto, S. Yukutake, A. Watanabe
This is the first report of the development of a monolithic isolator that can provide a transformerless small communications network interface IC. A novel capacitively isolated technology using trench capacitor on the SOI substrate has been developed, and that has achieved a 1.2 kV monolithic isolator of 0.25 mm/sup 2/. The monolithic isolator exhibits a good transmission characteristic at the frequency of 10 MHz.
{"title":"A novel monolithic isolator for a communications network interface IC","authors":"Y. Kojima, N. Akiyama, T. Oouchi, M. Amishiro, M. Nemoto, S. Yukutake, A. Watanabe","doi":"10.1109/ASIC.1998.722986","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722986","url":null,"abstract":"This is the first report of the development of a monolithic isolator that can provide a transformerless small communications network interface IC. A novel capacitively isolated technology using trench capacitor on the SOI substrate has been developed, and that has achieved a 1.2 kV monolithic isolator of 0.25 mm/sup 2/. The monolithic isolator exhibits a good transmission characteristic at the frequency of 10 MHz.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125467439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-09-13DOI: 10.1109/ASIC.1998.722999
J. Barby, C. Ryan
With the drive to ULSI design, the concept of design of the complete chip being done within a single design team is becoming rare. These large designs include large pieces of intellectual property (IP) from previous designs (design reuse) or imported from another company or design team (design core). To compound this, ULSI power budget targets are more difficult to meet than in the past when design complexity was less. In this session varying approaches to address these issues are discussed.
{"title":"Simulation And Modeling For High Level Design","authors":"J. Barby, C. Ryan","doi":"10.1109/ASIC.1998.722999","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722999","url":null,"abstract":"With the drive to ULSI design, the concept of design of the complete chip being done within a single design team is becoming rare. These large designs include large pieces of intellectual property (IP) from previous designs (design reuse) or imported from another company or design team (design core). To compound this, ULSI power budget targets are more difficult to meet than in the past when design complexity was less. In this session varying approaches to address these issues are discussed.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124528313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASIC.1998.722811
K. Vaniseghem, Hyun Lee
Summary form only given, as follows. Power considerations for today¿s systems are very important. Portable applications, remote applications and consumer products are all driving the need for reduced power consumption. Battery based systems are becoming much more prevalent and consumers do not wish to sacrifice performance. Thus minimizing power consumption is a very hot topic and the focus of this technical session. The session begins with a fabricated MPU design exhibiting very low power consumptiion using a multi-threshold scheme with separation by silicon-on-insulator (SOI) technology. A novel ultra low voltage differential technology with adjustable threshold voltages (and current-mirror and current-inverter applications using floating gate transistors) is presented. High level synthesis scheduling for multiple supply voltages is then presented. Another multiple supply voltage scheme is shown taking advantage of dual supply rails to all cells and proper scheduling of which rail is used for each cell. This scheme saves power at minimal cost of area and timing. Ultra low-power supply voltages below 1V introduce constraints not seen at higher supply voltages. A new MOSFET model is then presented that provides insight into the on/off current interdependence which becomes critical with voltage scaling. A new conditional-sum addition rule for low power applications is then presented. Next paper presents design technique for very low power applied to Speech Codec in the Personal Digital Cellular Phone. The final paper of this session outlines a PC-on-a-chip system using multi-chip package technology. This single package system requires numerous low power features implemented in silicon and this paper demonstrates such a system.
{"title":"Low Power [session summary]","authors":"K. Vaniseghem, Hyun Lee","doi":"10.1109/ASIC.1998.722811","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722811","url":null,"abstract":"Summary form only given, as follows. Power considerations for today¿s systems are very important. Portable applications, remote applications and consumer products are all driving the need for reduced power consumption. Battery based systems are becoming much more prevalent and consumers do not wish to sacrifice performance. Thus minimizing power consumption is a very hot topic and the focus of this technical session. The session begins with a fabricated MPU design exhibiting very low power consumptiion using a multi-threshold scheme with separation by silicon-on-insulator (SOI) technology. A novel ultra low voltage differential technology with adjustable threshold voltages (and current-mirror and current-inverter applications using floating gate transistors) is presented. High level synthesis scheduling for multiple supply voltages is then presented. Another multiple supply voltage scheme is shown taking advantage of dual supply rails to all cells and proper scheduling of which rail is used for each cell. This scheme saves power at minimal cost of area and timing. Ultra low-power supply voltages below 1V introduce constraints not seen at higher supply voltages. A new MOSFET model is then presented that provides insight into the on/off current interdependence which becomes critical with voltage scaling. A new conditional-sum addition rule for low power applications is then presented. Next paper presents design technique for very low power applied to Speech Codec in the Personal Digital Cellular Phone. The final paper of this session outlines a PC-on-a-chip system using multi-chip package technology. This single package system requires numerous low power features implemented in silicon and this paper demonstrates such a system.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASIC.1998.723090
J. Gilbert, S. Bart, B. Romanowicz
MicroElectroMechanical Systems (MEMS) is a new field whlch encompasses the fabrication of devices containing moving parts or fluids using fabrication techniques derived from the IC industry. In some areas and contexts (principally in Europe) the field is called Micro Systems Technology (MST). These devices and systems are: 0 Micron to mm scale devices having moving parts or fluids. 0 Batch fabricated by methods related or derived from the IC industry. 0 Sensors or Actuators or Transducers from one type of physics to another, 0 Controlled or integrated with on-chip or off chip ASICs MEMS design involves several layers of design work, and potentially concurrent engineering among several groups. An "Actor" based view of such conwent engineering is sketched in Figure 1.
{"title":"Design Of Integrated Systems Including Mems And Asics","authors":"J. Gilbert, S. Bart, B. Romanowicz","doi":"10.1109/ASIC.1998.723090","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723090","url":null,"abstract":"MicroElectroMechanical Systems (MEMS) is a new field whlch encompasses the fabrication of devices containing moving parts or fluids using fabrication techniques derived from the IC industry. In some areas and contexts (principally in Europe) the field is called Micro Systems Technology (MST). These devices and systems are: 0 Micron to mm scale devices having moving parts or fluids. 0 Batch fabricated by methods related or derived from the IC industry. 0 Sensors or Actuators or Transducers from one type of physics to another, 0 Controlled or integrated with on-chip or off chip ASICs MEMS design involves several layers of design work, and potentially concurrent engineering among several groups. An \"Actor\" based view of such conwent engineering is sketched in Figure 1.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115068085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASIC.1998.722798
G. Kedem, D. Braverman
Summary form only given, as follows. We find ASIC technology in a wide variety of demanding applications where high performance, low power, small weight or low parts count is a driving factor in design. This session has six articles describing a wide set of diverse applications. We begin with three articles describing ASICs for industrial applications. The first work describes a precision scale controller tha1 increases position resolution by an order of magnitude over existing methodologies. The second work describes a 32 bit embedded SPARC microcontroller designed for high performance motor control. The third details the utilization of a compact neural net design for precisely controlling electrical motor current. The forth work describes FPGA implementation of a Java processor designed to speed up applications v ritten in the popular Java programming language. The FPGA implementation is flexible, allowing the update of the processor design as the Java specification evolves. The fifth article describes the memory architecture of a high performance reconfigurable ATM switch supporting advanced features such as backpressure. The sixth pap r describes an ASIC implementation of the IDEA encryption algorithm. The authors describe an implementation that takes advantage of both temporal and spatial parallelism available in the IDEA algorithm. The HiPCrypto ASIC can encrypt/decrypt data at rates of up to 4.4 Gbps.
{"title":"ASIC Applications [session summary]","authors":"G. Kedem, D. Braverman","doi":"10.1109/ASIC.1998.722798","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722798","url":null,"abstract":"Summary form only given, as follows. We find ASIC technology in a wide variety of demanding applications where high performance, low power, small weight or low parts count is a driving factor in design. This session has six articles describing a wide set of diverse applications. We begin with three articles describing ASICs for industrial applications. The first work describes a precision scale controller tha1 increases position resolution by an order of magnitude over existing methodologies. The second work describes a 32 bit embedded SPARC microcontroller designed for high performance motor control. The third details the utilization of a compact neural net design for precisely controlling electrical motor current. The forth work describes FPGA implementation of a Java processor designed to speed up applications v ritten in the popular Java programming language. The FPGA implementation is flexible, allowing the update of the processor design as the Java specification evolves. The fifth article describes the memory architecture of a high performance reconfigurable ATM switch supporting advanced features such as backpressure. The sixth pap r describes an ASIC implementation of the IDEA encryption algorithm. The authors describe an implementation that takes advantage of both temporal and spatial parallelism available in the IDEA algorithm. The HiPCrypto ASIC can encrypt/decrypt data at rates of up to 4.4 Gbps.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129333026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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