Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492516
Suhwan Kim, H. Krishnamurthy, S. Amin, Sheldon Weng, Jin Feng, H. Do, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De
A 1S direct-battery-attach buck converter with a 5-stack, thin-gate-FinFET power train delivers a peak efficiency of 89.2% for a 3.8V in to 1.8V out, with 10x higher power density (~15A/mm2), switching at up to 10x higher frequency (40MHz) using 4x-10x lower inductance (10-100nH) than state of the art. Cascaded self-timed drivers and soft-switching low-side drivers minimize complexity in driving 10 individual power switches safely.
{"title":"A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers","authors":"Suhwan Kim, H. Krishnamurthy, S. Amin, Sheldon Weng, Jin Feng, H. Do, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De","doi":"10.23919/VLSICircuits52068.2021.9492516","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492516","url":null,"abstract":"A 1S direct-battery-attach buck converter with a 5-stack, thin-gate-FinFET power train delivers a peak efficiency of 89.2% for a 3.8V in to 1.8V out, with 10x higher power density (~15A/mm2), switching at up to 10x higher frequency (40MHz) using 4x-10x lower inductance (10-100nH) than state of the art. Cascaded self-timed drivers and soft-switching low-side drivers minimize complexity in driving 10 individual power switches safely.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133638798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492345
S. Kim, Dongkwun Kim, Ayushparth Sharma, Mingoo Seok
This paper presents EQZ-LDO, a digital low drop-out regulator (LDO) with attack detection and detection-driven protection for side-channel attack (SCA) resiliency. It typically incurs only 0.5% energy-delay-product (EDP) overhead since the proposed detection-driven scheme exercises protection only when the AES is under attack. This enables to amortize the EDP overhead over the lifetime of an Internet of Things (IoT) device. It still achieves very strong resiliency to SCA, demonstrating the protection of a 128b AES core from >10M-trace correlation power analysis (CPA).
{"title":"EQZ-LDO: A Near-Zero EDP Overhead, >10M-Attack-Resilient, Secure Digital LDO featuring Attack-Detection and Detection-Driven Protection for a Correlation-Power-Analysis-Resilient IoT Device","authors":"S. Kim, Dongkwun Kim, Ayushparth Sharma, Mingoo Seok","doi":"10.23919/VLSICircuits52068.2021.9492345","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492345","url":null,"abstract":"This paper presents EQZ-LDO, a digital low drop-out regulator (LDO) with attack detection and detection-driven protection for side-channel attack (SCA) resiliency. It typically incurs only 0.5% energy-delay-product (EDP) overhead since the proposed detection-driven scheme exercises protection only when the AES is under attack. This enables to amortize the EDP overhead over the lifetime of an Internet of Things (IoT) device. It still achieves very strong resiliency to SCA, demonstrating the protection of a 128b AES core from >10M-trace correlation power analysis (CPA).","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133124848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492406
Soon-Jae Kweon, Joonho Gil, Chulhyun Park, Sein Oh, Yoontae Jung, Injun Choi, Song-I Cheon, Hung Phan Dang, Ja-Hyuck Koo, Geunhoe Kim, S. Ha, M. Je
We present an impedance-monitoring IC achieving a wide frequency range (FR) and fast output data rate (ODR). The proposed IC support a wide FR with improved spectral density by down-converting the signal to the intermediate frequency (fIF) in front of the instrumentation amplifier (IA) using the LO signal generated by a single-side-band (SSB) mixer. The proposed IF-sampling architecture does not require narrow-bandwidth (BW) low-pass filter (LPF), resulting in a fast ODR. A time-interleaved (TI) DFT is also employed to further improve the ODR. A band-pass delta-sigma ADC (BP-ΔΣ-ADC) with the auto-calibration and BP truncation is adopted to achieve the best noise performance at fIF. The fabricated IC achieves 0.35ΩRMS resolution in the FR from 4kHz to 8MHz with 122.1Hz BW while providing the ODR up to 31.25kS/s.
{"title":"An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC","authors":"Soon-Jae Kweon, Joonho Gil, Chulhyun Park, Sein Oh, Yoontae Jung, Injun Choi, Song-I Cheon, Hung Phan Dang, Ja-Hyuck Koo, Geunhoe Kim, S. Ha, M. Je","doi":"10.23919/VLSICircuits52068.2021.9492406","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492406","url":null,"abstract":"We present an impedance-monitoring IC achieving a wide frequency range (FR) and fast output data rate (ODR). The proposed IC support a wide FR with improved spectral density by down-converting the signal to the intermediate frequency (fIF) in front of the instrumentation amplifier (IA) using the LO signal generated by a single-side-band (SSB) mixer. The proposed IF-sampling architecture does not require narrow-bandwidth (BW) low-pass filter (LPF), resulting in a fast ODR. A time-interleaved (TI) DFT is also employed to further improve the ODR. A band-pass delta-sigma ADC (BP-ΔΣ-ADC) with the auto-calibration and BP truncation is adopted to achieve the best noise performance at fIF. The fabricated IC achieves 0.35ΩRMS resolution in the FR from 4kHz to 8MHz with 122.1Hz BW while providing the ODR up to 31.25kS/s.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115400810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492478
Jaehwan Ko, Yeunhee Huh, Min-Woo Ko, Gyeong-Gu Kang, G. Cho, Hyunsik Kim
This paper presents an always-dual-path (ADP) DC-DC converter that achieves 4.5V-input 0.3-to-1.7V-output buck conversion for battery-powered low-voltage SoCs. Regardless of voltage conversion ratio (VCR), the proposed ADP converter maintains the inductor current constantly to be ×0.5 of the load current, bringing high efficiency with a large DCR of the compact-volume inductor. Seamless dual-power-path formed by two flying-capacitors merits a low ripple. The chip fabricated in 180-nm 5V CMOS obtains an efficiency of 91.5% (84.6%) at a VCR of 0.38 (0.2) even with an inductor DCR of 250mΩ.
{"title":"A 4.5V-Input 0.3-to-1.7V-Output Step-Down Always-Dual-Path DC-DC Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs","authors":"Jaehwan Ko, Yeunhee Huh, Min-Woo Ko, Gyeong-Gu Kang, G. Cho, Hyunsik Kim","doi":"10.23919/VLSICircuits52068.2021.9492478","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492478","url":null,"abstract":"This paper presents an always-dual-path (ADP) DC-DC converter that achieves 4.5V-input 0.3-to-1.7V-output buck conversion for battery-powered low-voltage SoCs. Regardless of voltage conversion ratio (VCR), the proposed ADP converter maintains the inductor current constantly to be ×0.5 of the load current, bringing high efficiency with a large DCR of the compact-volume inductor. Seamless dual-power-path formed by two flying-capacitors merits a low ripple. The chip fabricated in 180-nm 5V CMOS obtains an efficiency of 91.5% (84.6%) at a VCR of 0.38 (0.2) even with an inductor DCR of 250mΩ.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115444132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492418
Nicky Lu, C. Shiah, Juang-Ying Chueh, B. Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, C. Chang, Tzung-Shen Chen
Two inventions improve DRAM’s core circuits within a 1Gb DDR3 product: (1) Scale VCC down to 0.7V but generate a Restore ONE signal 1.3V into memory cells to enhance Retention-Time at least to 138ms at 125°C. This facilitates scaling VDD and peripheral devices. (2) When addresses are ready in the DRAM-controller, an Interface Circuitry enables pre-decoding Row/Column addresses into the DRAM before other Commands, thus accelerating Random-Access Row/Column Times by 1.5ns, respectively.
{"title":"Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns","authors":"Nicky Lu, C. Shiah, Juang-Ying Chueh, B. Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, C. Chang, Tzung-Shen Chen","doi":"10.23919/VLSICircuits52068.2021.9492418","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492418","url":null,"abstract":"Two inventions improve DRAM’s core circuits within a 1Gb DDR3 product: (1) Scale VCC down to 0.7V but generate a Restore ONE signal 1.3V into memory cells to enhance Retention-Time at least to 138ms at 125°C. This facilitates scaling VDD and peripheral devices. (2) When addresses are ready in the DRAM-controller, an Interface Circuitry enables pre-decoding Row/Column addresses into the DRAM before other Commands, thus accelerating Random-Access Row/Column Times by 1.5ns, respectively.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114412487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492444
Jinseok Lee, Hossein Valavi, Yinqi Tang, N. Verma
This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multi-level input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm2 (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.
{"title":"Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs","authors":"Jinseok Lee, Hossein Valavi, Yinqi Tang, N. Verma","doi":"10.23919/VLSICircuits52068.2021.9492444","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492444","url":null,"abstract":"This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multi-level input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm2 (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114950671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492441
Huajun Zhang, M. Berkhout, K. Makinwa, Qinwen Fan
This paper reports a Class-D audio amplifier that uses multiloop feedback to suppress output LC filter nonlinearity by 49 dB, enabling the use of small, low-cost LC filters with ±30% spread while maintaining low distortion. Fabricated in a 180 nm BCD process, the prototype achieves a THD of −121.5 dB and a THD+N of −107.1 dB. It delivers 12W/21W into an 8-Ω/4-Ω load with 91%/87% efficiency.
{"title":"A −121.5 dB THD Class-D Audio Amplifier with 49 dB Suppression of LC Filter Nonlinearity and Robust to +/−30% LC Filter Spread","authors":"Huajun Zhang, M. Berkhout, K. Makinwa, Qinwen Fan","doi":"10.23919/VLSICircuits52068.2021.9492441","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492441","url":null,"abstract":"This paper reports a Class-D audio amplifier that uses multiloop feedback to suppress output LC filter nonlinearity by 49 dB, enabling the use of small, low-cost LC filters with ±30% spread while maintaining low distortion. Fabricated in a 180 nm BCD process, the prototype achieves a THD of −121.5 dB and a THD+N of −107.1 dB. It delivers 12W/21W into an 8-Ω/4-Ω load with 91%/87% efficiency.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123591450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492482
Shiwei Wang, M. Ballini, Xiaolin Yang, C. Sawigun, J. Weijers, Dwaipayan Biswas, C. Lopez
This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm2 per channel, an input-referred noise of 5.53±0.36µVrms in the AP band and 2.88±0.18µVrms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.
{"title":"A 77-dB DR 16-Ch 2nd-order Δ-ΔΣ Neural Recording Chip with 0.0077mm2/Ch","authors":"Shiwei Wang, M. Ballini, Xiaolin Yang, C. Sawigun, J. Weijers, Dwaipayan Biswas, C. Lopez","doi":"10.23919/VLSICircuits52068.2021.9492482","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492482","url":null,"abstract":"This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm2 per channel, an input-referred noise of 5.53±0.36µVrms in the AP band and 2.88±0.18µVrms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130625014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492486
J. Sharma, Hao Li, Z. Xuan, Ranjeet Kumar, Chun-Ming Hsu, M. Sakib, P. Liao, H. Rong, J. Jaussi, G. Balamurugan
We present a 4λ×112 Gb/s/λ hybrid-integrated silicon photonic TX suitable for 400G Ethernet modules and co-packaged optics. The photonic IC (PIC) uses cascaded micro-ring modulators (MRMs) with integrated heaters for efficient wavelength division multiplexing (WDM). The 28nm CMOS electronic IC includes PAM4 MRM drivers with nonlinear FFE and control circuits to stabilize MRM performance against process and temperature variations. A thermal control scheme based on sensing MRM photocurrents is used to minimize monitoring hardware in the PIC. Measured results demonstrate 112 Gb/s PAM4 operation with <0.7 dB TDECQ from each of the 4 channels. To our best knowledge, this is the highest per-λ data rate reported for an O-band ring-based WDM transmitter.
{"title":"Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS","authors":"J. Sharma, Hao Li, Z. Xuan, Ranjeet Kumar, Chun-Ming Hsu, M. Sakib, P. Liao, H. Rong, J. Jaussi, G. Balamurugan","doi":"10.23919/VLSICircuits52068.2021.9492486","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492486","url":null,"abstract":"We present a 4λ×112 Gb/s/λ hybrid-integrated silicon photonic TX suitable for 400G Ethernet modules and co-packaged optics. The photonic IC (PIC) uses cascaded micro-ring modulators (MRMs) with integrated heaters for efficient wavelength division multiplexing (WDM). The 28nm CMOS electronic IC includes PAM4 MRM drivers with nonlinear FFE and control circuits to stabilize MRM performance against process and temperature variations. A thermal control scheme based on sensing MRM photocurrents is used to minimize monitoring hardware in the PIC. Measured results demonstrate 112 Gb/s PAM4 operation with <0.7 dB TDECQ from each of the 4 channels. To our best knowledge, this is the highest per-λ data rate reported for an O-band ring-based WDM transmitter.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492518
Ji-Seon Paek, Dongsu Kim, Jae-Yeol Han, Younghwan Choo, Jongwoo Lee
This paper presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on LTE and 5G bands. The designed fully switched-mode SM consists of a fast buck converter and a slow buck converter, and it achieves 88.2% peak efficiency with a low RX band noise of -140dBm/Hz at the SM output. The designed 5G NR SM, consisting of a class-AB linear amplifier (LA) and an interleaved 3-level buck-boost converter provides a 150-MHz 3-dB bandwidth for tracking the 100-MHz envelope signal. An optimal RF-PA supply deployment using the two SMs efficiently supports multiple RF-PA loads while satisfying the dual transmission requirements of E-UTRAN New Radio Dual-Connectivity (EN-DC) and 5G 100-MHz ET operation.
本文提出了一种双芯片供电调制架构，使用全开关模式供电调制器(SM)和线性辅助混合SM来实现有效的射频功率放大，以支持LTE和5G频段上的同时传输。所设计的全开关模式SM由一个快降压转换器和一个慢降压转换器组成，在SM输出端实现了88.2%的峰值效率和-140dBm/Hz的低RX波段噪声。设计的5G NR SM由ab类线性放大器(LA)和交错3电平降压-升压转换器组成，提供150-MHz 3-dB带宽，用于跟踪100-MHz包络信号。使用两个SMs的最佳RF-PA电源部署有效地支持多个RF-PA负载，同时满足E-UTRAN新无线电双连接(EN-DC)和5G 100-MHz ET操作的双传输要求。
{"title":"Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front-End","authors":"Ji-Seon Paek, Dongsu Kim, Jae-Yeol Han, Younghwan Choo, Jongwoo Lee","doi":"10.23919/VLSICircuits52068.2021.9492518","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492518","url":null,"abstract":"This paper presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on LTE and 5G bands. The designed fully switched-mode SM consists of a fast buck converter and a slow buck converter, and it achieves 88.2% peak efficiency with a low RX band noise of -140dBm/Hz at the SM output. The designed 5G NR SM, consisting of a class-AB linear amplifier (LA) and an interleaved 3-level buck-boost converter provides a 150-MHz 3-dB bandwidth for tracking the 100-MHz envelope signal. An optimal RF-PA supply deployment using the two SMs efficiently supports multiple RF-PA loads while satisfying the dual transmission requirements of E-UTRAN New Radio Dual-Connectivity (EN-DC) and 5G 100-MHz ET operation.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121285862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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