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A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers 采用5堆叠薄栅极22nm FinFET CMOS的1S直接电池贴合集成降压稳压器,具有有源电压平衡和级联自导通驱动器
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492516
Suhwan Kim, H. Krishnamurthy, S. Amin, Sheldon Weng, Jin Feng, H. Do, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De
A 1S direct-battery-attach buck converter with a 5-stack, thin-gate-FinFET power train delivers a peak efficiency of 89.2% for a 3.8V in to 1.8V out, with 10x higher power density (~15A/mm2), switching at up to 10x higher frequency (40MHz) using 4x-10x lower inductance (10-100nH) than state of the art. Cascaded self-timed drivers and soft-switching low-side drivers minimize complexity in driving 10 individual power switches safely.
1S电池直接贴合降压变换器采用5堆叠、薄栅极finfet电源串,在3.8V输入到1.8V输出时,峰值效率可达89.2%,功率密度提高10倍(~15A/mm2),开关频率提高10倍(40MHz),电感降低4 -10倍(10-100nH)。级联自定时驱动器和软开关低侧驱动器最大限度地降低了安全驱动10个单独电源开关的复杂性。
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引用次数: 1
EQZ-LDO: A Near-Zero EDP Overhead, >10M-Attack-Resilient, Secure Digital LDO featuring Attack-Detection and Detection-Driven Protection for a Correlation-Power-Analysis-Resilient IoT Device EQZ-LDO:近零EDP开销,> 10m攻击弹性,安全数字LDO,具有攻击检测和检测驱动保护功能,适用于相关功率分析弹性物联网设备
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492345
S. Kim, Dongkwun Kim, Ayushparth Sharma, Mingoo Seok
This paper presents EQZ-LDO, a digital low drop-out regulator (LDO) with attack detection and detection-driven protection for side-channel attack (SCA) resiliency. It typically incurs only 0.5% energy-delay-product (EDP) overhead since the proposed detection-driven scheme exercises protection only when the AES is under attack. This enables to amortize the EDP overhead over the lifetime of an Internet of Things (IoT) device. It still achieves very strong resiliency to SCA, demonstrating the protection of a 128b AES core from >10M-trace correlation power analysis (CPA).
本文介绍了EQZ-LDO,一种具有攻击检测和检测驱动保护的数字低差稳压器(LDO),用于侧信道攻击(SCA)弹性。它通常只产生0.5%的能量延迟积(EDP)开销,因为提议的检测驱动方案仅在AES受到攻击时才进行保护。这使得在物联网(IoT)设备的生命周期内分摊EDP开销成为可能。它仍然实现了非常强的抗SCA弹性,证明了128b AES核心对> 10m迹相关功率分析(CPA)的保护。
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引用次数: 5
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC 基于中频采样架构的8MHz 31.25kS/s阻抗监测IC,带通Delta-Sigma ADC
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492406
Soon-Jae Kweon, Joonho Gil, Chulhyun Park, Sein Oh, Yoontae Jung, Injun Choi, Song-I Cheon, Hung Phan Dang, Ja-Hyuck Koo, Geunhoe Kim, S. Ha, M. Je
We present an impedance-monitoring IC achieving a wide frequency range (FR) and fast output data rate (ODR). The proposed IC support a wide FR with improved spectral density by down-converting the signal to the intermediate frequency (fIF) in front of the instrumentation amplifier (IA) using the LO signal generated by a single-side-band (SSB) mixer. The proposed IF-sampling architecture does not require narrow-bandwidth (BW) low-pass filter (LPF), resulting in a fast ODR. A time-interleaved (TI) DFT is also employed to further improve the ODR. A band-pass delta-sigma ADC (BP-ΔΣ-ADC) with the auto-calibration and BP truncation is adopted to achieve the best noise performance at fIF. The fabricated IC achieves 0.35ΩRMS resolution in the FR from 4kHz to 8MHz with 122.1Hz BW while providing the ODR up to 31.25kS/s.
我们提出了一种实现宽频率范围(FR)和快速输出数据速率(ODR)的阻抗监测IC。所提出的集成电路通过使用单边带混频器(SSB)产生的LO信号在仪表放大器(IA)前将信号下变频到中频(fIF),从而支持宽FR和改进的频谱密度。所提出的中频采样架构不需要窄带带宽(BW)低通滤波器(LPF),从而实现快速的ODR。还采用了时间交错(TI) DFT来进一步提高ODR。采用带通δ - σ ADC (BP-ΔΣ-ADC),具有自动校准和BP截断功能,可在fIF下获得最佳噪声性能。制造的IC在4kHz至8MHz的FR中实现0.35ΩRMS分辨率,BW为122.1Hz, ODR高达31.25kS/s。
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引用次数: 2
A 4.5V-Input 0.3-to-1.7V-Output Step-Down Always-Dual-Path DC-DC Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs 一种4.5 v输入0.3 ~ 1.7 v输出降压型双路DC-DC变换器,具有250mΩ-DCR电感,用于低压soc,效率为91.5%
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492478
Jaehwan Ko, Yeunhee Huh, Min-Woo Ko, Gyeong-Gu Kang, G. Cho, Hyunsik Kim
This paper presents an always-dual-path (ADP) DC-DC converter that achieves 4.5V-input 0.3-to-1.7V-output buck conversion for battery-powered low-voltage SoCs. Regardless of voltage conversion ratio (VCR), the proposed ADP converter maintains the inductor current constantly to be ×0.5 of the load current, bringing high efficiency with a large DCR of the compact-volume inductor. Seamless dual-power-path formed by two flying-capacitors merits a low ripple. The chip fabricated in 180-nm 5V CMOS obtains an efficiency of 91.5% (84.6%) at a VCR of 0.38 (0.2) even with an inductor DCR of 250mΩ.
本文提出了一种总双路(ADP) DC-DC转换器,可实现4.5 v输入0.3到1.7 v输出降压转换,用于电池供电的低压soc。在不考虑电压转换比(VCR)的情况下,本文提出的ADP变换器使电感电流始终保持在负载电流的×0.5,以小体积电感的大DCR带来高效率。由两个飞行电容器形成的无缝双功率路径具有低纹波的优点。该芯片采用180nm 5V CMOS工艺,在VCR为0.38(0.2)的情况下,即使电感DCR为250mΩ,效率也高达91.5%(84.6%)。
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引用次数: 8
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns 用于缩放DRAM的增强核心电路:0.7V VCC,在125°C下保持138ms,随机行/列访问时间加速1.5ns
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492418
Nicky Lu, C. Shiah, Juang-Ying Chueh, B. Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, C. Chang, Tzung-Shen Chen
Two inventions improve DRAM’s core circuits within a 1Gb DDR3 product: (1) Scale VCC down to 0.7V but generate a Restore ONE signal 1.3V into memory cells to enhance Retention-Time at least to 138ms at 125°C. This facilitates scaling VDD and peripheral devices. (2) When addresses are ready in the DRAM-controller, an Interface Circuitry enables pre-decoding Row/Column addresses into the DRAM before other Commands, thus accelerating Random-Access Row/Column Times by 1.5ns, respectively.
两项发明改进了1Gb DDR3产品内的DRAM核心电路:(1)将VCC降至0.7V,但在存储单元中产生1.3V的Restore ONE信号,以在125°C下将保留时间至少提高到138ms。这有助于扩展VDD和外围设备。(2)当地址在DRAM控制器中准备好时,接口电路可以在其他命令之前将行/列地址预解码到DRAM中,从而使随机访问行/列时间分别加快1.5ns。
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引用次数: 0
Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs 全行/列并行内存计算SRAM宏,采用基于电容的5-b输入混合信号计算
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492444
Jinseok Lee, Hossein Valavi, Yinqi Tang, N. Verma
This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multi-level input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm2 (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.
本文提出了一个28纳米内存计算(IMC)宏,用于完全行/列并行矩阵向量乘法(MVM),利用精确的基于电容的模拟计算,从二进制输入向量元素扩展到5-b输入向量元素,从而提高16倍的能源效率和5倍的吞吐量。1152(row)x256(cold)宏采用基于数字开关DAC实现的多级输入驱动器,其保持的计算精度远远超过输出adc的8-b分辨率,并且其面积通过动态范围加倍(DRD)技术减半。该宏实现了最高的IMC能效(5796 TOPS/W)和计算密度(12 TOPS/mm2)(均归一化为1-b ops)。CIFAR-10图像分类的准确率达到91%,达到理想的软件实现水平。
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引用次数: 29
A −121.5 dB THD Class-D Audio Amplifier with 49 dB Suppression of LC Filter Nonlinearity and Robust to +/−30% LC Filter Spread - 121.5 dB THD类d音频放大器,具有49 dB的LC滤波器非线性抑制和+/ - 30% LC滤波器扩展鲁棒性
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492441
Huajun Zhang, M. Berkhout, K. Makinwa, Qinwen Fan
This paper reports a Class-D audio amplifier that uses multiloop feedback to suppress output LC filter nonlinearity by 49 dB, enabling the use of small, low-cost LC filters with ±30% spread while maintaining low distortion. Fabricated in a 180 nm BCD process, the prototype achieves a THD of −121.5 dB and a THD+N of −107.1 dB. It delivers 12W/21W into an 8-Ω/4-Ω load with 91%/87% efficiency.
本文报道了一种d类音频放大器,该放大器使用多环反馈将输出LC滤波器的非线性抑制了49 dB,从而可以在保持低失真的同时使用±30%扩展的小型低成本LC滤波器。在180 nm的BCD工艺中,原型实现了- 121.5 dB的THD和- 107.1 dB的THD+N。它提供12W/21W到8-Ω/4-Ω负载,效率为91%/87%。
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引用次数: 3
A 77-dB DR 16-Ch 2nd-order Δ-ΔΣ Neural Recording Chip with 0.0077mm2/Ch 一种77 db DR 16-Ch二阶Δ-ΔΣ神经记录芯片,0.0077mm2/Ch
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492482
Shiwei Wang, M. Ballini, Xiaolin Yang, C. Sawigun, J. Weijers, Dwaipayan Biswas, C. Lopez
This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm2 per channel, an input-referred noise of 5.53±0.36µVrms in the AP band and 2.88±0.18µVrms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.
本文提出了一种可扩展的16通道神经记录芯片,能够同时采集动作电位(APs),局部场电位(LFPs),电极直流偏移(edo)和刺激伪影(SAs)而不饱和。通过将直流耦合Δ-ΔΣ架构与新的自举和斩波方案相结合,所提出的读出IC实现了每通道面积为0.0077mm2, AP频段的输入参考噪声为5.53±0.36µVrms, LFP频段的输入参考噪声为2.88±0.18µVrms,动态范围(DR)为77dB, EDO公差为±70mV,输入阻抗为283MΩ。该芯片已在体外环境中进行了验证,证明即使使用小的高阻抗电极也能记录细胞外信号。由于实现的面积小,该结构可用于实现大规模电生理的超高密度神经探针。
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引用次数: 5
Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS 基于硅光子微环调制器的4 × 112 Gb/s o波段WDM发射机,基于环形光电流的28nm CMOS热控制
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492486
J. Sharma, Hao Li, Z. Xuan, Ranjeet Kumar, Chun-Ming Hsu, M. Sakib, P. Liao, H. Rong, J. Jaussi, G. Balamurugan
We present a 4λ×112 Gb/s/λ hybrid-integrated silicon photonic TX suitable for 400G Ethernet modules and co-packaged optics. The photonic IC (PIC) uses cascaded micro-ring modulators (MRMs) with integrated heaters for efficient wavelength division multiplexing (WDM). The 28nm CMOS electronic IC includes PAM4 MRM drivers with nonlinear FFE and control circuits to stabilize MRM performance against process and temperature variations. A thermal control scheme based on sensing MRM photocurrents is used to minimize monitoring hardware in the PIC. Measured results demonstrate 112 Gb/s PAM4 operation with <0.7 dB TDECQ from each of the 4 channels. To our best knowledge, this is the highest per-λ data rate reported for an O-band ring-based WDM transmitter.
我们提出了一种4λ×112 Gb/s/λ混合集成硅光子TX,适用于400G以太网模块和共封装光学器件。光子集成电路(PIC)采用级联微环调制器(MRMs)和集成加热器来实现高效的波分复用(WDM)。28nm CMOS电子集成电路包括PAM4 MRM驱动器,非线性FFE和控制电路,以稳定MRM性能,抵抗工艺和温度变化。一种基于MRM光电流传感的热控制方案被用于最小化PIC中的监控硬件。测量结果显示,PAM4运行速度为112 Gb/s, 4个通道的TDECQ均<0.7 dB。据我们所知,这是o波段环形WDM发射机报告的最高每λ数据速率。
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引用次数: 4
Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front-End 用于4G LTE和5G NR双连接射频前端的高效RF- pa双芯片电源调制器架构
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492518
Ji-Seon Paek, Dongsu Kim, Jae-Yeol Han, Younghwan Choo, Jongwoo Lee
This paper presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on LTE and 5G bands. The designed fully switched-mode SM consists of a fast buck converter and a slow buck converter, and it achieves 88.2% peak efficiency with a low RX band noise of -140dBm/Hz at the SM output. The designed 5G NR SM, consisting of a class-AB linear amplifier (LA) and an interleaved 3-level buck-boost converter provides a 150-MHz 3-dB bandwidth for tracking the 100-MHz envelope signal. An optimal RF-PA supply deployment using the two SMs efficiently supports multiple RF-PA loads while satisfying the dual transmission requirements of E-UTRAN New Radio Dual-Connectivity (EN-DC) and 5G 100-MHz ET operation.
本文提出了一种双芯片供电调制架构,使用全开关模式供电调制器(SM)和线性辅助混合SM来实现有效的射频功率放大,以支持LTE和5G频段上的同时传输。所设计的全开关模式SM由一个快降压转换器和一个慢降压转换器组成,在SM输出端实现了88.2%的峰值效率和-140dBm/Hz的低RX波段噪声。设计的5G NR SM由ab类线性放大器(LA)和交错3电平降压-升压转换器组成,提供150-MHz 3-dB带宽,用于跟踪100-MHz包络信号。使用两个SMs的最佳RF-PA电源部署有效地支持多个RF-PA负载,同时满足E-UTRAN新无线电双连接(EN-DC)和5G 100-MHz ET操作的双传输要求。
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引用次数: 3
期刊
2021 Symposium on VLSI Circuits
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