Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150298
L. Breuil, J. Lisoni, P. Blomme, G. Van den bosch, J. van Houdt
The required transition from Control Gate wrap-around to planar structure for NAND flash scaling below 20nm node causes important loss of coupling factor. In order to recover the Programming window, we develop a Hybrid Floating Gate using Ru as high work-function metal. With a proper nitridation of the underlying Si and ALD technique, we obtain a continuous Ru layer as thin as 2nm that is thermally stable in contact with Si. Thanks to the higher work function of Ru, a programming window of more than 10V has been be achieved.
{"title":"Optimization of Ru Based Hybrid Floating Gate for Planar NAND Flash","authors":"L. Breuil, J. Lisoni, P. Blomme, G. Van den bosch, J. van Houdt","doi":"10.1109/IMW.2015.7150298","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150298","url":null,"abstract":"The required transition from Control Gate wrap-around to planar structure for NAND flash scaling below 20nm node causes important loss of coupling factor. In order to recover the Programming window, we develop a Hybrid Floating Gate using Ru as high work-function metal. With a proper nitridation of the underlying Si and ALD technique, we obtain a continuous Ru layer as thin as 2nm that is thermally stable in contact with Si. Thanks to the higher work function of Ru, a programming window of more than 10V has been be achieved.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150283
Hao Wang, Kai Zhao, Tong Zhang
DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell-induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10-4 ~ 10-3 at very small (even negligible) latency overhead.
{"title":"Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes","authors":"Hao Wang, Kai Zhao, Tong Zhang","doi":"10.1109/IMW.2015.7150283","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150283","url":null,"abstract":"DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell-induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10-4 ~ 10-3 at very small (even negligible) latency overhead.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130793891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150277
Shun Okamoto, Chao Sun, Shogo Hachiya, Tomoaki Yamada, Yusuke Saito, T. Iwasaki, K. Takeuchi
In order to efficiently store, retrieve and process big data, the data-centric computing paradigm is adopted and an application-driven storage class memory (SCM)/NAND flash hybrid solid-state drive (SSD) is designed. SSD data management algorithms minimize data movement inside the storage system and the SSD system design parameter, SCM/NAND capacity ratio, is chosen depending on the application. Design guidelines are proposed, based on the evaluation of three SCM/NAND flash hybrid SSDs with: (1) write-back (WB) cache, (2) write-optimized data management (WO-DM) and (3) read-write balanced data management (RWB-DM) algorithms. The WO-DM algorithm achieves the highest SSD performance for write-intensive applications, whereas RWB-DM is most appropriate for read-hot (frequently accessed)-random workloads. As long as the workload is not read-cold-sequential or write-cold-sequential, adding SCM to the NAND SSD system is cost-effective to boost performance. Less than 10% SCM/NAND capacity ratios provides 10x speed, compared to the NAND flash-only SSD.
{"title":"Application Driven SCM and NAND Flash Hybrid SSD Design for Data-Centric Computing System","authors":"Shun Okamoto, Chao Sun, Shogo Hachiya, Tomoaki Yamada, Yusuke Saito, T. Iwasaki, K. Takeuchi","doi":"10.1109/IMW.2015.7150277","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150277","url":null,"abstract":"In order to efficiently store, retrieve and process big data, the data-centric computing paradigm is adopted and an application-driven storage class memory (SCM)/NAND flash hybrid solid-state drive (SSD) is designed. SSD data management algorithms minimize data movement inside the storage system and the SSD system design parameter, SCM/NAND capacity ratio, is chosen depending on the application. Design guidelines are proposed, based on the evaluation of three SCM/NAND flash hybrid SSDs with: (1) write-back (WB) cache, (2) write-optimized data management (WO-DM) and (3) read-write balanced data management (RWB-DM) algorithms. The WO-DM algorithm achieves the highest SSD performance for write-intensive applications, whereas RWB-DM is most appropriate for read-hot (frequently accessed)-random workloads. As long as the workload is not read-cold-sequential or write-cold-sequential, adding SCM to the NAND SSD system is cost-effective to boost performance. Less than 10% SCM/NAND capacity ratios provides 10x speed, compared to the NAND flash-only SSD.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125735515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150278
M. Barci, G. Molas, A. Toffoli, M. Bernard, A. Roule, C. Cagli, J. Cluzel, E. Vianello, B. De Salvo, L. Perniola
In this paper, a detailed reliability analysis of metal-oxide CBRAM devices is presented. We demonstrated that the addition of a thin metal-oxide layer in the bottom of the memory stack significantly increases the ROFF and the memory window (more than 1 decade), with improved endurance performance. At the same time, high thermal stability was also achieved (window margin constant during more than 24 hours at 250°C). The origin of the window margin degradation during endurance is discussed and interpreted by means of a Trap Assisted Tunneling Model, putting in evidence the role of defect generation and Cu residual atoms in the resistive layer.
{"title":"Bilayer Metal-Oxide CBRAM Technology for Improved Window Margin and Reliability","authors":"M. Barci, G. Molas, A. Toffoli, M. Bernard, A. Roule, C. Cagli, J. Cluzel, E. Vianello, B. De Salvo, L. Perniola","doi":"10.1109/IMW.2015.7150278","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150278","url":null,"abstract":"In this paper, a detailed reliability analysis of metal-oxide CBRAM devices is presented. We demonstrated that the addition of a thin metal-oxide layer in the bottom of the memory stack significantly increases the ROFF and the memory window (more than 1 decade), with improved endurance performance. At the same time, high thermal stability was also achieved (window margin constant during more than 24 hours at 250°C). The origin of the window margin degradation during endurance is discussed and interpreted by means of a Trap Assisted Tunneling Model, putting in evidence the role of defect generation and Cu residual atoms in the resistive layer.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"57 6 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116517976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150293
Lorenzo Zuolo, C. Zambelli, P. Olivo, R. Micheloni, A. Marelli
The reliability of the non-volatile NAND flash memories, measured in terms of Raw Bit Error Rate (RBER), is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it becomes essential exploiting powerful correction algorithms such as the Low Density Parity Check (LDPC). However, the burdens of this approach materialize in an increased NAND flash power consumption due to the increased memory read latencies that translates in limited disk performance. In this work it is performed a comparison between a standard LDPC decoding approach based on hard and soft decisions and an optimized solution called LDPC NAND- Assisted Soft Decision. The simulation results on 2X, 1X and mid-1X MLC NAND flash-based Solid State Drives in terms of NAND flash I/O power consumption, disk read latencies and performance, favor the adoption of the presented solution.
{"title":"LDPC Soft Decoding with Reduced Power and Latency in 1X-2X NAND Flash-Based Solid State Drives","authors":"Lorenzo Zuolo, C. Zambelli, P. Olivo, R. Micheloni, A. Marelli","doi":"10.1109/IMW.2015.7150293","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150293","url":null,"abstract":"The reliability of the non-volatile NAND flash memories, measured in terms of Raw Bit Error Rate (RBER), is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it becomes essential exploiting powerful correction algorithms such as the Low Density Parity Check (LDPC). However, the burdens of this approach materialize in an increased NAND flash power consumption due to the increased memory read latencies that translates in limited disk performance. In this work it is performed a comparison between a standard LDPC decoding approach based on hard and soft decisions and an optimized solution called LDPC NAND- Assisted Soft Decision. The simulation results on 2X, 1X and mid-1X MLC NAND flash-based Solid State Drives in terms of NAND flash I/O power consumption, disk read latencies and performance, favor the adoption of the presented solution.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120949849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150295
F. Merrikh-Bayat, M. Prezioso, X. Guo, B. Hoskins, D. Strukov, K. Likharev
Synapses, the most numerous elements of neural networks, are memory devices. Similarly to traditional memory applications, device density is one of the most essential metrics for large-scale artificial neural networks. This application, however, imposes a number of additional requirements, such as the continuous change of the memory state, so that novel engineering approaches are required. In this paper, we briefly review our recent efforts at addressing these needs. We start by reviewing the CrossNet concept, which was conceived to address major challenges of artificial neural networks. We then discuss the recent progress toward CrossNet implementation, in particular the experimental results for simple networks with crossbar-integrated resistive switching (memristive) metal oxide devices. Finally, we review preliminary results on redesigning commercial-grade embedded NOR flash memories to enable individual cell tuning. While NOR flash memories are less dense then memristor crossbars, their technology is much more mature and ready for the development of large-scale neural networks.
{"title":"Memory Technologies for Neural Networks","authors":"F. Merrikh-Bayat, M. Prezioso, X. Guo, B. Hoskins, D. Strukov, K. Likharev","doi":"10.1109/IMW.2015.7150295","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150295","url":null,"abstract":"Synapses, the most numerous elements of neural networks, are memory devices. Similarly to traditional memory applications, device density is one of the most essential metrics for large-scale artificial neural networks. This application, however, imposes a number of additional requirements, such as the continuous change of the memory state, so that novel engineering approaches are required. In this paper, we briefly review our recent efforts at addressing these needs. We start by reviewing the CrossNet concept, which was conceived to address major challenges of artificial neural networks. We then discuss the recent progress toward CrossNet implementation, in particular the experimental results for simple networks with crossbar-integrated resistive switching (memristive) metal oxide devices. Finally, we review preliminary results on redesigning commercial-grade embedded NOR flash memories to enable individual cell tuning. While NOR flash memories are less dense then memristor crossbars, their technology is much more mature and ready for the development of large-scale neural networks.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127834894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150305
Kyungkyu Min, I. Kwon, S.-H. Cho, Mikyung Kwon, T. Jang, Tae-Kyung Oh, Yong-Taik Kim, S. Cha, Sung-Kye Park, Sung-Joo Hong
This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub-10nm technology node.
{"title":"Study on the Sub-Threshold Margin Characteristics of the Extremely Scaled 3-D DRAM Cell Transistors","authors":"Kyungkyu Min, I. Kwon, S.-H. Cho, Mikyung Kwon, T. Jang, Tae-Kyung Oh, Yong-Taik Kim, S. Cha, Sung-Kye Park, Sung-Joo Hong","doi":"10.1109/IMW.2015.7150305","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150305","url":null,"abstract":"This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub-10nm technology node.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127351719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150284
T. Jew
SRAM and flash are the basis of embedded memory subsystems used in microcontroller applications. Factors such as the application, connectivity, human interfaces, power, safety, and security drive a complex mix of SRAM and flash memory requirements in a microcontroller. This paper explores some of the aspects of the applications which drive how much embedded SRAM and flash memory are required as well as how these memories are embedded in a microcontroller.
{"title":"Embedded Microcontroller Memories: Application Memory Usage","authors":"T. Jew","doi":"10.1109/IMW.2015.7150284","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150284","url":null,"abstract":"SRAM and flash are the basis of embedded memory subsystems used in microcontroller applications. Factors such as the application, connectivity, human interfaces, power, safety, and security drive a complex mix of SRAM and flash memory requirements in a microcontroller. This paper explores some of the aspects of the applications which drive how much embedded SRAM and flash memory are required as well as how these memories are embedded in a microcontroller.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126182588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150268
S. Dutta, S. Mittal, S. Lodha, J. Schulze, U. Ganguly
A planar bulk ZRAM is attractive from a simplicity, cost and scalability perspective - compared to SOI or FinFET based designs. Alternatively, the highly doped p-channel bulk planar ZRAM with electrostatic potential well-based hole-storage is susceptible to random- dopant-fluctuation (RDF) induced VT variability. Here, we propose and evaluate a planar bulk ZRAM device with an intrinsic channel of Si/SiGe/Si hetero-structure epitaxially grown on an n+Si well. TCAD simulations show excellent performance of 660mV VT shift at +/-1.5V operation and IREAD difference of 45μA/μm. In terms of RDF based VT variability, a σVT of 12.8 mV is observed which is estimated to be a small fraction (~51×) of the estimate VT shift (660mV) and 6.47× lower compared to p-doped channel based ZRAM. Initial experiments on MOSCAP devices validate the hole-storage in the SiGe well with a 0.5V VT shift and an excellent read disturb (>1000s).
{"title":"A Bulk Planar SiGe Quantum-Well Based ZRAM with Low Vt Variability","authors":"S. Dutta, S. Mittal, S. Lodha, J. Schulze, U. Ganguly","doi":"10.1109/IMW.2015.7150268","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150268","url":null,"abstract":"A planar bulk ZRAM is attractive from a simplicity, cost and scalability perspective - compared to SOI or FinFET based designs. Alternatively, the highly doped p-channel bulk planar ZRAM with electrostatic potential well-based hole-storage is susceptible to random- dopant-fluctuation (RDF) induced VT variability. Here, we propose and evaluate a planar bulk ZRAM device with an intrinsic channel of Si/SiGe/Si hetero-structure epitaxially grown on an n+Si well. TCAD simulations show excellent performance of 660mV VT shift at +/-1.5V operation and IREAD difference of 45μA/μm. In terms of RDF based VT variability, a σVT of 12.8 mV is observed which is estimated to be a small fraction (~51×) of the estimate VT shift (660mV) and 6.47× lower compared to p-doped channel based ZRAM. Initial experiments on MOSCAP devices validate the hole-storage in the SiGe well with a 0.5V VT shift and an excellent read disturb (>1000s).","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122284432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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