Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150273
R. Lo, P. Du, T. Hsu, C. Wu, Jung-Yi Guo, C. Cheng, H. Lue, Y. Shih, T. Hou, K. Hsieh, Chih-Yuan Lu
Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
{"title":"A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance","authors":"R. Lo, P. Du, T. Hsu, C. Wu, Jung-Yi Guo, C. Cheng, H. Lue, Y. Shih, T. Hou, K. Hsieh, Chih-Yuan Lu","doi":"10.1109/IMW.2015.7150273","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150273","url":null,"abstract":"Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150280
Sangheon Lee, Sooeun Lee, Kibong Moon, Jaehyuk Park, Byungsub Kim, H. Hwang
In this research, an one selector-one ReRAM (1S1R) cross-point array of a multi-level cell (MLC) was demonstrated and investigated. To expand high-density feasibility of cross-point array, MLC pulse writing and reading operations were assessed with parasitic line resistances and capacitances using Matlab and HSPICE simulations. We observed a switching energy is an important parameter for MLC in actual cross-point array in the operating point of view. In addition, not only ReRAM but also selector characteristics are highly important in the device point of view. Therefore, this study serves power efficient guidelines for 1S1R devices and operating schemes of cross-point array.
{"title":"Comprehensive Methodology for ReRAM and Selector Design Guideline of Cross-point Array","authors":"Sangheon Lee, Sooeun Lee, Kibong Moon, Jaehyuk Park, Byungsub Kim, H. Hwang","doi":"10.1109/IMW.2015.7150280","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150280","url":null,"abstract":"In this research, an one selector-one ReRAM (1S1R) cross-point array of a multi-level cell (MLC) was demonstrated and investigated. To expand high-density feasibility of cross-point array, MLC pulse writing and reading operations were assessed with parasitic line resistances and capacitances using Matlab and HSPICE simulations. We observed a switching energy is an important parameter for MLC in actual cross-point array in the operating point of view. In addition, not only ReRAM but also selector characteristics are highly important in the device point of view. Therefore, this study serves power efficient guidelines for 1S1R devices and operating schemes of cross-point array.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150306
Dongyean Oh, Bonghoon Lee, Eunmee Kwon, Sangyong Kim, G. Cho, Sungkye Park, Seokkiu Lee, Sungjoo Hong
We have developed a reliable and predictable TCAD modeling method for retention characteristics of the charge trap NAND Flash device. This modeling method can explain various retention phenomena related to temperature, program pattern, and bake time. The temperature dependency is well described by direct tunneling and thermionic emission, the pattern dependency can be explained by carrier diffusion and the short time retention can be described by the electron-hole dynamics in the storage nitride layer.
{"title":"TCAD Simulation of Data Retention Characteristics of Charge Trap Device for 3-D NAND Flash Memory","authors":"Dongyean Oh, Bonghoon Lee, Eunmee Kwon, Sangyong Kim, G. Cho, Sungkye Park, Seokkiu Lee, Sungjoo Hong","doi":"10.1109/IMW.2015.7150306","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150306","url":null,"abstract":"We have developed a reliable and predictable TCAD modeling method for retention characteristics of the charge trap NAND Flash device. This modeling method can explain various retention phenomena related to temperature, program pattern, and bake time. The temperature dependency is well described by direct tunneling and thermionic emission, the pattern dependency can be explained by carrier diffusion and the short time retention can be described by the electron-hole dynamics in the storage nitride layer.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"342 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124230820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150311
N. Ciocchini, M. Laudato, A. Leone, P. Fantini, A. Lacaita, D. Ielmini
Thermoelectric effects play an important role in phase change memory (PCM), where phase transition and atomic migration are accelerated by temperature. A deep understanding of thermoelectric effects may allow a physics-based design of the cell structure and materials to optimize programming speed/energy and reliability. In this work we study the polarity-dependence of PCM characteristics, including crystallization, melting, electrical switching/holding, and ion migration. These characteristics show slower kinetics at negative voltage, which we attribute to thermoelectric effects of electrically-induced heating. We demonstrate a universal correlation of positive/negative kinetics, which we reproduce by modelling Thomson and Peltier heating in the PCM device.
{"title":"Universal Thermoelectric Characteristic in Phase Change Memories","authors":"N. Ciocchini, M. Laudato, A. Leone, P. Fantini, A. Lacaita, D. Ielmini","doi":"10.1109/IMW.2015.7150311","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150311","url":null,"abstract":"Thermoelectric effects play an important role in phase change memory (PCM), where phase transition and atomic migration are accelerated by temperature. A deep understanding of thermoelectric effects may allow a physics-based design of the cell structure and materials to optimize programming speed/energy and reliability. In this work we study the polarity-dependence of PCM characteristics, including crystallization, melting, electrical switching/holding, and ion migration. These characteristics show slower kinetics at negative voltage, which we attribute to thermoelectric effects of electrically-induced heating. We demonstrate a universal correlation of positive/negative kinetics, which we reproduce by modelling Thomson and Peltier heating in the PCM device.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128961562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150303
A. Grossi, C. Zambelli, P. Olivo, E. Miranda, V. Stikanov, T. Schroeder, C. Walczyk, C. Wenger
In this work, cells behavior during forming is monitored through an incremental pulse and verify algorithm on 4kbit RRAM arrays. This technique allows recognising different cell behaviors in terms of read-verify current oscillation: the impact of these oscillations on reliability and cell-to-cell variability has been investigated during 1k endurance cycles and 100k pulse stress under a variety of cycling conditions. Conductance histograms for the post-forming current reveal the nanosized nature of the filamentary paths across the dielectric film.
{"title":"Relationship among Current Fluctuations during Forming, Cell-To-Cell Variability and Reliability in RRAM Arrays","authors":"A. Grossi, C. Zambelli, P. Olivo, E. Miranda, V. Stikanov, T. Schroeder, C. Walczyk, C. Wenger","doi":"10.1109/IMW.2015.7150303","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150303","url":null,"abstract":"In this work, cells behavior during forming is monitored through an incremental pulse and verify algorithm on 4kbit RRAM arrays. This technique allows recognising different cell behaviors in terms of read-verify current oscillation: the impact of these oscillations on reliability and cell-to-cell variability has been investigated during 1k endurance cycles and 100k pulse stress under a variety of cycling conditions. Conductance histograms for the post-forming current reveal the nanosized nature of the filamentary paths across the dielectric film.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129031567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150287
J. Tranchant, E. Janod, B. Corraze, M. Besland, L. Cario
The application of electrical pulses on Mott insulators AM4Q8 (A = Ga, Ge ; M = V, Nb, Ta, Mo; Q = S, Se) induces a new phenomenon of resistive switching (RS). Appearing above threshold electric fields of a few kV/cm, this volatile transition stabilizes into a non volatile RS for higher electric fields. A pulse protocol alternating short multi-pulses of high voltage with long single pulses of low voltage enables to control this reversible RS in crystals and thin films. The resulting cycling performances obtained on GaV4S8 miniaturized devices demonstrate the interest of these compounds towards Mott memory applications.
电脉冲在Mott绝缘子AM4Q8 (A = Ga, Ge)上的应用M = V, Nb, Ta, Mo;Q = S, Se)引起了一种新的电阻开关现象。出现在几kV/cm的阈值电场之上，这种挥发性跃迁在更高的电场中稳定为非挥发性RS。一种高电压的短多脉冲与低电压的长单脉冲交替的脉冲协议能够控制晶体和薄膜中的可逆RS。在GaV4S8小型化器件上获得的循环性能证明了这些化合物对Mott存储器应用的兴趣。
{"title":"From Resistive Switching Mechanisms in AM4Q8 Mott Insulators to Mott Memories","authors":"J. Tranchant, E. Janod, B. Corraze, M. Besland, L. Cario","doi":"10.1109/IMW.2015.7150287","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150287","url":null,"abstract":"The application of electrical pulses on Mott insulators AM4Q8 (A = Ga, Ge ; M = V, Nb, Ta, Mo; Q = S, Se) induces a new phenomenon of resistive switching (RS). Appearing above threshold electric fields of a few kV/cm, this volatile transition stabilizes into a non volatile RS for higher electric fields. A pulse protocol alternating short multi-pulses of high voltage with long single pulses of low voltage enables to control this reversible RS in crystals and thin films. The resulting cycling performances obtained on GaV4S8 miniaturized devices demonstrate the interest of these compounds towards Mott memory applications.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130306166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150302
Zizhen Jiang, Peng Huang, Liang Zhao, Shahar Kvatinsky, Shimeng Yu, Xiaoyan Liu, Jinfeng Kang, Y. Nishi, H. Wong
A methodology to analyze device-to-circuit characteristics and predict memory array performance is presented. With a five- parameter characterization of the selection device and a compact model of RRAM, we are able to capture the behaviors of reported selection devices and simulate 1S1R cell/array performance with RRAM compact modeling using HSPICE. To predict the performance of the memory array for a variety of selectors, machine-learning algorithms are employed, using device characteristics and circuit simulation results as the training data. The influence of selector parameters on the 1S1R cell and array behavior is investigated and projected to large Gbit arrays. The machine learning methods enable time-efficient and accurate estimates of 1S1R array performance to guide large-scale memory design.
{"title":"Performance Prediction of Large-Scale 1S1R Resistive Memory Array Using Machine Learning","authors":"Zizhen Jiang, Peng Huang, Liang Zhao, Shahar Kvatinsky, Shimeng Yu, Xiaoyan Liu, Jinfeng Kang, Y. Nishi, H. Wong","doi":"10.1109/IMW.2015.7150302","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150302","url":null,"abstract":"A methodology to analyze device-to-circuit characteristics and predict memory array performance is presented. With a five- parameter characterization of the selection device and a compact model of RRAM, we are able to capture the behaviors of reported selection devices and simulate 1S1R cell/array performance with RRAM compact modeling using HSPICE. To predict the performance of the memory array for a variety of selectors, machine-learning algorithms are employed, using device characteristics and circuit simulation results as the training data. The influence of selector parameters on the 1S1R cell and array behavior is investigated and projected to large Gbit arrays. The machine learning methods enable time-efficient and accurate estimates of 1S1R array performance to guide large-scale memory design.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125833424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150266
T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, Y. Shionoiri, K. Kato, T. Okuda, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki
A 16-level cell is demonstrated using a test chip of nonvolatile oxide semiconductor RAM comprising c-axis aligned crystalline In-Ga-Zn oxide FETs. A read circuit composed of voltage followers outputs a read voltage with a maximum distribution of 37 mV. A single voltage follower has a maximum distribution of the read voltage of 25.3 mV. A 200 ns write time of the test chip is demonstrated.
{"title":"A 16-Level-Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET","authors":"T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, Y. Ieda, Naoto Yamade, H. Miyairi, M. Sakakura, Y. Shionoiri, K. Kato, T. Okuda, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki","doi":"10.1109/IMW.2015.7150266","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150266","url":null,"abstract":"A 16-level cell is demonstrated using a test chip of nonvolatile oxide semiconductor RAM comprising c-axis aligned crystalline In-Ga-Zn oxide FETs. A read circuit composed of voltage followers outputs a read voltage with a maximum distribution of 37 mV. A single voltage follower has a maximum distribution of the read voltage of 25.3 mV. A 200 ns write time of the test chip is demonstrated.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125463523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150288
L. Luo, Y. Chow, X. Cai, F. Zhang, Z. Teo, D. Wang, K. Lim, B. Zhou, J. F. Liu, A. Yeo, T. Chang, Y. Kong, C. W. Yap, S. Lup, R. Long, J. B. Tan, D. Shum, N. Do, J. Kim, P. Ghazavi, V. Tiwari
This paper successfully demonstrates a functional and reliable self-aligned, split-gate NVM cell, down to a very competitive and small cell size. This NVM cell is embedded into a 40 nm Low Power (LP) ground rule logic process with copper low-K interconnects. The self- alignment sequence with gate spacer and poly CMP (Chemical Mechanical Polishing) provides an optimized and small cell that can be easily integrated in the standard logic process, in a modular way. This is the first time that the industry has demonstrated a functional split-gate embedded Flash memory cell at 1.1V VDD. This embedded Flash process also yielded on a baseline 32 Mb high-density SRAM test chip as well as a 10% larger automotive-grade embedded Flash cell. We have further demonstrated reliability data that met the tightest market requirements, with a more relaxed 55 nm ground rule on a 16 Mb test array, using the same 40 nm LP process.
{"title":"Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications","authors":"L. Luo, Y. Chow, X. Cai, F. Zhang, Z. Teo, D. Wang, K. Lim, B. Zhou, J. F. Liu, A. Yeo, T. Chang, Y. Kong, C. W. Yap, S. Lup, R. Long, J. B. Tan, D. Shum, N. Do, J. Kim, P. Ghazavi, V. Tiwari","doi":"10.1109/IMW.2015.7150288","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150288","url":null,"abstract":"This paper successfully demonstrates a functional and reliable self-aligned, split-gate NVM cell, down to a very competitive and small cell size. This NVM cell is embedded into a 40 nm Low Power (LP) ground rule logic process with copper low-K interconnects. The self- alignment sequence with gate spacer and poly CMP (Chemical Mechanical Polishing) provides an optimized and small cell that can be easily integrated in the standard logic process, in a modular way. This is the first time that the industry has demonstrated a functional split-gate embedded Flash memory cell at 1.1V VDD. This embedded Flash process also yielded on a baseline 32 Mb high-density SRAM test chip as well as a 10% larger automotive-grade embedded Flash cell. We have further demonstrated reliability data that met the tightest market requirements, with a more relaxed 55 nm ground rule on a 16 Mb test array, using the same 40 nm LP process.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150279
C. Miccoli, K. Sarpatwari, Domenico Di Cicco, Mattia Cichocki, V. Moschiano, P. Ruby, K. Parat
This work aims at providing an accurate and flexible tool to simulate the most advanced placement algorithms for state-of-the-art NAND Flash devices. A model for incremental step pulse programming is discussed and experimentally validated, showing its capability to describe the dependence on the program pulse duration/amplitude and to correctly reproduce the proximity effect and the selective slow program convergence behavior, when a bit line/channel bias is applied. Finally, when the entire memory array is simulated in a Monte Carlo fashion, the placement of our decananometer 3bit/cell device can be accurately reproduced, including the behavior of the advanced programming features.
{"title":"Characterization and Modeling of Advanced Placement Algorithms for NAND Flash Arrays","authors":"C. Miccoli, K. Sarpatwari, Domenico Di Cicco, Mattia Cichocki, V. Moschiano, P. Ruby, K. Parat","doi":"10.1109/IMW.2015.7150279","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150279","url":null,"abstract":"This work aims at providing an accurate and flexible tool to simulate the most advanced placement algorithms for state-of-the-art NAND Flash devices. A model for incremental step pulse programming is discussed and experimentally validated, showing its capability to describe the dependence on the program pulse duration/amplitude and to correctly reproduce the proximity effect and the selective slow program convergence behavior, when a bit line/channel bias is applied. Finally, when the entire memory array is simulated in a Monte Carlo fashion, the placement of our decananometer 3bit/cell device can be accurately reproduced, including the behavior of the advanced programming features.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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