Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150312
M. Kudo, M. Arita, Yasuo Takahashi, K. Ohba, Masayuki Shimuta, I. Fujiwara
The paper shows clear evidence that in-situ transmission electron microscopy (TEM) can be used as a powerful tool to analyze ReRAM operation. Reproducible resistive switching of 100k cycles in 30- or 70-nm Cu-Te CBRAMs was achieved for the first time during in-situ TEM observation. A TEM sample of the CBRAM cells was processed by a focused ion beam method. The formation and rupture of a Cu filament was observed and analyzed in the TEM with energy dispersive x-ray (EDX) mapping. Since the overshoot current at the resistive switching was efficiently suppressed by a MOSFET placed in the TEM holder, stable and reproducible ReRAM switching operations were achieved in the TEM.
{"title":"Visualization of Conductive Filament during Write and Erase Cycles on Nanometer-Scale ReRAM Achieved by In-Situ TEM","authors":"M. Kudo, M. Arita, Yasuo Takahashi, K. Ohba, Masayuki Shimuta, I. Fujiwara","doi":"10.1109/IMW.2015.7150312","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150312","url":null,"abstract":"The paper shows clear evidence that in-situ transmission electron microscopy (TEM) can be used as a powerful tool to analyze ReRAM operation. Reproducible resistive switching of 100k cycles in 30- or 70-nm Cu-Te CBRAMs was achieved for the first time during in-situ TEM observation. A TEM sample of the CBRAM cells was processed by a focused ion beam method. The formation and rupture of a Cu filament was observed and analyzed in the TEM with energy dispersive x-ray (EDX) mapping. Since the overshoot current at the resistive switching was efficiently suppressed by a MOSFET placed in the TEM holder, stable and reproducible ReRAM switching operations were achieved in the TEM.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131205574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150294
T. Iwasaki, S. Ning, Hiroki Yamazawa, Chao Sun, S. Tanakamaru, K. Takeuchi
The variable behavior of ReRAM memory cells is modeled with machine learning. Two types of prediction are investigated, reset in the next-cycle and cell fail in the long term. A new proposal, Proactive Bit Redundancy, introduces a ML-trained Prediction Engine into the SSD controller, to predict fail cells and replace them proactively - before actual failure- by redundancy. With the Invalid Masking technique, predicted cells are marked in-place within the page, so that no extra address table is needed. Thus, with ninimal overhead, 2.85x bit error rate reduction or 13x endurance improvement is obtained based on a 50nm AlxOy testchip.
{"title":"Machine Learning Prediction for 13X Endurance Enhancement in ReRAM SSD System","authors":"T. Iwasaki, S. Ning, Hiroki Yamazawa, Chao Sun, S. Tanakamaru, K. Takeuchi","doi":"10.1109/IMW.2015.7150294","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150294","url":null,"abstract":"The variable behavior of ReRAM memory cells is modeled with machine learning. Two types of prediction are investigated, reset in the next-cycle and cell fail in the long term. A new proposal, Proactive Bit Redundancy, introduces a ML-trained Prediction Engine into the SSD controller, to predict fail cells and replace them proactively - before actual failure- by redundancy. With the Invalid Masking technique, predicted cells are marked in-place within the page, so that no extra address table is needed. Thus, with ninimal overhead, 2.85x bit error rate reduction or 13x endurance improvement is obtained based on a 50nm AlxOy testchip.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"1996 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128200808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150301
Patrick R. Khayat, M. Kaynak, S. Parthasarathy, Saeed Sharifi Tehrani
High bit error rates of next-generation flash devices necessitate the use of more powerful error correction codes (ECCs), such as low-density parity-check (LDPC) codes, instead of the legacy Bose-Chaudhuri-Hocquenghem (BCH) codes. Unlike algebraic codes, the random nature of LDPC codes as well as their ability to use soft information requires the use of Monte Carlo (MC) simulations to evaluate code performance. Given a large volume of NAND data, this can pose resource challenges both in terms of simulation platforms and time needed for the Monte Carlo simulations. In order to overcome these challenges, we introduce a new channel metric in this paper to quantify the quality of soft information and propose a practical LDPC code performance characterization methodology.
{"title":"Performance Characterization of LDPC Codes for Large-Volume NAND Flash Data","authors":"Patrick R. Khayat, M. Kaynak, S. Parthasarathy, Saeed Sharifi Tehrani","doi":"10.1109/IMW.2015.7150301","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150301","url":null,"abstract":"High bit error rates of next-generation flash devices necessitate the use of more powerful error correction codes (ECCs), such as low-density parity-check (LDPC) codes, instead of the legacy Bose-Chaudhuri-Hocquenghem (BCH) codes. Unlike algebraic codes, the random nature of LDPC codes as well as their ability to use soft information requires the use of Monte Carlo (MC) simulations to evaluate code performance. Given a large volume of NAND data, this can pose resource challenges both in terms of simulation platforms and time needed for the Monte Carlo simulations. In order to overcome these challenges, we introduce a new channel metric in this paper to quantify the quality of soft information and propose a practical LDPC code performance characterization methodology.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115714703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150296
L. Crespi, A. Lacaita, M. Boniardi, E. Varesi, A. Ghetti, A. Redaelli, G. D'Arrigo
Atomic migration on Phase Change Memory devices with wall architecture has been experimentally investigated and a quantitative model including electrical, thermal, and mechanical driving forces has been developed. The experimental results collected by driving the device with programming pulses with direct and reverse polarity have been accounted for. Comparison with data of atomic migration on heavily cycled cells is also provided.
{"title":"Modeling of Atomic Migration Phenomena in Phase Change Memory Devices","authors":"L. Crespi, A. Lacaita, M. Boniardi, E. Varesi, A. Ghetti, A. Redaelli, G. D'Arrigo","doi":"10.1109/IMW.2015.7150296","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150296","url":null,"abstract":"Atomic migration on Phase Change Memory devices with wall architecture has been experimentally investigated and a quantitative model including electrical, thermal, and mechanical driving forces has been developed. The experimental results collected by driving the device with programming pulses with direct and reverse polarity have been accounted for. Comparison with data of atomic migration on heavily cycled cells is also provided.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130130647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150299
J. Bartoli, V. Della Marca, J. Postel-Pellerin, J. Delalleau, A. Régnier, S. Niel, F. la Rosa, P. Canet, F. Lalande
The development of new wireless devices is growing up, driven by the market of connected things for many applications: communications, cloud and health. In this scenario the current consumption of memory devices plays a key role. To save the battery of these devices, we need to develop the components that consume less and less. In this paper we propose to improve the performances of an original architecture of nonvolatile memory cell: the Asymmetrical Tunnel Window (ATW) cell. We compare here the standard Flash floating gate memory cell with the new proposed device, with an accurate experimental investigation of programming window and energy consumption. Moreover we optimized the ATW cell architecture by modifying the ratio of oxides lengths and thicknesses. Finally, we experimentally demonstrate an improvement of 4 times on the programming efficiency with respect the standard memory.
{"title":"Optimization of the ATW Non-Volatile Memory for Connected Smart Objects","authors":"J. Bartoli, V. Della Marca, J. Postel-Pellerin, J. Delalleau, A. Régnier, S. Niel, F. la Rosa, P. Canet, F. Lalande","doi":"10.1109/IMW.2015.7150299","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150299","url":null,"abstract":"The development of new wireless devices is growing up, driven by the market of connected things for many applications: communications, cloud and health. In this scenario the current consumption of memory devices plays a key role. To save the battery of these devices, we need to develop the components that consume less and less. In this paper we propose to improve the performances of an original architecture of nonvolatile memory cell: the Asymmetrical Tunnel Window (ATW) cell. We compare here the standard Flash floating gate memory cell with the new proposed device, with an accurate experimental investigation of programming window and energy consumption. Moreover we optimized the ATW cell architecture by modifying the ratio of oxides lengths and thicknesses. Finally, we experimentally demonstrate an improvement of 4 times on the programming efficiency with respect the standard memory.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116553403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150271
W. Khwa, J. Y. Wu, T. Su, M. Lee, H. Li, Y. Chen, M. BrightSky, T. Wang, T. Hsu, P. Du, W. Chien, S. Kim, H. Cheng, E. Lai, Y. Zhu, M. Chang, H. Lung, C. Lam
Inherent cell variation of phase change memory is difficult to control by material or device engineering alone. We previously reported R-I curve shift detection scheme as a good method for monitoring PCM cell characteristics. This paper extends that concept and proposes a Stress-trim procedure to tighten R-I characteristics for PCM MLC operation. By leveraging the right-shift phenomena of PCM R-I curves, we demonstrated that Stress-trim can effectively reduce cell variation to improve MLC performance. A MLC program current amplitude range reduction of 40% and MLC time to failure extension of nearly 150X are achieved.
{"title":"A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multi-Level-Cell Performances","authors":"W. Khwa, J. Y. Wu, T. Su, M. Lee, H. Li, Y. Chen, M. BrightSky, T. Wang, T. Hsu, P. Du, W. Chien, S. Kim, H. Cheng, E. Lai, Y. Zhu, M. Chang, H. Lung, C. Lam","doi":"10.1109/IMW.2015.7150271","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150271","url":null,"abstract":"Inherent cell variation of phase change memory is difficult to control by material or device engineering alone. We previously reported R-I curve shift detection scheme as a good method for monitoring PCM cell characteristics. This paper extends that concept and proposes a Stress-trim procedure to tighten R-I characteristics for PCM MLC operation. By leveraging the right-shift phenomena of PCM R-I curves, we demonstrated that Stress-trim can effectively reduce cell variation to improve MLC performance. A MLC program current amplitude range reduction of 40% and MLC time to failure extension of nearly 150X are achieved.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126198692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150290
B. Ji, H. Li, Q. Ye, S. Gausepohl, S. Deora, D. Veksler, S. Vivekanand, H. Chong, H. Stamper, T. Burroughs, C. Johnson, M. Smalley, S. Bennett, V. Kaushik, J. Piccirillo, M. Rodgers, M. Passaro, M. Liehr
Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories.
{"title":"In-Line-Test of Variability and Bit-Error-Rate of HfOx-Based Resistive Memory","authors":"B. Ji, H. Li, Q. Ye, S. Gausepohl, S. Deora, D. Veksler, S. Vivekanand, H. Chong, H. Stamper, T. Burroughs, C. Johnson, M. Smalley, S. Bennett, V. Kaushik, J. Piccirillo, M. Rodgers, M. Passaro, M. Liehr","doi":"10.1109/IMW.2015.7150290","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150290","url":null,"abstract":"Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130627561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150285
A. Belmonte, A. Fantini, R. Degraeve, U. Celano, W. Vandervorst, A. Redolfi, M. Houssa, M. Jurczak, L. Goux
We demonstrate that CBRAM devices based on SiO2 dielectric can target sub-10μA application, ensuring large programming window, fast and low-voltage switching and limited cycle-to-cycle variability at 5 μA. We report, for the first time, reliable 1-μs forming operation at 5 μA on RRAM devices. The thorough comparison of SiO2- and Al2O3-based devices, in terms of electrical and physical characterization, suggests that the Cu mobility in the switching layers plays a key role, impacting forming/switching speed as well as functionality at low current, and that it can be tuned by properly selecting the switching layer material. We also correlate the mismatch in the electrical performances in the sub-10 μA regime to different filament configurations in the two resistive states.
{"title":"Fast and Stable Sub-10uA Pulse Operation in W/SiO2/Ta/Cu 90nm 1T1R CBRAM Devices","authors":"A. Belmonte, A. Fantini, R. Degraeve, U. Celano, W. Vandervorst, A. Redolfi, M. Houssa, M. Jurczak, L. Goux","doi":"10.1109/IMW.2015.7150285","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150285","url":null,"abstract":"We demonstrate that CBRAM devices based on SiO2 dielectric can target sub-10μA application, ensuring large programming window, fast and low-voltage switching and limited cycle-to-cycle variability at 5 μA. We report, for the first time, reliable 1-μs forming operation at 5 μA on RRAM devices. The thorough comparison of SiO2- and Al2O3-based devices, in terms of electrical and physical characterization, suggests that the Cu mobility in the switching layers plays a key role, impacting forming/switching speed as well as functionality at low current, and that it can be tuned by properly selecting the switching layer material. We also correlate the mismatch in the electrical performances in the sub-10 μA regime to different filament configurations in the two resistive states.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132300457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150309
B. Govoreanu, Leqi Zhang, D. Crotti, Yang‐Shun Fan, V. Paraschiv, H. Hody, T. Witters, J. Meersschaut, S. Clima, C. Adelmann, M. Jurczak
We report on a novel Thin-Silicon Injector (TSI) selector concept with bidirectional operation for high density resistive switching memory. Model-based analysis shows how the current drive-nonlinearity trade-off can be broken by properly combining physical material properties to enable decoupling control parameters of the current injection from those of selectivity. We demonstrate experimentally structures down to 40nm-size, featuring a high-drive current of ~1MA/cm2, high current-voltage half-bias nonlinearity exceeding 6.103 at maximum current drive and very good reliability of >107cy endurance, with limited degradation of the selectivity. The selector has below 20nm thickness and it is fully implementable with readily available BEOL CMOS-compatible materials and processes.
{"title":"Thin-Silicon Injector (TSI): An All-Silicon Engineered Barrier, Highly Nonlinear Selector for High Density Resistive RAM Applications","authors":"B. Govoreanu, Leqi Zhang, D. Crotti, Yang‐Shun Fan, V. Paraschiv, H. Hody, T. Witters, J. Meersschaut, S. Clima, C. Adelmann, M. Jurczak","doi":"10.1109/IMW.2015.7150309","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150309","url":null,"abstract":"We report on a novel Thin-Silicon Injector (TSI) selector concept with bidirectional operation for high density resistive switching memory. Model-based analysis shows how the current drive-nonlinearity trade-off can be broken by properly combining physical material properties to enable decoupling control parameters of the current injection from those of selectivity. We demonstrate experimentally structures down to 40nm-size, featuring a high-drive current of ~1MA/cm2, high current-voltage half-bias nonlinearity exceeding 6.103 at maximum current drive and very good reliability of >107cy endurance, with limited degradation of the selectivity. The selector has below 20nm thickness and it is fully implementable with readily available BEOL CMOS-compatible materials and processes.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115030497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150281
A. Schonhals, D. Wouters, A. Marchewka, T. Breuer, K. Skaja, V. Rana, S. Menzel, R. Waser
The thickness of the oxygen scavenging metal layer, forming the Ohmic contact in HfOx and TaOx VCM-type Metal-Oxide ReRAM cells, was found to be the critical experimental parameter controlling stable bipolar resistive switching versus the occurrence of single-cell complimentary switching. It is argued that the physically controlling parameter is the effective work function (a)symmetry between top and bottom electrode contact of the ReRAM cell. For a thin metal cap layer, oxidation increases the effective work function changing from Ohmic to a more blocking contact behavior.
{"title":"Critical ReRAM Stack Parameters Controlling Complimentary versus Bipolar Resistive Switching","authors":"A. Schonhals, D. Wouters, A. Marchewka, T. Breuer, K. Skaja, V. Rana, S. Menzel, R. Waser","doi":"10.1109/IMW.2015.7150281","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150281","url":null,"abstract":"The thickness of the oxygen scavenging metal layer, forming the Ohmic contact in HfOx and TaOx VCM-type Metal-Oxide ReRAM cells, was found to be the critical experimental parameter controlling stable bipolar resistive switching versus the occurrence of single-cell complimentary switching. It is argued that the physically controlling parameter is the effective work function (a)symmetry between top and bottom electrode contact of the ReRAM cell. For a thin metal cap layer, oxidation increases the effective work function changing from Ohmic to a more blocking contact behavior.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115429036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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