Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150272
J. Baek, Sang-Yun Kim, Jae-Koo Park, Jae-Young Park, K. Kwon
In this paper, a reliable cross-point MLC ReRAM is introduced and fully integrated with 350nm CMOS technology. Both resistance states and variations are widely investigated with different compliance current. The self-termination scheme is adopted to prevent overstress to switched cell in set operation. As a result of self termination, write failure is prohibited and the uniformity on LRS of 300 uA compliance improved 2.3 times. In order to deter the compliance current offset in set operation, a sneak current compensation scheme of which controlled by ADC is proposed.
{"title":"A Reliable Cross-Point MLC ReRAM with Sneak Current Compensation","authors":"J. Baek, Sang-Yun Kim, Jae-Koo Park, Jae-Young Park, K. Kwon","doi":"10.1109/IMW.2015.7150272","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150272","url":null,"abstract":"In this paper, a reliable cross-point MLC ReRAM is introduced and fully integrated with 350nm CMOS technology. Both resistance states and variations are widely investigated with different compliance current. The self-termination scheme is adopted to prevent overstress to switched cell in set operation. As a result of self termination, write failure is prohibited and the uniformity on LRS of 300 uA compliance improved 2.3 times. In order to deter the compliance current offset in set operation, a sneak current compensation scheme of which controlled by ADC is proposed.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150308
S. Fujita, H. Noguchi, K. Ikegami, S. Takeda, K. Nomura, K. Abe
This paper presents fast and low-power embedded nonvolatile memory technologies and circuit designs based on perpendicular STT-MRAM. Future prospects of applications are also discussed.
{"title":"Technology Trends and Near-Future Applications of Embedded STT-MRAM","authors":"S. Fujita, H. Noguchi, K. Ikegami, S. Takeda, K. Nomura, K. Abe","doi":"10.1109/IMW.2015.7150308","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150308","url":null,"abstract":"This paper presents fast and low-power embedded nonvolatile memory technologies and circuit designs based on perpendicular STT-MRAM. Future prospects of applications are also discussed.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114607914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150289
Kwang-il Choi, Nam-Yun Kim, Sung-Kun Park, I. Cho
In this paper, we describe a new single poly MTP (multiple time programmable) cell using contact plate and select gate coupling manufactured by 90 nm standard CMOS (complementary metal-oxide semiconductor) process. Proposed MTP cell size is smaller than conventional well coupled MTP cell and only select gate lateral coupling MTP cell in order to have the similar coupling ratio (CR) as the 1.98~3.26 μm2. The program erase operation use channel hot electron injection (CHEI) and band to band hot hole injection (BTBT-HHI). The cell performances are compared with splits group by coupling ratio (CR). Through the results represented by the experiments, we were able to achieve cell endurance of 100 cycle and 10 year retention lifetime at 150 °C, and realize operation margin with ease if coupling ratio is increased by adding plate contact. The describing cell using coupling of select gate and plate contact is thought to have more useful application due to technology shrink.
{"title":"Improved Lateral Coupling Cell for a Standard Logic Process eNVM Application","authors":"Kwang-il Choi, Nam-Yun Kim, Sung-Kun Park, I. Cho","doi":"10.1109/IMW.2015.7150289","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150289","url":null,"abstract":"In this paper, we describe a new single poly MTP (multiple time programmable) cell using contact plate and select gate coupling manufactured by 90 nm standard CMOS (complementary metal-oxide semiconductor) process. Proposed MTP cell size is smaller than conventional well coupled MTP cell and only select gate lateral coupling MTP cell in order to have the similar coupling ratio (CR) as the 1.98~3.26 μm2. The program erase operation use channel hot electron injection (CHEI) and band to band hot hole injection (BTBT-HHI). The cell performances are compared with splits group by coupling ratio (CR). Through the results represented by the experiments, we were able to achieve cell endurance of 100 cycle and 10 year retention lifetime at 150 °C, and realize operation margin with ease if coupling ratio is increased by adding plate contact. The describing cell using coupling of select gate and plate contact is thought to have more useful application due to technology shrink.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132788124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150310
William E. Akin
The use of NAND flash-based SSDs in enterprises has grown at a ~33% compound annual growth rate [1] worldwide for the past three years. The majority of the growth comes from enterprise data center applications where the trend is to leverage the cost benefits of using MLC and TLC NAND flash memory by focusing on the use model behavior to optimize performance and life characteristics. In the data center, requirements for these MLC/TLC SSDs demand high sequential performance and reliability, moderate IOPS, and low power consumption along with maintaining 3 to 5 years of useful life. These challenges are tackled by tightening the links between the SSD's operation, host operating environment, and intrinsic NAND memory behavior and by exploiting increasingly sophisticated controllers, firmware, and flash memory error management techniques.
{"title":"Understanding NAND’s Intrinsic Characteristics Critical Role in Solid State Drive (SSD) Design","authors":"William E. Akin","doi":"10.1109/IMW.2015.7150310","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150310","url":null,"abstract":"The use of NAND flash-based SSDs in enterprises has grown at a ~33% compound annual growth rate [1] worldwide for the past three years. The majority of the growth comes from enterprise data center applications where the trend is to leverage the cost benefits of using MLC and TLC NAND flash memory by focusing on the use model behavior to optimize performance and life characteristics. In the data center, requirements for these MLC/TLC SSDs demand high sequential performance and reliability, moderate IOPS, and low power consumption along with maintaining 3 to 5 years of useful life. These challenges are tackled by tightening the links between the SSD's operation, host operating environment, and intrinsic NAND memory behavior and by exploiting increasingly sophisticated controllers, firmware, and flash memory error management techniques.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133580534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150275
H. Saito, T. Sugimachi, Ko Nakamura, S. Ozawa, N. Sashida, S. Mihara, Y. Hikosaka, Wensheng Wang, Tomoyuki Hori, K. Takai, M. Nakazawa, N. Kosugi, M. Okuda, M. Hamada, S. Kawashima, T. Eshita, M. Matsumiya
We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.
{"title":"A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance","authors":"H. Saito, T. Sugimachi, Ko Nakamura, S. Ozawa, N. Sashida, S. Mihara, Y. Hikosaka, Wensheng Wang, Tomoyuki Hori, K. Takai, M. Nakazawa, N. Kosugi, M. Okuda, M. Hamada, S. Kawashima, T. Eshita, M. Matsumiya","doi":"10.1109/IMW.2015.7150275","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150275","url":null,"abstract":"We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150282
W. Kang, Tingting Pang, Youguang Zhang, D. Ravelosona, Weisheng Zhao
Spin transfer torque magnetic random access memory (STT-MRAM) has been considered as a potential candidate for the next-generation nonvolatile memory. However, as technology continuously scales down, the sensing margin (SM) of STT-MRAM is significantly degraded because of the increased process variations and reduced supply voltage. Meanwhile the critical switching current of magnetic tunnel junction (MTJ) also reduces with technology scaling. The sensing current, which should be limited to prevent read disturbance (RD) during read operations, further degrades the SM. Therefore, the readability becomes a new challenge for the deeply scaled STT-MRAM. To alleviate this problem, various sensing circuits and schemes have recently been proposed. However, it is rather difficult to achieve a good tradeoff among the sensing reliability, latency, power and hardware efficiency etc. This paper presents a dynamic reference cell (DRC) as well as a dynamic reference sensing (DRS) scheme to deal with this problem. Monte-Carlo statistical simulations have been performed to show the superiority of the proposed DRS scheme compared with conventional sensing schemes.
{"title":"Dynamic Reference Sensing Scheme for Deeply Scaled STT-MRAM","authors":"W. Kang, Tingting Pang, Youguang Zhang, D. Ravelosona, Weisheng Zhao","doi":"10.1109/IMW.2015.7150282","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150282","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) has been considered as a potential candidate for the next-generation nonvolatile memory. However, as technology continuously scales down, the sensing margin (SM) of STT-MRAM is significantly degraded because of the increased process variations and reduced supply voltage. Meanwhile the critical switching current of magnetic tunnel junction (MTJ) also reduces with technology scaling. The sensing current, which should be limited to prevent read disturbance (RD) during read operations, further degrades the SM. Therefore, the readability becomes a new challenge for the deeply scaled STT-MRAM. To alleviate this problem, various sensing circuits and schemes have recently been proposed. However, it is rather difficult to achieve a good tradeoff among the sensing reliability, latency, power and hardware efficiency etc. This paper presents a dynamic reference cell (DRC) as well as a dynamic reference sensing (DRS) scheme to deal with this problem. Monte-Carlo statistical simulations have been performed to show the superiority of the proposed DRS scheme compared with conventional sensing schemes.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150298
L. Breuil, J. Lisoni, P. Blomme, G. Van den bosch, J. van Houdt
The required transition from Control Gate wrap-around to planar structure for NAND flash scaling below 20nm node causes important loss of coupling factor. In order to recover the Programming window, we develop a Hybrid Floating Gate using Ru as high work-function metal. With a proper nitridation of the underlying Si and ALD technique, we obtain a continuous Ru layer as thin as 2nm that is thermally stable in contact with Si. Thanks to the higher work function of Ru, a programming window of more than 10V has been be achieved.
{"title":"Optimization of Ru Based Hybrid Floating Gate for Planar NAND Flash","authors":"L. Breuil, J. Lisoni, P. Blomme, G. Van den bosch, J. van Houdt","doi":"10.1109/IMW.2015.7150298","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150298","url":null,"abstract":"The required transition from Control Gate wrap-around to planar structure for NAND flash scaling below 20nm node causes important loss of coupling factor. In order to recover the Programming window, we develop a Hybrid Floating Gate using Ru as high work-function metal. With a proper nitridation of the underlying Si and ALD technique, we obtain a continuous Ru layer as thin as 2nm that is thermally stable in contact with Si. Thanks to the higher work function of Ru, a programming window of more than 10V has been be achieved.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150283
Hao Wang, Kai Zhao, Tong Zhang
DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell-induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10-4 ~ 10-3 at very small (even negligible) latency overhead.
{"title":"Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes","authors":"Hao Wang, Kai Zhao, Tong Zhang","doi":"10.1109/IMW.2015.7150283","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150283","url":null,"abstract":"DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell-induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10-4 ~ 10-3 at very small (even negligible) latency overhead.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130793891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150297
Yanjun Ma
We discuss non-volatile SRAM cells capable of storing multiple bits and their applications as multi-context configuration memory. The cells are based on the standard 6T SRAM with multiple pairs of programmable resistors such as magnetic tunnel junction or resistive memory elements. In one of the cell designs the active state of the SRAM can be switched in one clock cycle by the use of an additional equalizer transistor, without the need to turn off the power to the cell, allowing real-time and low energy switching between different contexts in reconfigurable circuits. Other variations of the multistate non-volatile SRAM cells are also discussed.
{"title":"Novel Multi-Bit Non-Volatile SRAM Cells for Runtime Reconfigurable Computing","authors":"Yanjun Ma","doi":"10.1109/IMW.2015.7150297","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150297","url":null,"abstract":"We discuss non-volatile SRAM cells capable of storing multiple bits and their applications as multi-context configuration memory. The cells are based on the standard 6T SRAM with multiple pairs of programmable resistors such as magnetic tunnel junction or resistive memory elements. In one of the cell designs the active state of the SRAM can be switched in one clock cycle by the use of an additional equalizer transistor, without the need to turn off the power to the cell, allowing real-time and low energy switching between different contexts in reconfigurable circuits. Other variations of the multistate non-volatile SRAM cells are also discussed.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122205658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150300
Xueyao Huang, Huaqiang Wu, D. Sekar, S. Nguyen, Kun Wang, H. Qian
Recently, we demonstrated a TiN/TaOx/HfO2/TiN RRAM [1]. The Conductive Metal Oxide (TaOx) acted as an in-built current compliance layer and improved thermal efficiency too, leading to high-quality RRAM characteristics [1]. In this work, we report excellent resistance uniformity and endurance for these TiN/TaOx/HfO2/TiN RRAMs and present techniques to optimize switching and data retention. An oxygen anneal after HfO2 atomic layer deposition is shown to improve data retention quite significantly for 1kb arrays, while not having a deleterious effect on switching. Experiments on different HfO2 thicknesses indicate that an optimal thickness exists which gives a good tradeoff between FORM voltage and data retention.
{"title":"Optimization of TiN/TaOx/HfO2/TiN RRAM Arrays for Improved Switching and Data Retention","authors":"Xueyao Huang, Huaqiang Wu, D. Sekar, S. Nguyen, Kun Wang, H. Qian","doi":"10.1109/IMW.2015.7150300","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150300","url":null,"abstract":"Recently, we demonstrated a TiN/TaOx/HfO2/TiN RRAM [1]. The Conductive Metal Oxide (TaOx) acted as an in-built current compliance layer and improved thermal efficiency too, leading to high-quality RRAM characteristics [1]. In this work, we report excellent resistance uniformity and endurance for these TiN/TaOx/HfO2/TiN RRAMs and present techniques to optimize switching and data retention. An oxygen anneal after HfO2 atomic layer deposition is shown to improve data retention quite significantly for 1kb arrays, while not having a deleterious effect on switching. Experiments on different HfO2 thicknesses indicate that an optimal thickness exists which gives a good tradeoff between FORM voltage and data retention.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124081163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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