Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712678
M. Kundu, M. Chowdhury
In this article, we have proposed an interactive image retrieval scheme using MPEG-7 visual features, Neural Network (NN)-based pre-classifier and fuzzy based feature evaluation scheme. The performance of the existing image retrieval systems is generally limited due to semantic gap, resulted due to the discrepancies between the computed low-level features and user's conception of an image. Partitioning the database by a NN-based pre-classifier, and using a fuzzy based feature evaluation scheme, the performance of the proposed scheme has been found to improved drastically by reducing the retrieval time and increasing the accuracy.
{"title":"Image retrieval using NN based pre-classification and fuzzy relevance feedback","authors":"M. Kundu, M. Chowdhury","doi":"10.1109/INDCON.2010.5712678","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712678","url":null,"abstract":"In this article, we have proposed an interactive image retrieval scheme using MPEG-7 visual features, Neural Network (NN)-based pre-classifier and fuzzy based feature evaluation scheme. The performance of the existing image retrieval systems is generally limited due to semantic gap, resulted due to the discrepancies between the computed low-level features and user's conception of an image. Partitioning the database by a NN-based pre-classifier, and using a fuzzy based feature evaluation scheme, the performance of the proposed scheme has been found to improved drastically by reducing the retrieval time and increasing the accuracy.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126156516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712749
U. Mehta, K. Dasgupta, N. Devashrayee, Kushal Choksi
Scan chain design is a popular design-for-test technique for testing of sequential circuits. Significant amount of power is consumed during loading and unloading of scan chains due to weighted transitions. As the power consumption in the test mode is quite high compared to normal circuit operation, the test power has become the prime concern for current research. Scan chain reordering is widely used method to reduce test power. In this paper, a Hamming distance based distributed reordering for loading and unloading scan chain vector is proposed. This method focuses on how and where weighted transitions occur. In current scenario of VLSI the manufacturing cost and area of transistor is no longer a big issue for current VLSI world. In this context, the proposed method shows promising results in reduction of test power at a cost of area. The experimental results for widely sited ISCAS'89 benchmark circuits are presented to show the effectiveness of the proposed scheme.
{"title":"Hamming distance based distributed scan chain reordering for test power optimization","authors":"U. Mehta, K. Dasgupta, N. Devashrayee, Kushal Choksi","doi":"10.1109/INDCON.2010.5712749","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712749","url":null,"abstract":"Scan chain design is a popular design-for-test technique for testing of sequential circuits. Significant amount of power is consumed during loading and unloading of scan chains due to weighted transitions. As the power consumption in the test mode is quite high compared to normal circuit operation, the test power has become the prime concern for current research. Scan chain reordering is widely used method to reduce test power. In this paper, a Hamming distance based distributed reordering for loading and unloading scan chain vector is proposed. This method focuses on how and where weighted transitions occur. In current scenario of VLSI the manufacturing cost and area of transistor is no longer a big issue for current VLSI world. In this context, the proposed method shows promising results in reduction of test power at a cost of area. The experimental results for widely sited ISCAS'89 benchmark circuits are presented to show the effectiveness of the proposed scheme.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132843217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712646
I. Hatai, I. Chakrabarti
A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of 1.5×10−4. The FPGA implementation of the proposed design has an SFDR of −94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion.
{"title":"A novel low-latency, high-speed DDFS architecture","authors":"I. Hatai, I. Chakrabarti","doi":"10.1109/INDCON.2010.5712646","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712646","url":null,"abstract":"A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of 1.5×10−4. The FPGA implementation of the proposed design has an SFDR of −94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124062114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712654
J. Mukherjee, S. Ghosh
Geospatial data has been playing a central role in various decision support systems. Geographic Information system (GIS) captures, stores, manages and analyses and represents those data, there by contributes in extraction of geospatial information from data. Advancements in technology have allowed consuming GIS functionalities as services over the web. Integrating distributed services in terms of service chaining is required for resolving user requirements which needs involvements of more then one services. However, chaining distributed services comes with several heterogeneity issues as syntactic, semantic heterogeneity. Here, in this paper a service chaining approach for decision making systems have been proposed. Semantic heterogeneity among services has been taken care using ontology. A case study has been discussed to show the efficacy of the proposed approach.
{"title":"Geospatial service chaining in decision support systems","authors":"J. Mukherjee, S. Ghosh","doi":"10.1109/INDCON.2010.5712654","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712654","url":null,"abstract":"Geospatial data has been playing a central role in various decision support systems. Geographic Information system (GIS) captures, stores, manages and analyses and represents those data, there by contributes in extraction of geospatial information from data. Advancements in technology have allowed consuming GIS functionalities as services over the web. Integrating distributed services in terms of service chaining is required for resolving user requirements which needs involvements of more then one services. However, chaining distributed services comes with several heterogeneity issues as syntactic, semantic heterogeneity. Here, in this paper a service chaining approach for decision making systems have been proposed. Semantic heterogeneity among services has been taken care using ontology. A case study has been discussed to show the efficacy of the proposed approach.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121080411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712726
Sayanti Chatterjee, S. Sadhu, T. K. Ghosal
This contribution reports the design of state estimator for a nonlinear process using the recently proposed contraction analysis approach. Although the contraction based stability analysis for nonlinear systems is now an accepted tool for analyzing control systems with uncertain parameters, application of this technique for designing nonlinear state estimator is fairly recent and still evolving. The contraction analysis based estimator design method is briefly outlined before applying the method for a biochemical process, for which existing literature indicates the use of traditional nonlinear observers. A comparative study of estimator performance between an extended Luenberger observer based state estimation and the contraction observer has been reported. Results of simulation show that state estimation using contraction observer is better than that of the classical one.
{"title":"Contraction theory based observer for a biochemical process","authors":"Sayanti Chatterjee, S. Sadhu, T. K. Ghosal","doi":"10.1109/INDCON.2010.5712726","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712726","url":null,"abstract":"This contribution reports the design of state estimator for a nonlinear process using the recently proposed contraction analysis approach. Although the contraction based stability analysis for nonlinear systems is now an accepted tool for analyzing control systems with uncertain parameters, application of this technique for designing nonlinear state estimator is fairly recent and still evolving. The contraction analysis based estimator design method is briefly outlined before applying the method for a biochemical process, for which existing literature indicates the use of traditional nonlinear observers. A comparative study of estimator performance between an extended Luenberger observer based state estimation and the contraction observer has been reported. Results of simulation show that state estimation using contraction observer is better than that of the classical one.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121283597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712671
K. Roy, D. Chatterjee, A. K. Ganguli
Wound-rotor induction motor drive fed from inverters on both the stator and rotor side is discussed. The sensorless control scheme for the motor requires a V/f-type direct frequency control preferably on the rotor side, with either vector control or direct torque control on the stator side. Selection of any frequency for the rotor side inverter keeping the rotor flux constant is possible. This rotor frequency will decide the selection of the stator side frequency. In this paper, a study on core loss at different rotor injected frequencies is carried out at different loads. Also to operate the motor at an optimum efficiency during any loading condition, a method for correct selection of stator and rotor frequency is studied. It is also shown that core losses constitute a considerable amount of the total losses and hence should not be neglected for the sake of efficiency. Experimental results on a real machine are presented in support of the proposed concept.
{"title":"Modeling and estimation of core losses for doubly-fed wound rotor induction machine","authors":"K. Roy, D. Chatterjee, A. K. Ganguli","doi":"10.1109/INDCON.2010.5712671","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712671","url":null,"abstract":"Wound-rotor induction motor drive fed from inverters on both the stator and rotor side is discussed. The sensorless control scheme for the motor requires a V/f-type direct frequency control preferably on the rotor side, with either vector control or direct torque control on the stator side. Selection of any frequency for the rotor side inverter keeping the rotor flux constant is possible. This rotor frequency will decide the selection of the stator side frequency. In this paper, a study on core loss at different rotor injected frequencies is carried out at different loads. Also to operate the motor at an optimum efficiency during any loading condition, a method for correct selection of stator and rotor frequency is studied. It is also shown that core losses constitute a considerable amount of the total losses and hence should not be neglected for the sake of efficiency. Experimental results on a real machine are presented in support of the proposed concept.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128965829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712595
Aditya Tiwari, Hiranmay Ghosh
In this paper, a framework for recognition of Bangla ticker text1 from the Bangla news videos is presented. Tesseract OCR [1] has been used for Bangla script recognition. Tesseract OCR gives good results for text recognition in documents. But in case of images and videos, some processing is required beforehand. Approach here is to provide processed images to the Tesseract OCR to get better results than directly providing the raw video frames to the Tesseract OCR. The ticker text recognized can further be used for indexing of news videos on the basis of recognized keywords. Indexing of news videos is important for news monitoring agencies. Till now this is done manually. Automation of the monitoring process and indexing the news videos can save a lot of time as well as the efficiency of the news monitoring system.
{"title":"Ticker text extraction from Bangla news videos","authors":"Aditya Tiwari, Hiranmay Ghosh","doi":"10.1109/INDCON.2010.5712595","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712595","url":null,"abstract":"In this paper, a framework for recognition of Bangla ticker text1 from the Bangla news videos is presented. Tesseract OCR [1] has been used for Bangla script recognition. Tesseract OCR gives good results for text recognition in documents. But in case of images and videos, some processing is required beforehand. Approach here is to provide processed images to the Tesseract OCR to get better results than directly providing the raw video frames to the Tesseract OCR. The ticker text recognized can further be used for indexing of news videos on the basis of recognized keywords. Indexing of news videos is important for news monitoring agencies. Till now this is done manually. Automation of the monitoring process and indexing the news videos can save a lot of time as well as the efficiency of the news monitoring system.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712699
P. Jha, V. Sahula
Various unavoidable constraints (viz. physical, technical and financial) curtail the possibility of achieving continuous improvement in the computing capabilities through scaling down of devices using the conventional silicon technology. Molecular electronics aims to use the bottom-up approach to build nanoscale devices from basic molecular unit and promises unforeseen levels of computing per dollar-watt-cm2. The programmability feature of molecules is exploited to circumvent the problem of addressability. The nanocell concept is predicated on the belief that a random distribution of self-assembled molecules can be programmed to perform a specific logic function. In this paper we present a novel approach to demonstrate plausibility of the idea of “creating functionality from disorder”. The experimental results vindicate the plausibility of training a nanocell to perform a logic operation. A negative differential resistance (NDR) circuit has been designed to emulate the Λ-type I-V characteristics of the molecular switches connected between any pair of nodes in the actual nanocell. A nanocell model is then constructed taking instances of this NDR circuit. As a primary exploration of the nanocell concept the omnipotent programming was considered. The results from HSPICE simulations are then fed to the genetic algorithm(GA) solver in MATLAB to provide us with the optimized configuration(or a combination of switch states) of the NDR circuits for which the nanocell model yields the functionality of one or multiple target logic devices. Finally mortal programming is also accomplished. The GA solver is used again to provide us with the voltages which ought to be applied on each of the exterior nodes (apart from the input and output nodes) of the nanocell to yield a response resembling a NAND gate.
{"title":"Omnipotent and mortal training of a nanocell model to emulate the functionality of a logic gate","authors":"P. Jha, V. Sahula","doi":"10.1109/INDCON.2010.5712699","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712699","url":null,"abstract":"Various unavoidable constraints (viz. physical, technical and financial) curtail the possibility of achieving continuous improvement in the computing capabilities through scaling down of devices using the conventional silicon technology. Molecular electronics aims to use the bottom-up approach to build nanoscale devices from basic molecular unit and promises unforeseen levels of computing per dollar-watt-cm2. The programmability feature of molecules is exploited to circumvent the problem of addressability. The nanocell concept is predicated on the belief that a random distribution of self-assembled molecules can be programmed to perform a specific logic function. In this paper we present a novel approach to demonstrate plausibility of the idea of “creating functionality from disorder”. The experimental results vindicate the plausibility of training a nanocell to perform a logic operation. A negative differential resistance (NDR) circuit has been designed to emulate the Λ-type I-V characteristics of the molecular switches connected between any pair of nodes in the actual nanocell. A nanocell model is then constructed taking instances of this NDR circuit. As a primary exploration of the nanocell concept the omnipotent programming was considered. The results from HSPICE simulations are then fed to the genetic algorithm(GA) solver in MATLAB to provide us with the optimized configuration(or a combination of switch states) of the NDR circuits for which the nanocell model yields the functionality of one or multiple target logic devices. Finally mortal programming is also accomplished. The GA solver is used again to provide us with the voltages which ought to be applied on each of the exterior nodes (apart from the input and output nodes) of the nanocell to yield a response resembling a NAND gate.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122637358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712592
A. Basu, T. S. Das, S. Sarkar, Abhik Roy, N. Islam
The current explosion of digital media creates threats towards the security in multimedia data broadcasting. Watermarking technique becomes a prospective solution to this coercion by means of Intellectual Property Right Protection, Authentication and Integrity Verification of digital media. In this paper we introduce an approach that enables us to develop a low power, real time, reliable and secure data hiding system. As an effort towards the power efficient system, here we present an oblivious, spatial domain watermarking based authentication algorithm and its FPGA implementation. The low cost data embedding algorithm can hide watermark into original cover image coming from a sensor much faster than software implementation and the embedded image is easily transmitted to PC by using appropriate interface.
{"title":"FPGA prototype of visual information hiding","authors":"A. Basu, T. S. Das, S. Sarkar, Abhik Roy, N. Islam","doi":"10.1109/INDCON.2010.5712592","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712592","url":null,"abstract":"The current explosion of digital media creates threats towards the security in multimedia data broadcasting. Watermarking technique becomes a prospective solution to this coercion by means of Intellectual Property Right Protection, Authentication and Integrity Verification of digital media. In this paper we introduce an approach that enables us to develop a low power, real time, reliable and secure data hiding system. As an effort towards the power efficient system, here we present an oblivious, spatial domain watermarking based authentication algorithm and its FPGA implementation. The low cost data embedding algorithm can hide watermark into original cover image coming from a sensor much faster than software implementation and the embedded image is easily transmitted to PC by using appropriate interface.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124763950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/INDCON.2010.5712685
N. Choudhury, S. Goswami
Allocating losses due to transmission in deregulated power market has become an important issue due to the changed operating mode of restructured power system. The difficulty with the job of loss allocation to the participating players lies in the fact that transmission losses have mutual couplings thus having no acceptable engineering solutions. Game theoretic approach might be an acceptable approach as they are developed based on the satisfaction of the individual players. Applying game theoretic approach on the other hand, as an independent solution tool is also difficult as it needs handling of huge data to solve a single case. A combination of the game theory and neural network thus is proposed here as an alternative solution.
{"title":"Transmission loss allocation using Bayesian regularization backpropagation ANN","authors":"N. Choudhury, S. Goswami","doi":"10.1109/INDCON.2010.5712685","DOIUrl":"https://doi.org/10.1109/INDCON.2010.5712685","url":null,"abstract":"Allocating losses due to transmission in deregulated power market has become an important issue due to the changed operating mode of restructured power system. The difficulty with the job of loss allocation to the participating players lies in the fact that transmission losses have mutual couplings thus having no acceptable engineering solutions. Game theoretic approach might be an acceptable approach as they are developed based on the satisfaction of the individual players. Applying game theoretic approach on the other hand, as an independent solution tool is also difficult as it needs handling of huge data to solve a single case. A combination of the game theory and neural network thus is proposed here as an alternative solution.","PeriodicalId":109071,"journal":{"name":"2010 Annual IEEE India Conference (INDICON)","volume":"510 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122215355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：