In this paper, we have improved dynamic IRdrop performance in large SoC design through various dynamic IRdrop reduction technique. Robust power/ground rail structure is proposed and applied to standard cell power/ground pin connection. Manual adding extra power switch cell is applied to fix localized IRdrop hot-spot. For memory macro, sharing power/ground metal scheme is shown significant improvement memory IRdrop performance. Those techniques are fully adopted in our FinFET based SoC implementation stage. As a result makes it easier to sign-off full-chip IRdrop compared to traditional physical design methodology.
{"title":"Improving of Dynamic IRdrop Performance in FinFET SoC Design","authors":"Changseok Choi, Minji Lee, Sungjun Lim, Kieyong Park, Hosoon Shin, Yongseok Kang, Woohyun Paik","doi":"10.1109/ISOCC47750.2019.9078510","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078510","url":null,"abstract":"In this paper, we have improved dynamic IRdrop performance in large SoC design through various dynamic IRdrop reduction technique. Robust power/ground rail structure is proposed and applied to standard cell power/ground pin connection. Manual adding extra power switch cell is applied to fix localized IRdrop hot-spot. For memory macro, sharing power/ground metal scheme is shown significant improvement memory IRdrop performance. Those techniques are fully adopted in our FinFET based SoC implementation stage. As a result makes it easier to sign-off full-chip IRdrop compared to traditional physical design methodology.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"49 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123462951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078502
M. R. Rehman, Imran Ali, Pervesh Kumar, Sungjin Kim, Kangyoon Lee
This paper presents a real time high accuracy phase difference measurement method for parallel multi-channel sensors. The parallel data acquisition from multiple sensors is commonly used in Sonar based systems to increase distance measurement accuracy and reliability. Due to the mismatch in the analog path and PVT variations, the sensor signal experience delay among multiple channels. It causes phase difference which need to be consider for precise distance measurement. A LabVIEW based real time phase difference measurement method is proposed by using NI PXIe-6555 high speed digital I/O (HSDIO). The serial digital data from sensor’s ADC is converted into parallel in FPGA and then multiplexed with channel ID. The NI PXIe-6555 reads parallel multiplexed data from FPGA and calculate phase difference among multiple channels in LabVIEW with six digit fractional precision. A real time phase difference measurement of two parallel channel ADC chip for SONAR application is also performed while considering channel mismatch and PVT variations.
{"title":"Real time High Accuracy Phase Difference Measurement for Parallel Multi-Channel Sensors","authors":"M. R. Rehman, Imran Ali, Pervesh Kumar, Sungjin Kim, Kangyoon Lee","doi":"10.1109/ISOCC47750.2019.9078502","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078502","url":null,"abstract":"This paper presents a real time high accuracy phase difference measurement method for parallel multi-channel sensors. The parallel data acquisition from multiple sensors is commonly used in Sonar based systems to increase distance measurement accuracy and reliability. Due to the mismatch in the analog path and PVT variations, the sensor signal experience delay among multiple channels. It causes phase difference which need to be consider for precise distance measurement. A LabVIEW based real time phase difference measurement method is proposed by using NI PXIe-6555 high speed digital I/O (HSDIO). The serial digital data from sensor’s ADC is converted into parallel in FPGA and then multiplexed with channel ID. The NI PXIe-6555 reads parallel multiplexed data from FPGA and calculate phase difference among multiple channels in LabVIEW with six digit fractional precision. A real time phase difference measurement of two parallel channel ADC chip for SONAR application is also performed while considering channel mismatch and PVT variations.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078536
Heejae Hwang, Jongsun Kim
A low-power 20 Gbps multi-phase multiplying delaylocked loop (MDLL)-based clock and data recovery (CDR) with receiver equalization is presented. The proposed MDLL-based digital CDR uses 2x-oversampling technique to lower the bit error rate (BER) and achieves fast lock time using an initial tracking mode. A multi-phase MDLL is utilized to provide the 8- phase reference clocks needed for the PI-based CDR, thereby achieving the power reduction effect. A near-ground signaling (NGS) receiver with a passive CTLE is used for lower power operation at 20 Gbps/channel. The proposed 20 Gbps CDR with receiver equalization is implemented in a 40nm CMOS process, achieving a power consumption of only 25.0 mW (=1.25 mW/Gb/s).
{"title":"A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization","authors":"Heejae Hwang, Jongsun Kim","doi":"10.1109/ISOCC47750.2019.9078536","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078536","url":null,"abstract":"A low-power 20 Gbps multi-phase multiplying delaylocked loop (MDLL)-based clock and data recovery (CDR) with receiver equalization is presented. The proposed MDLL-based digital CDR uses 2x-oversampling technique to lower the bit error rate (BER) and achieves fast lock time using an initial tracking mode. A multi-phase MDLL is utilized to provide the 8- phase reference clocks needed for the PI-based CDR, thereby achieving the power reduction effect. A near-ground signaling (NGS) receiver with a passive CTLE is used for lower power operation at 20 Gbps/channel. The proposed 20 Gbps CDR with receiver equalization is implemented in a 40nm CMOS process, achieving a power consumption of only 25.0 mW (=1.25 mW/Gb/s).","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An IoT system has been built to observe and analyze shrimp and feed conditions under turbid underwater environment in typical shrimp farms. The system streams underwater videos and water quality sensor data to a cloud server where the videos are automatically enhanced and analyzed, based on AI related techniques, to identify important objects such as shrimps and feeds. To support the scalability of our system, edge devices are currently under development to perform real time video enhancement and object detection at the farm site such that only processed information are sent back to the cloud in order to reduce the burdens of the network bandwidth and the computing/storage of the cloud servers.
{"title":"AIoTs for Smart Shrimp Farming","authors":"Ing-Jer Huang, Shiann-Rong Kuang, Yun-Nan Chang, Chin-Chang Hung, Chang-Ru Tsai, Kai-Lin Feng","doi":"10.1109/ISOCC47750.2019.9078467","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078467","url":null,"abstract":"An IoT system has been built to observe and analyze shrimp and feed conditions under turbid underwater environment in typical shrimp farms. The system streams underwater videos and water quality sensor data to a cloud server where the videos are automatically enhanced and analyzed, based on AI related techniques, to identify important objects such as shrimps and feeds. To support the scalability of our system, edge devices are currently under development to perform real time video enhancement and object detection at the farm site such that only processed information are sent back to the cloud in order to reduce the burdens of the network bandwidth and the computing/storage of the cloud servers.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124486364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078464
Daisuke Ito, Tomotaka Tanaka, Makoto Nakamura, K. Kishine
A new voltage controlled oscillator (VCO) design based on a ring oscillator with a double-short-path loop architecture is presented. The proposed circuit employs the Gilbert cell as a delay component and two short paths in order to expand the oscillation frequency tuning range. We designed and fabricated the six-stage ring VCO with double-short-path architecture in 0.18-μm CMOS technology. It has about 150 % wider tuning range than the conventional one and can oscillate from 0.36 to 1.2 GHz.
{"title":"A wideband differential VCO based on double-short-path loop architecture","authors":"Daisuke Ito, Tomotaka Tanaka, Makoto Nakamura, K. Kishine","doi":"10.1109/ISOCC47750.2019.9078464","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078464","url":null,"abstract":"A new voltage controlled oscillator (VCO) design based on a ring oscillator with a double-short-path loop architecture is presented. The proposed circuit employs the Gilbert cell as a delay component and two short paths in order to expand the oscillation frequency tuning range. We designed and fabricated the six-stage ring VCO with double-short-path architecture in 0.18-μm CMOS technology. It has about 150 % wider tuning range than the conventional one and can oscillate from 0.36 to 1.2 GHz.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121420944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078535
Xiang Gao
A PLL usually consists of a voltage controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with: a phase detector (PD), a charge pump (CP), a loop filter (LF) and a frequency divider with ratio N (÷N). Every component will add noise and power to the PLL. In an ideal case, the PLL jitter and power should be mostly determined by the VCO and Ref, while the other components like PD, CP, LF and divider adds negligible noise and consumes negligible power. This paper describes this "PLL Utopia" and discusses how it can be achieved through PLL architecture and circuit design innovations.
{"title":"Low Jitter and Low Power PLL：Towards The Utopia","authors":"Xiang Gao","doi":"10.1109/ISOCC47750.2019.9078535","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078535","url":null,"abstract":"A PLL usually consists of a voltage controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with: a phase detector (PD), a charge pump (CP), a loop filter (LF) and a frequency divider with ratio N (÷N). Every component will add noise and power to the PLL. In an ideal case, the PLL jitter and power should be mostly determined by the VCO and Ref, while the other components like PD, CP, LF and divider adds negligible noise and consumes negligible power. This paper describes this \"PLL Utopia\" and discusses how it can be achieved through PLL architecture and circuit design innovations.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124284318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078496
Min-Hsing Cheng, Hyunyul Lim, Tae Hyun Kim, Sungho Kang
Three dimensional integrated circuits (3D ICs) have been proposed as a solution for the limitation of microfabrication technology. However, through-silicon via (TSV), which connects two different dies vertically, may fail, and it can decrease the yield of 3D-ICs. A novel TSV repair architecture to repair defect TSVs is proposed in this paper. By shifting the corresponding signals of the faulty TSVs vertically and diagonally to the non-faulty TSVs, the proposed method maintains repair rate of TSV to 88.6% when there are 8 faulty TSVs. The hardware area of MUXs in proposed method is 193.6μm² while that of the previous work is 245.8spl mu/m² and 297.9 spl mu/m².
{"title":"A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology","authors":"Min-Hsing Cheng, Hyunyul Lim, Tae Hyun Kim, Sungho Kang","doi":"10.1109/ISOCC47750.2019.9078496","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078496","url":null,"abstract":"Three dimensional integrated circuits (3D ICs) have been proposed as a solution for the limitation of microfabrication technology. However, through-silicon via (TSV), which connects two different dies vertically, may fail, and it can decrease the yield of 3D-ICs. A novel TSV repair architecture to repair defect TSVs is proposed in this paper. By shifting the corresponding signals of the faulty TSVs vertically and diagonally to the non-faulty TSVs, the proposed method maintains repair rate of TSV to 88.6% when there are 8 faulty TSVs. The hardware area of MUXs in proposed method is 193.6μm² while that of the previous work is 245.8spl mu/m² and 297.9 spl mu/m².","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078490
Imran Ali, Muhammad Asif, Y. Qaragoez, M. R. Rehman, Kangyoon Lee
In this paper, an adaptive power amplifier (PA) modulation index controller with temperature compensation is presented for 5.8 GHz dedicated short-range communication (DSRC) transceiver applications. The number of Class-E type PA cores are configurable for amplitude shift keying (ASK) modulation and correction factor due to temperature variation is compensated adaptively in automatic mode to keep constant PA output power. In external mode, the modulation index and correction factor are configurable for the suitable number of core selection for higher PA output power. The design consumes 17.29 nW power and draws 14.41 nA current from 1.2 V supply. The proposed design is fully synthesizable and it needs only 854 gates for its implementation in 130 nm CMOS process with 64 × 153 μm² of area.
{"title":"An Adaptive PA Modulation Index Controller with Temperature Compensation for DSRC Applications","authors":"Imran Ali, Muhammad Asif, Y. Qaragoez, M. R. Rehman, Kangyoon Lee","doi":"10.1109/ISOCC47750.2019.9078490","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078490","url":null,"abstract":"In this paper, an adaptive power amplifier (PA) modulation index controller with temperature compensation is presented for 5.8 GHz dedicated short-range communication (DSRC) transceiver applications. The number of Class-E type PA cores are configurable for amplitude shift keying (ASK) modulation and correction factor due to temperature variation is compensated adaptively in automatic mode to keep constant PA output power. In external mode, the modulation index and correction factor are configurable for the suitable number of core selection for higher PA output power. The design consumes 17.29 nW power and draws 14.41 nA current from 1.2 V supply. The proposed design is fully synthesizable and it needs only 854 gates for its implementation in 130 nm CMOS process with 64 × 153 μm² of area.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128921846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078521
Kaname Shimada, Takuma Hikida, Hiroki Nishikawa, Ittetsu Taniguchi, H. Tomiyama
This paper studies scheduling of malleable tasks on multicore architectures. The proposed technique decides the number of cores for each task at the same time as task scheduling. DMA-based inter-task communication is also taken into account during task scheduling.
{"title":"Scheduling of Malleable Tasks with DMA-based Communication","authors":"Kaname Shimada, Takuma Hikida, Hiroki Nishikawa, Ittetsu Taniguchi, H. Tomiyama","doi":"10.1109/ISOCC47750.2019.9078521","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078521","url":null,"abstract":"This paper studies scheduling of malleable tasks on multicore architectures. The proposed technique decides the number of cores for each task at the same time as task scheduling. DMA-based inter-task communication is also taken into account during task scheduling.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging Non-volatile memory (NVM) has demonstrated superior performance on the computing-in-memory (CIM) architecture. By re-purposing the peripheral circuits, the certain NVM array can perform both storage and computing operations to accelerate the data-intensive convention Neural Networks (CNNs). However, the parallelism of the NVM-based CIM should be considered. In this paper, we present a CIM architecture developed by the Spin-orbit Torque (SOT) MRAM using both read-out and write-in operations. We highlight the memory structure and control method of the write-in operations. With the excellent write performance of SOT-MRAM, the proposed writein operation can obtain ultra-fast and energy-efficient computing data operations. The write-in operation works as a complement of the conventional read-out CIM architecture rather than replace it.
{"title":"Ultra-fast and Energy-efficient Write-Computing Operation for Neuromorphic Computing","authors":"Liang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao","doi":"10.1109/ISOCC47750.2019.9078528","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078528","url":null,"abstract":"Emerging Non-volatile memory (NVM) has demonstrated superior performance on the computing-in-memory (CIM) architecture. By re-purposing the peripheral circuits, the certain NVM array can perform both storage and computing operations to accelerate the data-intensive convention Neural Networks (CNNs). However, the parallelism of the NVM-based CIM should be considered. In this paper, we present a CIM architecture developed by the Spin-orbit Torque (SOT) MRAM using both read-out and write-in operations. We highlight the memory structure and control method of the write-in operations. With the excellent write performance of SOT-MRAM, the proposed writein operation can obtain ultra-fast and energy-efficient computing data operations. The write-in operation works as a complement of the conventional read-out CIM architecture rather than replace it.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126407608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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