Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037448
R. Spencer, S. Sturm
A circuit has been developed which performs a continuoustime analog computation of the f m t two moments of a discrete distribution of currents. The circuit is intended for use with tactile sensor arrays and it is assumed that there are currents available which are proportional to the sum of the forces applied to the elements in each column and row. The zeroth moment then corresponds to the total force on the array and the first moments of the row and column sums correspond to the means of the pressure distributions in the two directions. The circuit comprises a canonical cell which is repeated once for each input current (i.e., once for each column or row) and a divider circuit which is used once for each distribution (i.e., one for the row distribution and one for the column distribution). The reveating canonical cell uses onlv five transistors and can be cascadeTd to work with an NxM a&y for any values of N and M. Background It has long been recognized that the next generation of robots will require 'smart tactile sensors in addition to vision and the standard sensors used to control motion [1,21. Smart tactile sensors could perform some preliminary data reduction in order to reduce the volume of data sent to a digital controller, and would also facilitate the implementation of local feedback control loops in the gripper thereby freeing the central controller for higher level tasks. It is not clear at this time how much processing should be performed locally, but it is clear that the total force and the center of contact of the force would both be useful for obtaining and maintaining a stable grasp, and that moments. in particular, would be useful 131. Continuous-time analog control is usually capable of responding more rapidly than digital control. For low-level functions like total force it may make sense to use analog control loops. The circuit described here provides a total force output (the zeroth moment) in addition to outputs for the mean (the first moment) of the pressure distribution for both the row and column sums. If the pressure distribution is unimodal, which is likely for a curved finger on an articulated hand, then the mean is a measure of the location of the contact. Figure 1 shows the assumed architecture of the sensor array. Each individual element, called a tactel, has two open-collector current outputs. The tactel outputs are tied together to produce row and column sums. As shown in the figure, the column sums represent discrete samples of the pressure distribution in the x direction while the row sums represent discrete samples of the pressure distribution in they direction. The "ray would usually be covered with an elastic layer so that point loads applied between sensors would produce a response. Figure 1 also shows the canonical circuit block, hereinafter called the cell, associated with each row and column. The first two moments of the discrete force dismbutions are given by the following sums. where J-0 is the zerot
{"title":"A continuous-time analog moment calculating circuit","authors":"R. Spencer, S. Sturm","doi":"10.1109/VLSIC.1988.1037448","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037448","url":null,"abstract":"A circuit has been developed which performs a continuoustime analog computation of the f m t two moments of a discrete distribution of currents. The circuit is intended for use with tactile sensor arrays and it is assumed that there are currents available which are proportional to the sum of the forces applied to the elements in each column and row. The zeroth moment then corresponds to the total force on the array and the first moments of the row and column sums correspond to the means of the pressure distributions in the two directions. The circuit comprises a canonical cell which is repeated once for each input current (i.e., once for each column or row) and a divider circuit which is used once for each distribution (i.e., one for the row distribution and one for the column distribution). The reveating canonical cell uses onlv five transistors and can be cascadeTd to work with an NxM a&y for any values of N and M. Background It has long been recognized that the next generation of robots will require 'smart tactile sensors in addition to vision and the standard sensors used to control motion [1,21. Smart tactile sensors could perform some preliminary data reduction in order to reduce the volume of data sent to a digital controller, and would also facilitate the implementation of local feedback control loops in the gripper thereby freeing the central controller for higher level tasks. It is not clear at this time how much processing should be performed locally, but it is clear that the total force and the center of contact of the force would both be useful for obtaining and maintaining a stable grasp, and that moments. in particular, would be useful 131. Continuous-time analog control is usually capable of responding more rapidly than digital control. For low-level functions like total force it may make sense to use analog control loops. The circuit described here provides a total force output (the zeroth moment) in addition to outputs for the mean (the first moment) of the pressure distribution for both the row and column sums. If the pressure distribution is unimodal, which is likely for a curved finger on an articulated hand, then the mean is a measure of the location of the contact. Figure 1 shows the assumed architecture of the sensor array. Each individual element, called a tactel, has two open-collector current outputs. The tactel outputs are tied together to produce row and column sums. As shown in the figure, the column sums represent discrete samples of the pressure distribution in the x direction while the row sums represent discrete samples of the pressure distribution in they direction. The \"ray would usually be covered with an elastic layer so that point loads applied between sensors would produce a response. Figure 1 also shows the canonical circuit block, hereinafter called the cell, associated with each row and column. The first two moments of the discrete force dismbutions are given by the following sums. where J-0 is the zerot","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133932998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037440
S. Akui, S. Takagi, M. Furihata, M. Nagata, T. Yanagisawa
In+3xdu&i on The monolithic filter in reference (1) requires no pnp transistors even in bias circuits and its implementation by a standard bipolar process showed good frequency characteristics up to 10 MHz. This fact tempts us to implement higher-frequency filters by a much advanced process. This summary reports a monolithic implementation of a 100 MHz lowpass filter by a 3 micron biplar process. The lowpass filter is realized by a NIC-based gyrator technique like in reference (1 ) . Although the lowpass filter inherits low sensitivity property to reactance elements from a prototype LCR filter, a canpensation for nonidealities of transistors is indispensable especially in such a extremely high-frequency filter. The campensation method is discussed in this summary. A monolithic implementation and experimental results of the filter are shown.
{"title":"100 MHz monolithic lowpass filter using balanced-type NIC's","authors":"S. Akui, S. Takagi, M. Furihata, M. Nagata, T. Yanagisawa","doi":"10.1109/VLSIC.1988.1037440","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037440","url":null,"abstract":"In+3xdu&i on The monolithic filter in reference (1) requires no pnp transistors even in bias circuits and its implementation by a standard bipolar process showed good frequency characteristics up to 10 MHz. This fact tempts us to implement higher-frequency filters by a much advanced process. This summary reports a monolithic implementation of a 100 MHz lowpass filter by a 3 micron biplar process. The lowpass filter is realized by a NIC-based gyrator technique like in reference (1 ) . Although the lowpass filter inherits low sensitivity property to reactance elements from a prototype LCR filter, a canpensation for nonidealities of transistors is indispensable especially in such a extremely high-frequency filter. The campensation method is discussed in this summary. A monolithic implementation and experimental results of the filter are shown.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129797216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037420
S. Hayakawa, K. Sato, A. Aono, T. Yoshida, T. Ohmi, K. Ochii
{"title":"A process-insensitivity voltage down converter suitable for half-micron SRAM's","authors":"S. Hayakawa, K. Sato, A. Aono, T. Yoshida, T. Ohmi, K. Ochii","doi":"10.1109/VLSIC.1988.1037420","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037420","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131996097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037421
M. Matsui, S. Hayakawa, K. Sato, A. Suzuki, N. Upakawa, T. Hamano, T. Ohtani, K. Ochit
Scaled SRAMs suffer from large power dissipation because both the number of cells and the transistor drivability increase. In CMOS SRAMs the automatic power down (APD) scheme ([I]) is widely used on the read operation. In the APD scheme, word lines and sense amplifiers to which idling current is indispensable, are activaled dynamically by a timer pulse which is generated from address transition demtors (ATDs). and the operation power on rather low frequency is reduced. In order to salvage the slowest bits and to improve yield. however, the APD timer pulse should be 1.0 1.5 times as wide as the access time. Therefore the APD scheme cannot conribule the power reduction under the'minimum operation cycle. Besides, the scheme doesn't function on the write operation. This paper describes two novel power down circuits suitable for high density CMOS SRAMs. One is self-timed power down (SPD) scheme which employs self-timed mechanism for the data read-out completion. The other is automatic power down scheme on the write operation (APDW). The effectiveness of these new circuits is demonstrated on a 1M bit CMOS SRAM.
{"title":"Two novel power-down circuits on the 1Mb CMOS SRAM","authors":"M. Matsui, S. Hayakawa, K. Sato, A. Suzuki, N. Upakawa, T. Hamano, T. Ohtani, K. Ochit","doi":"10.1109/VLSIC.1988.1037421","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037421","url":null,"abstract":"Scaled SRAMs suffer from large power dissipation because both the number of cells and the transistor drivability increase. In CMOS SRAMs the automatic power down (APD) scheme ([I]) is widely used on the read operation. In the APD scheme, word lines and sense amplifiers to which idling current is indispensable, are activaled dynamically by a timer pulse which is generated from address transition demtors (ATDs). and the operation power on rather low frequency is reduced. In order to salvage the slowest bits and to improve yield. however, the APD timer pulse should be 1.0 1.5 times as wide as the access time. Therefore the APD scheme cannot conribule the power reduction under the'minimum operation cycle. Besides, the scheme doesn't function on the write operation. This paper describes two novel power down circuits suitable for high density CMOS SRAMs. One is self-timed power down (SPD) scheme which employs self-timed mechanism for the data read-out completion. The other is automatic power down scheme on the write operation (APDW). The effectiveness of these new circuits is demonstrated on a 1M bit CMOS SRAM.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114538878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037453
Y. Arai, T. Baba
{"title":"A CMOS time to digital converter VLSI for high-energy physics","authors":"Y. Arai, T. Baba","doi":"10.1109/VLSIC.1988.1037453","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037453","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123510338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037407
M. Verleysen, B. Sirletti, P. Jespers
{"title":"A large VLSI fully interconnected neural network","authors":"M. Verleysen, B. Sirletti, P. Jespers","doi":"10.1109/VLSIC.1988.1037407","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037407","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129993966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037403
S. Schuster, T. Chappell, B. Chappell, J. Allan, J. Sun, S. Klepner, R. Franch, P. Greier, P. Restle
{"title":"A 3.5ns CMOS 64K ECL RAM at 77/spl deg/K","authors":"S. Schuster, T. Chappell, B. Chappell, J. Allan, J. Sun, S. Klepner, R. Franch, P. Greier, P. Restle","doi":"10.1109/VLSIC.1988.1037403","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037403","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037419
K. L. Wang, K. Teng, M. D. Bader, R. Kung
{"title":"A low standby power, high efficiency, clamped P-well bias generator for high density fast SRAMs","authors":"K. L. Wang, K. Teng, M. D. Bader, R. Kung","doi":"10.1109/VLSIC.1988.1037419","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037419","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122781123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037433
T. Nakayama, Y. Miyawaki, K. Kobayashi, Y. Terada, H. Arima, T. Matsukawa, T. Yoshihara
Recently, several types of Rash EEPROMs have been proposed 1 ' ) 1 3 1 . These Bash EEPROMs, however, require a external high voltage supply for programming and the rrose/wntc cycling of them is one or two orders less than that of normal EEPROMs, because programming is accomplished by hot electron injection into the Boating gate. On the other hand, the memory cell of nornivl EEPROM8 which is byte erase type consists of two transistors, that is a bit select transistor and D memory transistor, and has a byte select transistor per byte. The chip sise is two to three timea larger than that of EPROM8 and Baah EEPROMs, because four parity bite per byte are required for ECC in addition to the large cell a i m This paper presents a 5V only 1 Tr. page erase type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program iuhibited by applying U program inhibiting voltage to the draina and the control gates. The number of parity bit for ECG is five per two bytes, which are controled by LB signal. LB is the lowest address input. The total number of memory cells is 88 % compared to byte erase type EEPROMs and the chip siae has been substantially reduced. The device has fast two byte serial I C E O ~ I mode.
{"title":"A 5V only 1 Tr, 256K EEPROM with page mode erase","authors":"T. Nakayama, Y. Miyawaki, K. Kobayashi, Y. Terada, H. Arima, T. Matsukawa, T. Yoshihara","doi":"10.1109/VLSIC.1988.1037433","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037433","url":null,"abstract":"Recently, several types of Rash EEPROMs have been proposed 1 ' ) 1 3 1 . These Bash EEPROMs, however, require a external high voltage supply for programming and the rrose/wntc cycling of them is one or two orders less than that of normal EEPROMs, because programming is accomplished by hot electron injection into the Boating gate. On the other hand, the memory cell of nornivl EEPROM8 which is byte erase type consists of two transistors, that is a bit select transistor and D memory transistor, and has a byte select transistor per byte. The chip sise is two to three timea larger than that of EPROM8 and Baah EEPROMs, because four parity bite per byte are required for ECC in addition to the large cell a i m This paper presents a 5V only 1 Tr. page erase type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program iuhibited by applying U program inhibiting voltage to the draina and the control gates. The number of parity bit for ECG is five per two bytes, which are controled by LB signal. LB is the lowest address input. The total number of memory cells is 88 % compared to byte erase type EEPROMs and the chip siae has been substantially reduced. The device has fast two byte serial I C E O ~ I mode.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037409
T. Yamasaki, K. Shima, S. Komori, T. Tamura, T. Ohno, O. Tomisawa, H. Terada
{"title":"VLSI implementation of the variable length pipeline scheme for data-driven processors","authors":"T. Yamasaki, K. Shima, S. Komori, T. Tamura, T. Ohno, O. Tomisawa, H. Terada","doi":"10.1109/VLSIC.1988.1037409","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037409","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125949777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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