Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037397
M. Nayebi, B. Wooley
I. lntroductbn ABiCMOSooerationalampllierwiihd.e. aainof 6548 and bandwidthofover ~ O O M H Z sdescrlbed The amp noer can awe a 5OLlload wnn a Yonage sw ng 01 T I V h JSS t5 V and -5 V s~pplies and ach wes a 110 dB CMRR h s mended lor ,re in samp e-and-hola and anaog-to-algira mnvnrslon systemsoperat ngstvaeofreqLenciesenaabove. Thec rc~nisoeinglabr caleo n a BiCMOS tscnm ogy dew opea lor high.rpeed stalc RAM app cat ons. The tecnnology LSBO 1.1 dosgn wles. ana the m n mJm emmer sze IS 1 .I +m x 3pm. The0 e s!2e is38 x47 m'P. Tnepowerdtss paton en tnemre oltneampdier s112mW,wh etnat mtheonp~tstage s300mW.
{"title":"A 0.5 GHz BiCMOS operational amplifier","authors":"M. Nayebi, B. Wooley","doi":"10.1109/VLSIC.1988.1037397","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037397","url":null,"abstract":"I. lntroductbn ABiCMOSooerationalampllierwiihd.e. aainof 6548 and bandwidthofover ~ O O M H Z sdescrlbed The amp noer can awe a 5OLlload wnn a Yonage sw ng 01 T I V h JSS t5 V and -5 V s~pplies and ach wes a 110 dB CMRR h s mended lor ,re in samp e-and-hola and anaog-to-algira mnvnrslon systemsoperat ngstvaeofreqLenciesenaabove. Thec rc~nisoeinglabr caleo n a BiCMOS tscnm ogy dew opea lor high.rpeed stalc RAM app cat ons. The tecnnology LSBO 1.1 dosgn wles. ana the m n mJm emmer sze IS 1 .I +m x 3pm. The0 e s!2e is38 x47 m'P. Tnepowerdtss paton en tnemre oltneampdier s112mW,wh etnat mtheonp~tstage s300mW.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037411
T. Machida, T. Matsuda, F. Tsukuda, R. Hashishita
This paper will describe a V U 1 chip-set for Personal Computers. It consists of Peripheral Controller (PERIJ made of I1 standard peripheral mega-macro block, Text Controller (CRZT), and Graphics Controller (CRTG). The chips fully utilize hierarchical automatic layout design system. 205K transistors have been integrated by a three chip-set. They have been fabricated by I.5pm double metal-layer CMOS process technology. The chip-set allows to design a personal computer of M-size with CPU, memory and some inteqace logics. The personal computer consumes only 114 of power. compared to a standard version with the same system configuration. Introduction : This paper describes a VLSI chip-set for Personal Computers. The set consists of Peripheral Controller (PERI), Text Controller (CRm), and Graphics Controller bus and address bus. Bus controller gives bus interface Control signals, such as memory readlwrite and I10 readwrite, to mega-macro blocks. Custom-macro blocks are provided to realize user-defined functions, such as timing control of the device, extemal interface, offchip memory interface, and so on. Standard cell approach realizes these custom-macros. Microphotograph of the chip is shown in Fig.3. The CRTT contains a Graphic Display Controller (GDC) mega-macro and 5.4K-gate custom-macro.The CRTG contains a GDC and 11 .5K-gate custom-macro. Table 1 summarizes features of three chips. Fig.4 shows an example of PC system configuration by the chip-set. As is shown, only the interface logics are required, in addition to ROM/RAM and CPU. Mega-Macro Blocks : The mega-macro blocks are the (CKIti). A VLSI chip-set which integrates various standard peripheral LSIs is highly required by system vendors so that a small system with low Power consumption can be realized. In this case, the chip-set should be software-compatible with the off-the-shelf standard peripheral LSIs, and should be developedin shortperiod. A simple way of implementing such VLSIs without modifying the original LSIS tends to have enormous chip area. Entirely new design of standard LSI by another technology, such as standard cell approach, also has enormous man-power to modify existing standard LSI circuit for standard cell. mozified versions of standard m&roprocessor peripheral controllers. Features of mega-macros are shown in Table 2. Use of a mega-macro block reduces the number of transistors and area size, compared to the standard cell approach. For example, the PI0 mega-macro block has 2,500 transistors, however it would have 4,400 transistors if it were designed by using standard cell technique. In the PERI-chip case, this technique has reduced 37% of total chip size than the standard cell design. The original layout of standard LSIs were used as first approximation of mega-macro blocks, then VO pads were stripped out to have the smallest block area. It has brought 25% to 54% of area reduction, compared to ones with The chip-set has been developed to fulfill these I/O Dads. The oumut
{"title":"VLSI chip-set for personal computers","authors":"T. Machida, T. Matsuda, F. Tsukuda, R. Hashishita","doi":"10.1109/VLSIC.1988.1037411","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037411","url":null,"abstract":"This paper will describe a V U 1 chip-set for Personal Computers. It consists of Peripheral Controller (PERIJ made of I1 standard peripheral mega-macro block, Text Controller (CRZT), and Graphics Controller (CRTG). The chips fully utilize hierarchical automatic layout design system. 205K transistors have been integrated by a three chip-set. They have been fabricated by I.5pm double metal-layer CMOS process technology. The chip-set allows to design a personal computer of M-size with CPU, memory and some inteqace logics. The personal computer consumes only 114 of power. compared to a standard version with the same system configuration. Introduction : This paper describes a VLSI chip-set for Personal Computers. The set consists of Peripheral Controller (PERI), Text Controller (CRm), and Graphics Controller bus and address bus. Bus controller gives bus interface Control signals, such as memory readlwrite and I10 readwrite, to mega-macro blocks. Custom-macro blocks are provided to realize user-defined functions, such as timing control of the device, extemal interface, offchip memory interface, and so on. Standard cell approach realizes these custom-macros. Microphotograph of the chip is shown in Fig.3. The CRTT contains a Graphic Display Controller (GDC) mega-macro and 5.4K-gate custom-macro.The CRTG contains a GDC and 11 .5K-gate custom-macro. Table 1 summarizes features of three chips. Fig.4 shows an example of PC system configuration by the chip-set. As is shown, only the interface logics are required, in addition to ROM/RAM and CPU. Mega-Macro Blocks : The mega-macro blocks are the (CKIti). A VLSI chip-set which integrates various standard peripheral LSIs is highly required by system vendors so that a small system with low Power consumption can be realized. In this case, the chip-set should be software-compatible with the off-the-shelf standard peripheral LSIs, and should be developedin shortperiod. A simple way of implementing such VLSIs without modifying the original LSIS tends to have enormous chip area. Entirely new design of standard LSI by another technology, such as standard cell approach, also has enormous man-power to modify existing standard LSI circuit for standard cell. mozified versions of standard m&roprocessor peripheral controllers. Features of mega-macros are shown in Table 2. Use of a mega-macro block reduces the number of transistors and area size, compared to the standard cell approach. For example, the PI0 mega-macro block has 2,500 transistors, however it would have 4,400 transistors if it were designed by using standard cell technique. In the PERI-chip case, this technique has reduced 37% of total chip size than the standard cell design. The original layout of standard LSIs were used as first approximation of mega-macro blocks, then VO pads were stripped out to have the smallest block area. It has brought 25% to 54% of area reduction, compared to ones with The chip-set has been developed to fulfill these I/O Dads. The oumut ","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037427
S. Hamilton
{"title":"Enhanced implication for automatic test pattern generation","authors":"S. Hamilton","doi":"10.1109/VLSIC.1988.1037427","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037427","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123484484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037413
K. Kaneko, S. Goldta, T. Kishi, Y. Tsue, K. Zaiki, M. Watanabe, T. Mimura, H. Kadota
Introduction For the past twenty years. parallel processing has been considered a promlslng technlque for hlgh-performance computers of the next generation. Recently. several machlnes wlth parallel architecture have become commercially available. but their performancc Is lower than what has been expected. One of the maJor problems to be solved for a hlgh performancc parallel machlne Is deslgnlng a n efficlent network for transfenlng data between the processor elements (PES). A new network Structure for a parallel processor system. ADENA. has been proposed[ll. which wlll reallze emdent data transmlsslon and hlgh-speed numerical computatlon. In thls paper. two component devlces. a chlp set for bulldlng that network, wlll be descrlhed. The first chip. HM. Is a high-performance bldlrectional Buffer-Memory (FIFO) array. and the second chlp. SRC. Is a data-Send/ReecRc Controller. Two new techniques are used to get a hlgh data-hansfa rate: 11 Metchlng Butfn-Memory status I : empty/rUll I by SRC. 21 C m l t deslgn for a high-speed RFO wlth m m u m readnow-hugh ume. The peak data-transfer rate through these chips is zOMBytes/s for each bus. The structure and the usage of the network are also dlscussed.
在过去的二十年里。并行处理已被认为是下一代高性能计算机的一项有待解决的技术。最近。一些机器与lth并行架构已经成为商业可用。但他们的表现低于预期。高性能并行机需要解决的主要问题之一是如何设计一个有效的网络来实现处理器单元之间的数据传输。一种新的并行处理器系统网络结构。阿登纳人。已被提议[1]。实现了实时数据传输和高速数值计算。在这篇论文中。两个组件的设备。我们将描述用于构建该网络的CHLP集。第一个芯片。嗯。是一个高性能的定向缓冲存储器(FIFO)阵列。第二个chlp。SRC。是一个数据发送/ReecRc控制器。采用了两种新技术来获得高数据传输率:11 Metchlng button - memory status I: empty/rUll I by SRC。本文介绍了一种高速RFO的设计方法，该设计方法采用了高速RFO的设计方法。每个总线通过这些芯片的峰值数据传输速率为zOMBytes/s。讨论了网络的结构和使用方法。
{"title":"Network-component chip set for a parallel processor system","authors":"K. Kaneko, S. Goldta, T. Kishi, Y. Tsue, K. Zaiki, M. Watanabe, T. Mimura, H. Kadota","doi":"10.1109/VLSIC.1988.1037413","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037413","url":null,"abstract":"Introduction For the past twenty years. parallel processing has been considered a promlslng technlque for hlgh-performance computers of the next generation. Recently. several machlnes wlth parallel architecture have become commercially available. but their performancc Is lower than what has been expected. One of the maJor problems to be solved for a hlgh performancc parallel machlne Is deslgnlng a n efficlent network for transfenlng data between the processor elements (PES). A new network Structure for a parallel processor system. ADENA. has been proposed[ll. which wlll reallze emdent data transmlsslon and hlgh-speed numerical computatlon. In thls paper. two component devlces. a chlp set for bulldlng that network, wlll be descrlhed. The first chip. HM. Is a high-performance bldlrectional Buffer-Memory (FIFO) array. and the second chlp. SRC. Is a data-Send/ReecRc Controller. Two new techniques are used to get a hlgh data-hansfa rate: 11 Metchlng Butfn-Memory status I : empty/rUll I by SRC. 21 C m l t deslgn for a high-speed RFO wlth m m u m readnow-hugh ume. The peak data-transfer rate through these chips is zOMBytes/s for each bus. The structure and the usage of the network are also dlscussed.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131557983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037417
H. Okuyana, T. Nakano, S. Nishida, Jun Fukuchi, S. Arita
11. CIRCUIT CONFIGURATION The chip architecture of the RM is shown in Figure 1. The memry cell array is divided into 32 blocks allovs divided-word-line architecture. A main vord line runs Y-direction in the second-level metal and the divided vord lines drives only 64 memory cells. A bit line, vhich runs X-direction in the first-level =tal. is connected to only 128 memory cells. Also. only one of 32 blocks is activated remining other blocks in a standby state so that the pover dissipation is reduced. Figurq 2 and 3 shov the read out circuit and the internal timing diagram of theRAN. Double Activated Pulse: Yo&Line-Enable(nE) pulse and SenseAmplifier-Enable&#) pulse are generated by the Ampulse vhich is generated by detecting the transition of all addresses and CE input. So far the WLEpulse. vhich activates the vord line. was generated by the fallins edge of the ATl-pulse to obtain immunity against address skevs. This technique hinders the high speed access because of its stable operation. But in this RAN the LE-pulse is generated by the rising e k e of the ATl-pulse. not by the falling edge, so that the vord line is immediately turned on after an address transition occurs. Therefore it has been possible to reduce access time by the active period o f the ATD-pulse. On the other hand in order to o h i n sufficient immunity against address skevs. the SAE-pulse vhich activates the bus lines and the sense amplifiers is generated by the falling e k e of the ATl-pulse. The RC delay both of the rord lines and of the bit lines are reduced by the chip architecture. "he bus lines and the sense amplifiers are activated after all address changes have been stable. Consesuentlv it has been possible to obtain immunity aminst address skevs. After the data is E c h e d to the output buffer, the =-pulse and the SAE-pulse are inactivated . (1) Therefore, the power dissipation has been reduced in case of a long cycle read operation. Consequently. the high speed access, the lor pover dissipation and the complete immunity against address skevs have been achieved by usim this Double Activated Pulse circuit. To reduce the transition time of the output buffer, nev data output reset circuit has been developed. The data output is reset to a intermediate level before the true data output appars. In this circuit, the current through both the data output nchannel and p-channel HOSFET's is nothing. The true data output changes from the intermediate level. Therefore it has been possible to achieve the high speed access and to diminish the noise vhich occurrs oving to the peak current of the output buffer.
{"title":"A 7.5ns 32K x 8 high-speed CMOS SRAM","authors":"H. Okuyana, T. Nakano, S. Nishida, Jun Fukuchi, S. Arita","doi":"10.1109/VLSIC.1988.1037417","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037417","url":null,"abstract":"11. CIRCUIT CONFIGURATION The chip architecture of the RM is shown in Figure 1. The memry cell array is divided into 32 blocks allovs divided-word-line architecture. A main vord line runs Y-direction in the second-level metal and the divided vord lines drives only 64 memory cells. A bit line, vhich runs X-direction in the first-level =tal. is connected to only 128 memory cells. Also. only one of 32 blocks is activated remining other blocks in a standby state so that the pover dissipation is reduced. Figurq 2 and 3 shov the read out circuit and the internal timing diagram of theRAN. Double Activated Pulse: Yo&Line-Enable(nE) pulse and SenseAmplifier-Enable&#) pulse are generated by the Ampulse vhich is generated by detecting the transition of all addresses and CE input. So far the WLEpulse. vhich activates the vord line. was generated by the fallins edge of the ATl-pulse to obtain immunity against address skevs. This technique hinders the high speed access because of its stable operation. But in this RAN the LE-pulse is generated by the rising e k e of the ATl-pulse. not by the falling edge, so that the vord line is immediately turned on after an address transition occurs. Therefore it has been possible to reduce access time by the active period o f the ATD-pulse. On the other hand in order to o h i n sufficient immunity against address skevs. the SAE-pulse vhich activates the bus lines and the sense amplifiers is generated by the falling e k e of the ATl-pulse. The RC delay both of the rord lines and of the bit lines are reduced by the chip architecture. \"he bus lines and the sense amplifiers are activated after all address changes have been stable. Consesuentlv it has been possible to obtain immunity aminst address skevs. After the data is E c h e d to the output buffer, the =-pulse and the SAE-pulse are inactivated . (1) Therefore, the power dissipation has been reduced in case of a long cycle read operation. Consequently. the high speed access, the lor pover dissipation and the complete immunity against address skevs have been achieved by usim this Double Activated Pulse circuit. To reduce the transition time of the output buffer, nev data output reset circuit has been developed. The data output is reset to a intermediate level before the true data output appars. In this circuit, the current through both the data output nchannel and p-channel HOSFET's is nothing. The true data output changes from the intermediate level. Therefore it has been possible to achieve the high speed access and to diminish the noise vhich occurrs oving to the peak current of the output buffer.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131798581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037396
K. Sakamura, K. Kimbara, Y. Tominaga
All of us are well aware of the remarkably rapid pace of progress being made in semiconductor technology. This progress is spreading far and wide, high and low. As part of it. we're seeing -if not building -ever-smaller VLSl microprocessors that offer continually higher levels of performance. And these microprocessors are spreading in use and utility, to where they now are used in connection with or embedded in daily items and pieces of equipment that offer performance that was previously qu i t e inconceivable.
{"title":"The TRON project and development of a TRON-spec 32-bit microprocessor","authors":"K. Sakamura, K. Kimbara, Y. Tominaga","doi":"10.1109/VLSIC.1988.1037396","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037396","url":null,"abstract":"All of us are well aware of the remarkably rapid pace of progress being made in semiconductor technology. This progress is spreading far and wide, high and low. As part of it. we're seeing -if not building -ever-smaller VLSl microprocessors that offer continually higher levels of performance. And these microprocessors are spreading in use and utility, to where they now are used in connection with or embedded in daily items and pieces of equipment that offer performance that was previously qu i t e inconceivable.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129573833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037455
B. Ginetti, A. Vandemeulebroecke, P. Jespers
{"title":"RSD cyclic analog-to-digital converter","authors":"B. Ginetti, A. Vandemeulebroecke, P. Jespers","doi":"10.1109/VLSIC.1988.1037455","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037455","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133422406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037450
S. Fujii, H. Satoh, H. Shimizu, K. Matsuo, M. Kaizuka, I. Tsuchiya, K. Kasai
{"title":"A high-performance VFO-LSIusing 2-/spl mu/m CMOS analog and digital standard cell methodology","authors":"S. Fujii, H. Satoh, H. Shimizu, K. Matsuo, M. Kaizuka, I. Tsuchiya, K. Kasai","doi":"10.1109/VLSIC.1988.1037450","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037450","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037445
O. Vainio, H. Tenhunen, T. Korpiharju, J. Tomberg, Y. Neuvo
Abs t r ac t Fast pipelined implementat ion of t h e F E Median Hybr id filter has been designed on CM09. The Blter structure combines linear averaging subBltto a median opera t ion in a way that leads to a very efeeieet implementation. The fi l ter removes noise while preserving sharp edges in t h e signals. The integrated circuit c a n operate up to SOME. clock r a t e s and it is capable of 5ltving real time video aignals including future HDTV applications. The window size is adjustable from S to 257 samples.
本文在CM09上设计了fe中值混合滤波器的快速流水线实现。Blter结构将线性平均子Blter与中值运算结合在一起，以一种非常有效的方式实现。该滤波器去除噪声，同时保持信号的尖锐边缘。集成电路c a n工作到SOME。它可以接收实时视频信号，包括未来的高清电视应用。窗口大小可调，从S到257个样品。
{"title":"A video frequency bit-parallel CMOS FIR median hybrid filter","authors":"O. Vainio, H. Tenhunen, T. Korpiharju, J. Tomberg, Y. Neuvo","doi":"10.1109/VLSIC.1988.1037445","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037445","url":null,"abstract":"Abs t r ac t Fast pipelined implementat ion of t h e F E Median Hybr id filter has been designed on CM09. The Blter structure combines linear averaging subBltto a median opera t ion in a way that leads to a very efeeieet implementation. The fi l ter removes noise while preserving sharp edges in t h e signals. The integrated circuit c a n operate up to SOME. clock r a t e s and it is capable of 5ltving real time video aignals including future HDTV applications. The window size is adjustable from S to 257 samples.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128394264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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