Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037428
R. Swartz
{"title":"A technique for real-time measurement of d/sup i/V/dI/sup i/: application to high speed optical communications","authors":"R. Swartz","doi":"10.1109/VLSIC.1988.1037428","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037428","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037425
H. Tran, P. Fung, D. Scott, R. Havemann, R. Eklund
1 TIL ML The advent of BiCMOS technology brings the availability of bipolar and CMOS components to one silicon chip, and allows the integration oi bipolar high preeirion analog circuita with lower power digital circuitry in next generation of high performance products [l]. This paper will describe a BiCMOS TTL input buffer which employs analog circuit design techniques to enhance the circuit performance. This novel implementation demonstrates the broad range of analog design techniques which can be applied in BiCMOS digital c k u i t s . The Mynchronoua operation CMOS TTL input buffer has two major obstacles that have been taunting IC circuit designers-for years. First is the variations of input trip point across power .up ply, process and temperature. Second is the high power dissipation of the buffer's first stage inverter, which results from the small voltage swing of the TTL input level. Furthermore, for eompatibility to the standby power requirements of the existing products, a CMOS input buffer often must be gated by an enabling signal for switching lo and from the standby mode. These problems require compromises to be made between speed, power, yield and reliability. and thus tend to degrade the overall performance oi the device. The transistor i i a e s of the buffer's fint stsge inverter are chosen surh that the DC trip point is centered et a midpoint of the TTL input level (1.4 volts). However, as process, power supply and temperature fluctuate. the DC trip point deviates away from the midpoint and reduces the input signal margins, as shown in figure 1. In additional, a significant current is Bowing in the CMOS input buffer when its input 1s at TTL VIH level of 2.0 volts, M shown in figure 2a. This current is caused by the CMOS input buffer's first stage inverter which is partially in an on state. reference voltage of 1.4 volts LO II Threshold Reference (TREF) ckcuit to establish a CMOS inverter trip point dependent VTH signal. This signal is connected to bipolar transistor Q1 to supply a rcgulated voltage level to the source of the Pchannel pull-up MP1. This voltage level is designed to keep the trip point of the TCON input buffer's h t stage inverter at the midpoint of TTL high and low levels. The transistor sizes of the first stage inverter M also chosen such that the voltage a t the source ofthe Pchannel MPI ir alwayat or below L voltage level of (VTTLhi + Vtp); where VTTLhi is the TTL logic high level of 2.0 volts and Vtp is the Vt of the Pchanne1 transistor. Figure 2b shows a plot of the current of the TCON input buffer vs its input voltage when condition stated above is satisfied. The buffer (current is essentially ~ e r o when its input is held at a valid TTL level. This important feature allows the standby to active enabling signal to he omitted from the design of the input circuitry. The elimination of this enabling signal allows faster eircui1 operation because the output of the buffer is in II correct logic state during the
{"title":"A novel BiCMOS TTL input buffer; a merging of analog and digital circuit design techniques","authors":"H. Tran, P. Fung, D. Scott, R. Havemann, R. Eklund","doi":"10.1109/VLSIC.1988.1037425","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037425","url":null,"abstract":"1 TIL ML The advent of BiCMOS technology brings the availability of bipolar and CMOS components to one silicon chip, and allows the integration oi bipolar high preeirion analog circuita with lower power digital circuitry in next generation of high performance products [l]. This paper will describe a BiCMOS TTL input buffer which employs analog circuit design techniques to enhance the circuit performance. This novel implementation demonstrates the broad range of analog design techniques which can be applied in BiCMOS digital c k u i t s . The Mynchronoua operation CMOS TTL input buffer has two major obstacles that have been taunting IC circuit designers-for years. First is the variations of input trip point across power .up ply, process and temperature. Second is the high power dissipation of the buffer's first stage inverter, which results from the small voltage swing of the TTL input level. Furthermore, for eompatibility to the standby power requirements of the existing products, a CMOS input buffer often must be gated by an enabling signal for switching lo and from the standby mode. These problems require compromises to be made between speed, power, yield and reliability. and thus tend to degrade the overall performance oi the device. The transistor i i a e s of the buffer's fint stsge inverter are chosen surh that the DC trip point is centered et a midpoint of the TTL input level (1.4 volts). However, as process, power supply and temperature fluctuate. the DC trip point deviates away from the midpoint and reduces the input signal margins, as shown in figure 1. In additional, a significant current is Bowing in the CMOS input buffer when its input 1s at TTL VIH level of 2.0 volts, M shown in figure 2a. This current is caused by the CMOS input buffer's first stage inverter which is partially in an on state. reference voltage of 1.4 volts LO II Threshold Reference (TREF) ckcuit to establish a CMOS inverter trip point dependent VTH signal. This signal is connected to bipolar transistor Q1 to supply a rcgulated voltage level to the source of the Pchannel pull-up MP1. This voltage level is designed to keep the trip point of the TCON input buffer's h t stage inverter at the midpoint of TTL high and low levels. The transistor sizes of the first stage inverter M also chosen such that the voltage a t the source ofthe Pchannel MPI ir alwayat or below L voltage level of (VTTLhi + Vtp); where VTTLhi is the TTL logic high level of 2.0 volts and Vtp is the Vt of the Pchanne1 transistor. Figure 2b shows a plot of the current of the TCON input buffer vs its input voltage when condition stated above is satisfied. The buffer (current is essentially ~ e r o when its input is held at a valid TTL level. This important feature allows the standby to active enabling signal to he omitted from the design of the input circuitry. The elimination of this enabling signal allows faster eircui1 operation because the output of the buffer is in II correct logic state during the ","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037416
T. Sakurai, K. Nogami, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maegucm, K. Kobayasm, T. Ando, Y. Hayakasfh, T. Mfyosfu, K. Sato
Introduction A w h e memory is effective in enhancing CPU system throughput[lI. A circuit design aspect of a newly developed integrated cache memory which includes 32Kbyte DATA memory, with a typical IUT delay of 18ns is desnibed. The present memory achieves four times larger DATA memory size together with much faster operation sped compared with the recenlly reponed integrated cache memory[2l. The memory includes 32Kbyte DATA (INSISTRUCTION) memory, 3Kbit TAG memory. XKbit VALID flag, 2Kbit LRU flag. comparator. and CPU interface logic circuits. The inclusion of DATA memory is imponant in improving system cycle time as shown in Fig.1. It is also imponant for reducing board area and cost, because it replaces about ten LSl's.
内存是提高CPU系统吞吐量的有效方法[j]。介绍了一种新开发的集成缓存存储器的电路设计，该存储器包括32Kbyte DATA存储器，典型IUT延迟为18ns。与最近发布的集成缓存存储器相比，目前的存储器实现了四倍大的数据存储器容量和更快的操作速度[21]。内存包括32Kbyte DATA (insstruction)内存，3Kbit TAG内存。XKbit VALID标志，2Kbit LRU标志。比较器。以及CPU接口逻辑电路。数据存储器的加入对于提高系统周期时间非常重要，如图1所示。它对于减少电路板面积和成本也很重要，因为它取代了大约10个LSl。
{"title":"A circuit design of 32Kbyte integrated cache memory","authors":"T. Sakurai, K. Nogami, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maegucm, K. Kobayasm, T. Ando, Y. Hayakasfh, T. Mfyosfu, K. Sato","doi":"10.1109/VLSIC.1988.1037416","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037416","url":null,"abstract":"Introduction A w h e memory is effective in enhancing CPU system throughput[lI. A circuit design aspect of a newly developed integrated cache memory which includes 32Kbyte DATA memory, with a typical IUT delay of 18ns is desnibed. The present memory achieves four times larger DATA memory size together with much faster operation sped compared with the recenlly reponed integrated cache memory[2l. The memory includes 32Kbyte DATA (INSISTRUCTION) memory, 3Kbit TAG memory. XKbit VALID flag, 2Kbit LRU flag. comparator. and CPU interface logic circuits. The inclusion of DATA memory is imponant in improving system cycle time as shown in Fig.1. It is also imponant for reducing board area and cost, because it replaces about ten LSl's.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037439
G. Venzl, R. Mitchell
{"title":"A compilable binary tree parallel multiplier designed for speed and testability","authors":"G. Venzl, R. Mitchell","doi":"10.1109/VLSIC.1988.1037439","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037439","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128954874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037404
T. Chappell, S. Schuster, B. Chappell, J. Allan, S. Klepner, R. Franch, P. Greier, P. Restle
INTQnnl lrTlnN Y-Address. Dolo-In. and Write Conrrol Inouls (22 Inoulsl. These in.. . . ..----. .-.. . . . . pnts use the dynamic sense amplifier receiver shown in Fig. 2 with slow-set and fast-set clocking for ECL-to-CMOS conversion. As in DRAMS, the dynamic sense amplifier operates reliably with signals as small as 100 mV. Although this receiver is somewhat slower than the X-address receiver. it has no DC standby DOWCT and it is still much Sub-lo ns 64Kb SRAMs with ECL interfaces have been reported in both bipolar and BiCMOS technologies [I-21. This Paper reports the first sub-10 ns 64Kb CMOS RAM with ECL interface signals. The high performance of this RAM is due to the combination of innova_ . tive CMOS circuit design and an advanced. SeleCti"elY scaled CMOS process with 0.5 pm Leff, both of which will be described.
{"title":"A 6.2 ns 64Kb CMOS RAM with ECL interfaces","authors":"T. Chappell, S. Schuster, B. Chappell, J. Allan, S. Klepner, R. Franch, P. Greier, P. Restle","doi":"10.1109/VLSIC.1988.1037404","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037404","url":null,"abstract":"INTQnnl lrTlnN Y-Address. Dolo-In. and Write Conrrol Inouls (22 Inoulsl. These in.. . . ..----. .-.. . . . . pnts use the dynamic sense amplifier receiver shown in Fig. 2 with slow-set and fast-set clocking for ECL-to-CMOS conversion. As in DRAMS, the dynamic sense amplifier operates reliably with signals as small as 100 mV. Although this receiver is somewhat slower than the X-address receiver. it has no DC standby DOWCT and it is still much Sub-lo ns 64Kb SRAMs with ECL interfaces have been reported in both bipolar and BiCMOS technologies [I-21. This Paper reports the first sub-10 ns 64Kb CMOS RAM with ECL interface signals. The high performance of this RAM is due to the combination of innova_ . tive CMOS circuit design and an advanced. SeleCti\"elY scaled CMOS process with 0.5 pm Leff, both of which will be described.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124254162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037438
R. Shamz, A. Lopez, J. Michejda, S. Hillenius, J. M. Andrews, A. J. Studwell
{"title":"A 6.75ns single level metal CMOS 16x16 multiplier IC","authors":"R. Shamz, A. Lopez, J. Michejda, S. Hillenius, J. M. Andrews, A. J. Studwell","doi":"10.1109/VLSIC.1988.1037438","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037438","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126445717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037442
Chung-Yu Wu, Tsai-Chung Yu, Shin-Chih Chang
A new algorithm t o r e a l i z e SC FIR and I I R f i l t e r s i s presented. It uses t h e SC d i f f e r e n t i a t o r and the SC i n v e r t e r as building blocks. Simple Structure and good performance make t h e design q u i t e a t t r a c t i v e i n V L S I s igna l processing.
{"title":"Realization of FIR and IIR ftlters using SC differentiators","authors":"Chung-Yu Wu, Tsai-Chung Yu, Shin-Chih Chang","doi":"10.1109/VLSIC.1988.1037442","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037442","url":null,"abstract":"A new algorithm t o r e a l i z e SC FIR and I I R f i l t e r s i s presented. It uses t h e SC d i f f e r e n t i a t o r and the SC i n v e r t e r as building blocks. Simple Structure and good performance make t h e design q u i t e a t t r a c t i v e i n V L S I s igna l processing.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124878595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037454
H. Ando, M. Naxai, H. Ono, N. Ozawa, S. Ouba, T. Suzuki, M. Ufuara, I. Taxemoto
Introduction VCA(Video-Cassette-Recorder) cameras have been developed to have high sensitivity a n d low smear noise(l),(2), (3). Nowadays, g o o d resolution for motion pictures is eagerly desired. To satisfy the characteristic, an electronic shutter function i s necessary. Moreover, a variable shutter scheme, which controls signal integration time, is suitable for an electronic iris control, too. FIT(Frame-Interline-TransferbCCD imagers or QFIT(Ouasi-FIT)-CCD imagers have already been reported to have a shutter function(4). (5). They, however, should have one or partial frame memory, s o their die sizes are greater than those of conventional IL(lnter-Line)-CCDs. In this paper, a 489(V)*670(H) pixels 1/2 inch lL-CCD imager with low-voltage variable shutter has been realized by a novel overflow gate and a complete depletion photo-diode structure.
{"title":"A 1/2 inch-CCD imager with low-voltage variable shutter","authors":"H. Ando, M. Naxai, H. Ono, N. Ozawa, S. Ouba, T. Suzuki, M. Ufuara, I. Taxemoto","doi":"10.1109/VLSIC.1988.1037454","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037454","url":null,"abstract":"Introduction VCA(Video-Cassette-Recorder) cameras have been developed to have high sensitivity a n d low smear noise(l),(2), (3). Nowadays, g o o d resolution for motion pictures is eagerly desired. To satisfy the characteristic, an electronic shutter function i s necessary. Moreover, a variable shutter scheme, which controls signal integration time, is suitable for an electronic iris control, too. FIT(Frame-Interline-TransferbCCD imagers or QFIT(Ouasi-FIT)-CCD imagers have already been reported to have a shutter function(4). (5). They, however, should have one or partial frame memory, s o their die sizes are greater than those of conventional IL(lnter-Line)-CCDs. In this paper, a 489(V)*670(H) pixels 1/2 inch lL-CCD imager with low-voltage variable shutter has been realized by a novel overflow gate and a complete depletion photo-diode structure.","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115896085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037412
T. Morita, T. Hayashi, Y. Saita, T. Ohno, S. Yoshida, T. Fukuda, R. Ikeda
A 3 2 b i t P r o c a s s o r f o r ESS ( E l e c t r o n i c S w i t c h l n s S y s t e m s ) w i t h m i x e d (R ISC & C iSC) i n s t r u c t i o n s e t i s d e s c r i b e d . The p e r f o r m a n c e i s a c h i e v e d by a 4 s t a g e P i p e l i n e and t h e l o c a l s t o r a g e f o r R i S C l i k e i n s t r u c t i o n s and b y WCS ( W r i t a b l e C o n t r o l S t o r a g e ) f o r C iSC l i k e i n s t r u c t i o n s a t 16MHz. U s i n s 1 . 2 m i c r o n d o u b l e m e t a l CMOS t s c h n a l o o v . t h e c h i p c o n t a i n s 160K t r a n s i s t o r s o n a 13.2x13.7 mm d i e .
{"title":"A 5.5 MIPS call handling processor for switching systems","authors":"T. Morita, T. Hayashi, Y. Saita, T. Ohno, S. Yoshida, T. Fukuda, R. Ikeda","doi":"10.1109/VLSIC.1988.1037412","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037412","url":null,"abstract":"A 3 2 b i t P r o c a s s o r f o r ESS ( E l e c t r o n i c S w i t c h l n s S y s t e m s ) w i t h m i x e d (R ISC & C iSC) i n s t r u c t i o n s e t i s d e s c r i b e d . The p e r f o r m a n c e i s a c h i e v e d by a 4 s t a g e P i p e l i n e and t h e l o c a l s t o r a g e f o r R i S C l i k e i n s t r u c t i o n s and b y WCS ( W r i t a b l e C o n t r o l S t o r a g e ) f o r C iSC l i k e i n s t r u c t i o n s a t 16MHz. U s i n s 1 . 2 m i c r o n d o u b l e m e t a l CMOS t s c h n a l o o v . t h e c h i p c o n t a i n s 160K t r a n s i s t o r s o n a 13.2x13.7 mm d i e .","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123356302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VLSIC.1988.1037415
T. Seki, E. Ito, K. Komatsu, T. Yabu, N. Suzuki
{"title":"A 14ns 256K CMOS SRAM with internal parity","authors":"T. Seki, E. Ito, K. Komatsu, T. Yabu, N. Suzuki","doi":"10.1109/VLSIC.1988.1037415","DOIUrl":"https://doi.org/10.1109/VLSIC.1988.1037415","url":null,"abstract":"","PeriodicalId":115887,"journal":{"name":"Symposium 1988 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128874757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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