Symposium 1988 on VLSI Circuits最新文献

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A 256K CMOS EEPROM with enhanced reliability and testability 256K CMOS EEPROM，增强了可靠性和可测试性

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037434

J. Do, J. K. Kim, H. G. Lee, J. Choi, H. Lim

This paper will describe a 32K x 8 CMOS EEPROM with on-chip ECC (Error Checking and Correction). Test features that enable effective testing of the on-chip ECC circuit and cell thrshold voltage will be described. A novel electrically programmable fuse circuit renders reliable implementation of redundancy and programmable optional features. The 5V full-featured [ I ] , [2] EEPROM with 64-byte page write mode has additional test features such as ECC disable, write cycle and program voltage (Vpp) ramp speed control, and write inhibit Vcc level adjustment. A double-poly, single-metal N-well CMOS technilagy with thin tunnel-oxide ( < I O O A O ) floating-gate cell is used to build the EEPROM. Minimum feature size 1 . 2 um is used to achieve 60 um' cell size and 68 mm' chip size. A 350A' composite interpoly dielectric is used to provide enhanced cell data retention characteristics. Far high voltage path, graded junction formed by double ion implantation is used to increase breakdown voltage. A modified Hamming code ECC scheme, having 4 parity cells per byte, is implemented with extended test features (Figure 1). Since most of endurance and data retention failures in a thin-oxide floating-gate EEPROM are caused by random defects in tunnel oxide, which can be corrected by the ECC scheme if not multiple in a byte, reliability of the EEPROM is drastically improved by the ECC scheme when the chip is properly tested. Parity code generator, core array data bits, and core array parity bits can be tested in separated modes. This separated testing is essential to production of highly reliable EEPROM and to direct evaluation of ECC impact an the chip reliability and yield. In the parity code check mode ( H 1 high), the parity generator is tested in a read speed by forming a closedloop circuit consisted of data-in buffer, parity code generator, and data-out buffer, as shown in dash lines in Figure 1. In this mode, when OE is low, input data is latched at the data-in buffer and corresponding parity code can be read from the data-out buffer. In the ECC disable made (H3 high), core array data bits are checked without correction, whereas core array parity bits are tested in the parity bit check mode (H2 high). Threshold voltage of each cell in the core array, used for precise monitoring of charge retention characteristic, is measured by excecuting a read cycle with external voltage applied to the cell control-gate line (Figure 2 ) . The external voltage is applied through pass transistors, the gates of which are connected to output of a high voltage follower circuit shown in Figure 3. Since the output of the high voltage follower circuit is grounded when input voltage is lower than the trip voltage, which is always about 3 Vt above Vcc, this threshold measurement scheme does not affect normal operation. In the threshold measurement mode, however, external voltage higher than Vcc can be transfer to the control-gate line by applying high voltage to the input of the foll

本文将描述一个32K x 8 CMOS EEPROM与片上ECC(错误检查和校正)。将描述能够有效测试片上ECC电路和单元阈值电压的测试功能。一种新颖的电可编程保险丝电路提供可靠的实现冗余和可编程的可选功能。具有64字节页面写入模式的5V全功能[I]， [2] EEPROM具有额外的测试功能，例如ECC禁用，写入周期和程序电压(Vpp)斜坡速度控制以及写入抑制Vcc水平调整。采用双聚、单金属n阱CMOS技术和薄通道氧化物(< I O O O A O)浮栅单元构建EEPROM。最小特征尺寸1。2微米用于实现60微米的电池尺寸和68毫米的芯片尺寸。350A’复合内插介质用于提供增强的小区数据保留特性。采用双离子注入形成的梯度结来提高击穿电压。一种改进的汉明码ECC方案，每字节有4个奇偶校验单元，实现了扩展的测试功能(图1)。由于薄氧化物浮动门EEPROM的大多数耐久性和数据保留故障是由隧道氧化物中的随机缺陷引起的，如果不是在一个字节中多个，则可以通过ECC方案进行纠正，当芯片经过适当测试时，ECC方案大大提高了EEPROM的可靠性。奇偶校验码生成器，核心阵列数据位，和核心阵列奇偶校验位可以在分离的模式下进行测试。这种分离测试对于生产高可靠性EEPROM和直接评估ECC对芯片可靠性和成品率的影响至关重要。在奇偶码校验模式(h1高)下，通过组成一个由数据输入缓冲区、奇偶码生成器和数据输出缓冲区组成的闭环电路，以读速度测试奇偶码生成器，如图1虚线所示。在这种模式下，当OE较低时，输入数据被锁存于数据输入缓冲区，相应的奇偶校验码可以从数据输出缓冲区中读取。在ECC disable (H3 high)下，对核心阵列数据位进行校验而不进行校正，而对核心阵列奇偶校验模式(H2 high)下进行奇偶校验。核心阵列中每个电池的阈值电压用于精确监测电荷保持特性，通过在电池控制门线上施加外部电压执行读取周期来测量(图2)。外部电压通过通型晶体管施加，通型晶体管的门连接到图3所示的高压跟随电路的输出。由于输入电压低于脱扣电压时，高压从动电路输出接地，脱扣电压始终高于Vcc约3vt，因此该阈值测量方案不影响正常工作。然而，在阈值测量模式下，可以通过向跟随电路的输入端施加高压，将高于Vcc的外部电压转移到控制门线。图4显示了一种新型的可编程和可擦除保险丝电路。四单元桥接结构大大提高了熔断器元件的可靠性，因为熔断器元件可以容忍其6个单元中的单个单元故障。这种可靠的保险丝元件用于冗余修复，用于用户模式，如软件数据保护状态和ECC禁用状态的非易失性存储，以及测试模式，包括Vpp斜坡速度控制，写周期时间控制和写抑制Vcc水平调整。读取路径设计的重点是Vcc和温度裕度，对dildt的最小化，以及对电池电荷损失的免疫。在读取操作期间将细胞控制门线电位设置为细胞初始阈值电压(0.8 v)，可提供EEPROM对细胞电荷损失或增益的固有免疫力。通过在数据输出缓冲器中使用耗尽晶体管，可以在高Vcc角处最小化地弹跳噪声，而在低Vcc角处没有速度损失(图5)。输出驱动器栅极节点的上升时间对Vcc变化不敏感，因为它是由耗尽晶体管的饱和电流控制的。256K EEPROM的照片如图6所示。室温下5V时的读周期波形如图7所示。

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引用次数: 3

GHz band high gain GaAs monolithic amplifiers using parallel feedback technique 采用并行反馈技术的GHz频段高增益GaAs单片放大器

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037400

N. Ishihara, H. Kikuchi, M. Ohara

引用次数: 1

8ns 64K BiCMOS SRAM's 8ns 64K BiCMOS SRAM

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037405

H. Miwa, K. Tsuruoka, K. Yamauchi, H. Endoh, M. Odaka, Y. Saito

INTRODUCTION S ince Bi-CMOS technology employs h ighd r i v a b i l i t y g a t e c i r c u i t s and h i g h s e n s i t i v i t y Sense c i r c u i t s , h i g h e r speed memory c i r c u i t s than t h o s e through CMOS p r o c e s s technology can b e ach ieved . This paper d e s c r i b e s 64K TTL SRAM d e s i g n us ing 1 . 3 u m Hi-BiCMOS technology. A 16Kw x 4b o r 64Kw x Ib RAM i s c o n f i g u r a b l e by changing t h e w i r i n g l a y e r c o n f i g u r a t i o n . I n t h i s R A M , t he c u r r e n t source c i r c u i t i s s t a b i l i z e d a g a i n s t power-supply v o l t a g e Vcc and t empera tu re so t h a t i n c r e a s e i n a c c e s s t ime a s we l l a s i n power consumption under t h e wors t c o n d i t i o n s a r e minimized. The a d d r e s s a c c e s s time of t h e RAM i s 8 .0 ns and t h e a c t i v e c u r r e n t i s 45 mA under the c o n d i t i o n s of Vcc=5.0 V , Ta=25"C, and 50 M H r .

引言由于 Bi-CMOS 技术采用了高速存储器和高速传感存储器，因此可以实现比 CMOS p r o c e s s 技术更快的存储器速度。本文利用 1 .3 u m Hi-BiCMOS 技术。16Kw x 4b 或 64Kw x Ib RAM 可通过改变存储容量来实现。在这种 R A M 中，c u r r e n t c i r c u i t i s t a b i l i z e d a g a i n s t power-supply v o l t a g e Vcc and t empera tu re so so t h a t i n c r e a s e i n a c c e s time a s we l l a s i n power consumption under t h e wors t c o n d i t i o n s a r e minimized.在 Vcc=5.0 V、Ta=25 "C 和 50 M H r 的条件下，RAM 的启动时间为 8.0 ns，功耗为 45 mA。

引用次数: 0

A 1024-channel time switch LSI with an operating frequency of 50MHz 一个工作频率为50MHz的1024通道时间开关LSI

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037447

K. Aoyama, K. Narita, S. Karafuji, K. Nagai, K. Matsumoto

引用次数: 2

Bipolar scaling for BiCMOS circuits BiCMOS电路的双极标度

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037426

G. P. Rosseel, R. Dutton

引用次数: 5

New DRAM noise generation under half Vcc precharge and its reduction using a transposed amplifier 半Vcc预充条件下的新型DRAM噪声产生及其用转置放大器的降低

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037432

S. Ienaga, M. Aoki, Y. Nakagome, M. Horiguchi, Y. Kawase, Y. Kawamoto, K. Itoh

引用次数: 7

A programmable SLIC consisting of both SCF and DSP technologies with 30dB return loss characteristics 具有30dB回波损耗特性的可编程SLIC，由SCF和DSP技术组成

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037446

T. Okamoto, J. Hirakawa, S. Morisaki, Y. Kurose, M. Takeda, K. Shiraki

引用次数: 0

Neural networks and expectation of VLSI implementation 神经网络和VLSI实现的期望

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037406

M. Kawato, S. Miyake, T. Inui

2.1 Transformation Neural Network Computational neuroscience and its application to The most fundamental motivation for exploring neuengineering “neurocomputing” have been a subject ral networks as a guide to future information processof great interest for the past several years. Research ing machines comes from the fact that we do have of neurocomputing is expected to lead to developits most fascinating realization as the human brain. ment of massively parallel network systems based Neural networks have at least two remarkable charon neural network models: neurocompufer. There acteristics in contrast with the present von Neumann seems to be several reasons for the recent resurgence type computer. First it h a s the capability of learning of interest in neural network as an information prowith use of plastic changes of synaptic connections cessing machine. (i) Improvement of computer fabetween its computing elements neurons. Second it cility as a tool for simulating neural network modsolves computational problems by cooperative operels. (ii) Increasing feasibility of hardware implemenation of great number of neurons (10” in-the brain). tation of neural network models by analogue VLSI [1,2,3], optoelectronic devices [4] etc. (iii) Steady deAccording to the above two features, many Of the velopment of experimental neuroscience. (iV) connetwork models, which were proposed t o account for sidetable amount of fundamental principles and neubrain functions such pattern recognition or memral network models accumulated during past 25 years ory in a somewhat abstract can be classiresearch of biological information processing. (v) AI fied into the two The research, which aims at the similar intelligence as huis called as “transformation” neural network model

在过去的几年里，探索神经工程“神经计算”的最基本动机一直是一个主题，即网络作为未来信息处理的指南。对机器的研究来自于这样一个事实，即我们确实拥有神经计算，它有望引领人类大脑最迷人的发展。基于大规模并行网络系统的神经网络至少有两种显著的charon神经网络模型:神经计算机。与目前的冯·诺伊曼的特点相比，似乎有几个原因使最近的计算机类型死而复生。首先，利用突触连接处理机的可塑性变化，研究神经网络作为信息证明的兴趣学习能力。(i)计算机计算元素神经元之间的性能改进。其次，它作为一种模拟神经网络模型的工具，通过协同操作来解决计算问题。(ii)增加大量神经元(大脑中10英寸)硬件实现的可行性。通过模拟VLSI[1,2,3]、光电器件[4]等建立神经网络模型。(三)稳定分解根据以上两个特点，许多实验神经科学得以发展。(四)连接模型(connetwork models)是生物信息处理的分类研究，在过去的25年里，模式识别或记忆网络模型等神经系统的基本原理和功能在一定程度上是抽象的。(5)人工智能(AI)与人工智能(AI)相结合的研究，其目标是与人工智能相似的智能，被称为“转换”神经网络模型

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引用次数: 1

A new nibbled-page architecture for high density DRAMs 一种用于高密度dram的新型咬页架构

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037429

K. Numata, Y. Oowaki, Y. Itah, T. Hara, H. Tsuchida, T. Kobavashi, M. Ohta, S. Watanabe, K. Ohuchi

引用次数: 1

A CMOS nondifferential static sampling sense amplifier 一种CMOS非差分静态采样感测放大器

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037449

V. Pinto, R. Marko, E. Cohen, J. Levy, L. Lev

引用次数: 0

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