Symposium 1988 on VLSI Circuits最新文献

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Pipelined parallel bidirectional shift (PPB) architecture for high speed serial access 用于高速串行访问的流水线并行双向移位(PPB)架构

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037437

Y. Norooka, T. Kobayashi, K. Yasuda, M. Yanada

引用次数: 0

A new pipelined-subranging 8 bit 20MHz CMOS AD converter 一种新型流水线分程8位20MHz CMOS模数转换器

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037456

K. Tsuji, S. Saitoh, S. Morinaga, T. Iida

引用次数: 4

Improvement of soft error rate in MOS SRAMs MOS固态存储器软错误率的改进

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037422

S. Murakami, K. Ichinose, K. Anami, S. Kayano

I n t r o d u c t i o n Recently, the access time of VLSI CMOS SRAMS’.’.~ has come to the level of ECL RAMs. The a-particle induced soft error ia the SRAMs with high resistive load cell has been a serious problem, b c cause the soft error rate (SER) abruptly increases at the short cycle time ‘.‘. Although the SER is reduced by the increme of the capacitance in storage nodes, the scaled amnll cell area limits the increase of the capacitance. This paper proposes two unique improvement techniques with no extra ailicon area, and the SER is improved by 2 orders of magnitude.

近年来，对VLSI CMOS sram的存取时间进行了研究。~已经达到了ECL RAMs的水平。在高阻负载传感器的sram中，a粒子引起的软误差一直是一个严重的问题，因为它会导致软误差率(SER)在短周期内突然增加。虽然SER会随着存储节点中电容的增加而降低，但缩小的小单元面积限制了电容的增加。本文提出了两种独特的改进技术，在不增加额外的ailicon面积的情况下，将SER提高了2个数量级。

引用次数: 2

1.5um CMOS gate arrays with analog/digital macros designed using the common base arrays 采用通用基阵设计的带模拟/数字宏的1.5um CMOS门阵列

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037424

S. Kawada, Y. Hara, T. Isono, T. Inuzuka

Mixed analog and digital circuits are realized on a single chip of 1.5um rule, single t5V power supplied, si.licon gate, and 320 through 19600 cells CMOS digital gate arrays without any extension of turn-around time and any restriction of designing. Voltage comparator with input offset voltage of lOmV MAX. and response time of 60nsec. D/A converters and A/D converters with 4 bit, 6 bit, 8 bit respectively, and an analog switch with 250hm on-resistance can exist simultaneously with digital circuits. Using this technology, about 1/10 of turnaround time on system developments compared with full-custom LSIs can be achieved. INTRODUCTION I t is desired eagerly in the semi-custom LSI field to integrate a system on a single chip by establishing a mixture of analog and digital technologies. Up to this time, there are a few ways to create mixed analog and digital circuits; i.e., full-custom LSIs, standard cells, masterslice LSIs which have more than 2 channel length transistors for analog circuit parts and digital circuit parts. or gate array of which all base transistor arrays are long channel length type [ I ] , t21. Each of them have several weak points, for example long turn-around time, high development Cost, restriction of the ratio between analog circuit parts and digital circuit parts, very Poor digital circuit's performance, and so on. STRUCTURES Analog function blocks are produced on base transistor arrays of commonly used 1.5um rule, single +5V power.supplied, and silicon gate CMOS digital gate array series. This gate array series contains 16 masters with 320 through 19600 cells. Figure 1 shows a microphotograph of a chip including analog function blocks. All of analog circuits can be placed anywhere on the base transistor arrays with only a few consideration (ex. cross talk. noise etc.) like digital circuits. These analog function blocks are registered as hardware macros in function block libraries. PRODUCTS DEVELOPMENT FLOW Gate arrays including analog circuits are developed according to the flow chart shown in Figure 2 . Just the same development flow and CAD tools of designing gate arrays with only digital circuits are used. In case of circuit simulation, analog function blocks are treated as black boxes. And only connections between analog function blocks and other blocks are checked. In this way, the turn-around time from the end o f the circuit simulation to the supply of engineering sample of mixed analog and digital circuits is reduced to about 1/10 compared with fullcustom LSIs. VOLTAGE COUPARAT ORS short channel length unit transistors such as: Wp/Lp = 33um/1.8um All analog circuits are constructed with WN/LN = 33um/1.6um, Figure 3 shows one of the comparator's layout pattern. Input transistors of differential Stage uses two unit transistors each, and they are placed cross coupled with each other. And power supply wires are also placed equally for the input pair transistors. The comparator's layout is made under such consideration, a

模拟和数字混合电路在1.5um规则，单t5V电源，si芯片上实现。和320到19600单元CMOS数字门阵列，不延长周转时间和设计上的任何限制。输入偏置电压为lOmV MAX的电压比较器。响应时间为60nsec。分别为4位、6位、8位的D/A转换器和A/D转换器，导通电阻250hm的模拟开关可以与数字电路同时存在。使用这种技术，与完全定制的lsi相比，系统开发的周转时间可以缩短1/10。在半定制LSI领域，迫切需要通过建立模拟和数字技术的混合来将系统集成到单个芯片上。到目前为止，有几种方法可以创建混合模拟和数字电路;即，全定制lsi，标准单元，具有超过2通道长度晶体管的主片lsi，用于模拟电路部件和数字电路部件。或所有基极晶体管阵列均为长通道长度型的门阵列[I]， t21。它们都存在着周期长、开发成本高、模拟电路与数字电路比例受限、数字电路性能很差等缺点。模拟功能块是在常用的1.5um规则的基极晶体管阵列上生产的，单电源+5V。提供，和硅门CMOS数字门阵列系列。该门阵列系列包含16个主控单元，有320到19600个单元。图1显示了包含模拟功能块的芯片的显微照片。所有的模拟电路都可以放置在基本晶体管阵列的任何地方，只需要考虑一些问题(例如串扰)。噪声等)像数字电路。这些模拟函数块在函数块库中被注册为硬件宏。包括模拟电路在内的门阵列是根据图2所示的流程图开发的。仅使用数字电路设计门阵列的开发流程和CAD工具。在电路仿真中，模拟功能块被视为黑盒子。并且只检查模拟功能模块与其他模块之间的连接。这样，与全定制lsi相比，从电路仿真结束到提供混合模拟和数字电路的工程样本的周转时间减少到约1/10。电压耦合器或短通道长度单位晶体管，如:Wp/Lp = 33um/1.8um所有模拟电路均以WN/LN = 33um/1.6um构建，图3显示了比较器的布局图之一。差动级输入晶体管各采用两个单位晶体管，并交叉耦合放置。输入对晶体管的电源线也同样放置。比较器的布局是在这样的考虑下进行的，因此，输入偏置电压在g 0 m V MAX以内。，响应时间为60nsec TYP。比较器输入偏置电压的分布如图4所示。

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引用次数: 0

Fast converging analog adaptive filter for general purpose noise canceller 用于通用降噪的快速收敛模拟自适应滤波器

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037441

T. Ritoniemi, T. Karema, H. Tenhunen

引用次数: 4

16Mb ROM design using bank select architecture 使用银行选择架构的16Mb ROM设计

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037435

M. Okada, Y. Hotta, R. Matsuyama, Y. Surninaga, J. Tanimoto, K. Nakahara, M. Takahi, H. Korniya, T. Ashida, K. Sane, A. Kunikane, R. Miyake

Market nee& for high density and shorter t u n around time (TAT) mask programmable ROM's I mask ROM's ) have increased rapidly due to the demand for storing the Kanji charseter fonts and dictionaries used in Japanese word pmcesso~s and storing the mftwere used in TV games. We have realized a mask ROM canfiguration which ratisfie. requirements far bath high density and shorter TAT by employing a new ROM cell I Flat cell I Structure and a bank Selection technique. This paper describes B high density 16M bi t inask ROM configuralion ( a block diagram is shown in F ig .1 I . As a type nf redundancy technique , a new concept of bypass technique for non-programmed ROM areas is described . A testability design named H V parity matrix teat-mode design is also described.

市场对高密度和短周期(TAT)掩码可编程ROM (I掩码ROM)的需求迅速增加，这是由于存储日语单词处理器中使用的汉字字符字体和字典以及存储电视游戏中使用的mft的需求。我们实现了一个令人满意的掩码ROM配置。通过采用新的ROM单元I、平面单元I结构和银行选择技术，要求远密度和更短的TAT。本文描述了B高密度16M字节inask ROM配置(框图如图1.1所示)。作为一种nf冗余技术，本文提出了一种非编程ROM区旁路技术的新概念。本文还介绍了一种可测试性设计——hv奇偶矩阵模态设计。

引用次数: 7

High-density quaternary logic array chip for knowledge information processing systeks 用于知识信息处理系统的高密度四元逻辑阵列芯片

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037408

T. Hanyu, T. Higuchi

instance, production systemshave been observed to spend more than nine-tenths of its total run time performing the pattern matching. The knowledge information processing system requires high computational power and large memory capacity at low cost to make many kinds of real-time applications possible [ 1 I . This paper presents a new high-density quaternary logic array chip for high-speed pattern matching instead of depending on expensive and time-consuming software systems 121. A double pattern matching algorithm can be effectively employed for achieving greater densities on smaller semiconductor chips. The appropriate quaternary encoding for the contents of B working memory and a production memory can perform a double pattern matching. Four states for two-bit information concerning with two elements of a rule can be stored into a pattern matching cell using multiple ion implant technique which makes the threshold of the transistor programmable [ 3 ] , A9 a result, the pattern matching cell can be implemented by using only a single transistor. The number. of cells and transistors in the proposed logic array are reduced to 50% of the corresponding binary implementation. Moreover, the pattern matching operations can be performed in parallel, so that the processing time on each reasoning cycle can be provided by the propagation delay time of a single transistor. information processing system interpreters. For

例如，已经观察到生产系统花费超过其总运行时间的十分之九来执行模式匹配。知识信息处理系统需要高计算能力和低成本的大存储容量，才能使多种实时应用成为可能[1]。本文提出了一种新的高密度四元逻辑阵列芯片，用于高速模式匹配，而不是依赖于昂贵和耗时的软件系统。双模式匹配算法可以有效地用于在更小的半导体芯片上实现更大的密度。对B工作存储器和生产存储器的内容进行适当的四进制编码可以执行双模式匹配。利用多离子植入技术，可以将与规则的两个元素相关的两位信息的四种状态存储到模式匹配单元中，使晶体管的阈值可编程[3]，因此，模式匹配单元可以仅使用单个晶体管实现。这个号码。所提出的逻辑阵列中的单元和晶体管的数量减少到相应二进制实现的50%。此外，模式匹配操作可以并行执行，因此每个推理周期的处理时间可以由单个晶体管的传播延迟时间提供。信息处理系统解释器。为

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引用次数: 3

A multiplying encoder for digital signal processing 用于数字信号处理的乘法编码器

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037443

K. Okada, S. Takeuchi, M. Kimura, T. Kumamoto, N. Yazawa

引用次数: 1

A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM 一个0.1/spl mu/A待机电流，抗弹跳噪声1Mb SRAM

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037418

M. Ando, T. Okazawa, H. Furuta, M. Ohkaaa, J. Monden, N. Kodama, K. Are, H. Ishihara, I. Sasaki

I) Introduction Recentlv. lhlb SRAMs with nolvsilicon load resistor cell have been r e p ~ r t e d l , ~ , ~ , ~ . But i t becomes difficult to reduce standby current less than ILIA, because of data retention problem and process difficulty of high resistivity polysilicon formation. This paper describes a 1Mb SRAM with a standby current of O.IpA, employing, as cell load devices, p-channel polysilicon transistors with offset gate-drain structure, stacked on n-channel driver transistors5. The SRAM also employed an optimal sensitivity-control scheme of clock generators, immune to VCCIGND voltagebouncing noises which induce serious problem in a byte-wide RAM with an address transition, det,ector. The circuit scheme widened input voltage margins by 0.2V.

(一)简介采用无硅负载电阻单元的lhlb sram已被广泛地应用于~，~，~，~。但由于数据保留问题和高电阻多晶硅形成的工艺难度，使待机电流减小到低于ILIA变得困难。本文描述了一种待机电流为0.ipa的1Mb SRAM，它采用偏置栅漏结构的p沟道多晶硅晶体管堆叠在n沟道驱动晶体管上作为单元负载器件。SRAM还采用了时钟发生器的最佳灵敏度控制方案，避免了VCCIGND电压弹跳噪声的影响，这种噪声在具有地址转换、检测器和矢量的字节级RAM中会引起严重的问题。该电路方案将输入电压裕度加宽0.2V。

引用次数: 16

Mixed-mode simulation and verification: status and future 混合模式仿真与验证:现状与未来

Symposium 1988 on VLSI Circuits

Pub Date : 1900-01-01 DOI: 10.1109/VLSIC.1988.1037423

D. Smith

引用次数: 0

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