Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616911
M. Gharib, A. Abrishamifar
This paper describes a dual-loop DLL architecture with linear delay element in analog loop and a monotonic digitally controlled delay element in its digital loop. The proposed architecture is based on two loops, fine loop and coarse loop which is controlled by peripheral circuits such as FSM (finite state machine) and lock detector circuit. The ADS simulator is used to verify the circuit design. All of simulations are based upon 0.18 mum CMOS technology at 1.8 V power supply voltage. The simulation results show that the proposed DLL has wide-range operation from 200 to 400 MHz and low-power dissipation and low-jitter performance. Moreover, the rms jitter is as low as 20 ps and the power dissipation is as low as 4.5 mW over the operating frequency range.
本文介绍了一种双环动态链接库结构，在模拟环中采用线性延迟元件，在数字环中采用单调数字控制延迟元件。该结构基于粗、细两环，由有限状态机(FSM)和锁检电路等外围电路控制。利用ADS模拟器对电路设计进行了验证。所有仿真均基于1.8 V电源电压下的0.18 μ m CMOS技术。仿真结果表明，该DLL具有200 ~ 400 MHz宽工作范围、低功耗、低抖动等特点。此外，在工作频率范围内，rms抖动低至20ps，功耗低至4.5 mW。
{"title":"A novel low-power and high-performance dual-loop DLL with linear delay element","authors":"M. Gharib, A. Abrishamifar","doi":"10.1109/MWSCAS.2008.4616911","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616911","url":null,"abstract":"This paper describes a dual-loop DLL architecture with linear delay element in analog loop and a monotonic digitally controlled delay element in its digital loop. The proposed architecture is based on two loops, fine loop and coarse loop which is controlled by peripheral circuits such as FSM (finite state machine) and lock detector circuit. The ADS simulator is used to verify the circuit design. All of simulations are based upon 0.18 mum CMOS technology at 1.8 V power supply voltage. The simulation results show that the proposed DLL has wide-range operation from 200 to 400 MHz and low-power dissipation and low-jitter performance. Moreover, the rms jitter is as low as 20 ps and the power dissipation is as low as 4.5 mW over the operating frequency range.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126919436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616769
Shizhong Mei
Rigorous math is provided in this paper to obtain the transfer function of a charge pump phase locked loop (CPLL). The math clearly explains when and how the impulse invariant transform based method works and corrects its errors in some cases. The loop transfer function is then used for loop stability evaluation and jitter calculation. It is shown that the loop stability can be improved by increasing loop gain and loop delay, revealing a counterintuitive application of loop delay, i.e., a loop delay can be used to speed up phase locking process. As for the jitter calculation, a closed form expression is derived to predict the output jitter due to deterministic input noise.
{"title":"Analysis of charge pump phase locked loop in the presence of loop delay and deterministic noise","authors":"Shizhong Mei","doi":"10.1109/MWSCAS.2008.4616769","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616769","url":null,"abstract":"Rigorous math is provided in this paper to obtain the transfer function of a charge pump phase locked loop (CPLL). The math clearly explains when and how the impulse invariant transform based method works and corrects its errors in some cases. The loop transfer function is then used for loop stability evaluation and jitter calculation. It is shown that the loop stability can be improved by increasing loop gain and loop delay, revealing a counterintuitive application of loop delay, i.e., a loop delay can be used to speed up phase locking process. As for the jitter calculation, a closed form expression is derived to predict the output jitter due to deterministic input noise.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123369636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616905
Chin-Ying Chen, J. Ho, W. Liou, R. Hsiao
A 5-GHz CMOS fractional-N frequency synthesizer with a delta-sigma modulator is designed in this paper. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. In consideration of low power consumption, we use an injection-locked frequency divider as the first stage prescaler. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of-116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18-mum CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27 KHz and the locking time is 8 mus.
{"title":"A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator","authors":"Chin-Ying Chen, J. Ho, W. Liou, R. Hsiao","doi":"10.1109/MWSCAS.2008.4616905","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616905","url":null,"abstract":"A 5-GHz CMOS fractional-N frequency synthesizer with a delta-sigma modulator is designed in this paper. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. In consideration of low power consumption, we use an injection-locked frequency divider as the first stage prescaler. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of-116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18-mum CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27 KHz and the locking time is 8 mus.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126338018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616933
T. Hinamoto, T. Oumi, O. I. Omoifo, Wu-Sheng Lu
The minimization problem of frequency-weighted l2-sensitivity subject to l2-scaling constraints is formulated for two-dimensional (2-D) state-space digital filters described by the Roesser model. It is shown that the Fornasini-Marchesini second model can be readily imbedded in the Roesser model. An iterative method is developed to solve the constrained optimization problem. This method converts the problem into an unconstrained optimization formulation by using linear-algebraic techniques and solves it by applying an efficient quasi-Newton algorithm. A case study is presented to illustrate the utility of the proposed technique.
{"title":"Two-dimensional state-space digital filters with minimum frequency-weighted l2-sensitivity under l2-scaling constraints","authors":"T. Hinamoto, T. Oumi, O. I. Omoifo, Wu-Sheng Lu","doi":"10.1109/MWSCAS.2008.4616933","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616933","url":null,"abstract":"The minimization problem of frequency-weighted l2-sensitivity subject to l2-scaling constraints is formulated for two-dimensional (2-D) state-space digital filters described by the Roesser model. It is shown that the Fornasini-Marchesini second model can be readily imbedded in the Roesser model. An iterative method is developed to solve the constrained optimization problem. This method converts the problem into an unconstrained optimization formulation by using linear-algebraic techniques and solves it by applying an efficient quasi-Newton algorithm. A case study is presented to illustrate the utility of the proposed technique.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122452398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616759
C. Radhakrishnan, W. Jenkins
Previously it has been shown that an FFT-based transform domain adaptive filter (FTAF) operating on real-valued signals can achieve a remarkable degree of fault tolerant performance based on parameter redundancy inherent in the complex arithmetic. In this paper the use of the Walsh-Hadamard transform is considered as a computationally efficient way of achieving fault tolerance. Although the WHT does not provide full fault tolerance it does provide a large degree of fault coverage that may be useful for adaptive filters implemented in highly scaled nano-technology circuits where soft (transient) errors and hard (permanent) faults are of increasing concern.
{"title":"Fault tolerant adaptive filters based on the Walsh-Hadamard transform","authors":"C. Radhakrishnan, W. Jenkins","doi":"10.1109/MWSCAS.2008.4616759","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616759","url":null,"abstract":"Previously it has been shown that an FFT-based transform domain adaptive filter (FTAF) operating on real-valued signals can achieve a remarkable degree of fault tolerant performance based on parameter redundancy inherent in the complex arithmetic. In this paper the use of the Walsh-Hadamard transform is considered as a computationally efficient way of achieving fault tolerance. Although the WHT does not provide full fault tolerance it does provide a large degree of fault coverage that may be useful for adaptive filters implemented in highly scaled nano-technology circuits where soft (transient) errors and hard (permanent) faults are of increasing concern.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122947882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616747
Rui He, Lihong Zhang
With the breathtaking advance of technology, the modern analog/mixed-signal design needs to consider the requirements of low voltage/power and the effects of the MOSFET channel length shrinking. Although a few different schemes have been proposed, the bulk-driven technique, which uses bulk terminal (the fourth terminal of a MOSFET) for signal input, is a promising solution to the low-voltage and low-power applications. However, the conventional MOSFET models are normally set up for the typical gate-driven applications (i.e., using gate terminal for signal input). Besides, due to shrinking MOSFET channels, those MOSFET models may not perform correctly and accurately for the bulk-driven applications, especially in the moderate inversion region. In this paper, we evaluate two MOSFET models including BSIM3V3 and EKV for the bulk-driven applications in a sub-micron CMOS technology. BSIM3V3 is a widely used model in the semiconductor industry, while the EKV model is suitable for the small-channel-length simulation. We focus on several critical MOSFET parameters for bulk-driven application and conduct thorough experiments using the two aforementioned models. The simulation results are analyzed to demonstrate the advantages of the bulk-driven technique compared to the gate-driven scheme in the low-voltage/low-power applications. Finally the performance of the two MOSFET models in the bulk-driven applications is summarized.
{"title":"Evaluation of modern MOSFET models for bulk-driven applications","authors":"Rui He, Lihong Zhang","doi":"10.1109/MWSCAS.2008.4616747","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616747","url":null,"abstract":"With the breathtaking advance of technology, the modern analog/mixed-signal design needs to consider the requirements of low voltage/power and the effects of the MOSFET channel length shrinking. Although a few different schemes have been proposed, the bulk-driven technique, which uses bulk terminal (the fourth terminal of a MOSFET) for signal input, is a promising solution to the low-voltage and low-power applications. However, the conventional MOSFET models are normally set up for the typical gate-driven applications (i.e., using gate terminal for signal input). Besides, due to shrinking MOSFET channels, those MOSFET models may not perform correctly and accurately for the bulk-driven applications, especially in the moderate inversion region. In this paper, we evaluate two MOSFET models including BSIM3V3 and EKV for the bulk-driven applications in a sub-micron CMOS technology. BSIM3V3 is a widely used model in the semiconductor industry, while the EKV model is suitable for the small-channel-length simulation. We focus on several critical MOSFET parameters for bulk-driven application and conduct thorough experiments using the two aforementioned models. The simulation results are analyzed to demonstrate the advantages of the bulk-driven technique compared to the gate-driven scheme in the low-voltage/low-power applications. Finally the performance of the two MOSFET models in the bulk-driven applications is summarized.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"43 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120975944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616854
Zuoliang Ning, B. Blalock, E.M. Nance, J. Oliver, R. Van Berg, P. O'connor, C. Britton
A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescopepsilas CCD imagers. The prototype chip has been fabricated in a 0.8-mum BCD-SOI process, and is designed to operate down to 150 K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.
{"title":"A high voltage CCD Sensor Control Chip for the Large Synoptic Survey Telescope (LSST)","authors":"Zuoliang Ning, B. Blalock, E.M. Nance, J. Oliver, R. Van Berg, P. O'connor, C. Britton","doi":"10.1109/MWSCAS.2008.4616854","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616854","url":null,"abstract":"A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescopepsilas CCD imagers. The prototype chip has been fabricated in a 0.8-mum BCD-SOI process, and is designed to operate down to 150 K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121081108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616941
J. Teller, F. Ozguner, R. Ewing
Our research addresses the need to efficiently execute and control the increasingly demanding and diverse nature of applications running on embedded systems. We propose optimizing an application at runtime, sharing execution resources between the runtime optimizations and the application. We use the TRIPS processor (developed by the University of Texas at Austin) to demonstrate runtime optimization using speculative slice execution on a nanoprocessor architecture (NA). Preliminary results are promising. Despite the current implementations limitations, we show speedups of 7%/25% (whole application/single task), with larger speedups are possible for future implementations.
{"title":"Optimization at runtime on a nanoprocessor architecture","authors":"J. Teller, F. Ozguner, R. Ewing","doi":"10.1109/MWSCAS.2008.4616941","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616941","url":null,"abstract":"Our research addresses the need to efficiently execute and control the increasingly demanding and diverse nature of applications running on embedded systems. We propose optimizing an application at runtime, sharing execution resources between the runtime optimizations and the application. We use the TRIPS processor (developed by the University of Texas at Austin) to demonstrate runtime optimization using speculative slice execution on a nanoprocessor architecture (NA). Preliminary results are promising. Despite the current implementations limitations, we show speedups of 7%/25% (whole application/single task), with larger speedups are possible for future implementations.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616797
C. Cruz, R. Reyes, M. Nakano, H. Pérez
In this paper, an image content authentication algorithm based on semi-fragile watermarking is proposed. In the proposed approach, the robust digital signature which is extracted from the image is embedded into the image as a watermark signal. The embedding process is performed using Vector Quantization method in the Discrete Wavelet Transform domain, while the watermark extraction process is performed using a blind scheme, where the original image is not required. The proposed algorithm is applied to gray-scale and color images. The experimental results show that the proposed technique detects the photomontage region of the images a false positive error of about 10%, while the technique tolerates any modification which preserves image contents such as: JPEG compression and noise contamination. The proposed algorithm is compared with another authentication method to show desirable performance of the proposed one.
{"title":"Image content authentication system based on semi-fragile watermarking","authors":"C. Cruz, R. Reyes, M. Nakano, H. Pérez","doi":"10.1109/MWSCAS.2008.4616797","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616797","url":null,"abstract":"In this paper, an image content authentication algorithm based on semi-fragile watermarking is proposed. In the proposed approach, the robust digital signature which is extracted from the image is embedded into the image as a watermark signal. The embedding process is performed using Vector Quantization method in the Discrete Wavelet Transform domain, while the watermark extraction process is performed using a blind scheme, where the original image is not required. The proposed algorithm is applied to gray-scale and color images. The experimental results show that the proposed technique detects the photomontage region of the images a false positive error of about 10%, while the technique tolerates any modification which preserves image contents such as: JPEG compression and noise contamination. The proposed algorithm is compared with another authentication method to show desirable performance of the proposed one.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122403049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616871
R. Ewing, H. Abdel-Aty-Zohdy, M.C. Hollenbeck, K. Stevens
Fractional-order systems have applications in the areas of flight control, robotics, missile guidance, control of structural vibrations of space platforms and sensor technology. Fractional-order transfer functions can characterize complex nonlinear dynamics with many fewer parameters than integer-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating fractional-order algorithms for signal processing. The PETpsilas advantage over the conventional RC and RL circuits is that it can be both functionally scaled and varied for dynamic fractional-order parameter controllability.
{"title":"Fractional-order signal processing using a polymer-electrolyte transistor","authors":"R. Ewing, H. Abdel-Aty-Zohdy, M.C. Hollenbeck, K. Stevens","doi":"10.1109/MWSCAS.2008.4616871","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616871","url":null,"abstract":"Fractional-order systems have applications in the areas of flight control, robotics, missile guidance, control of structural vibrations of space platforms and sensor technology. Fractional-order transfer functions can characterize complex nonlinear dynamics with many fewer parameters than integer-order functions. This paper addresses the use of a polymer-electrolyte transistor (PET) for use in implementating fractional-order algorithms for signal processing. The PETpsilas advantage over the conventional RC and RL circuits is that it can be both functionally scaled and varied for dynamic fractional-order parameter controllability.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132926163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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