Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616836
C. Noeske, M. Ortmanns, Y. Manoli
Dynamic-element-matching (DEM) techniques are used to reduce distortions in multi-bit digital-to-analog-converters (DACs), which occur due to the static level mismatch of the switching elements. The common design strategy of established DEM algorithms is to shape the produced mismatch error signal by targeting a uniform usage of the DAC switching elements. In this paper a novel DEM technique is presented, which derives data dependent error signals for each element and shapes their spectra by using delta-sigma modulation techniques. Since the derived data dependent error signals are precisely proportional to the real error signals also for large sample values, this element error shaping DEM algorithm (EES-DEM) is well suited to deal with signals with DC-content and large amplitudes.
{"title":"A dynamic-Element-Matching architecture using individual element error shaping","authors":"C. Noeske, M. Ortmanns, Y. Manoli","doi":"10.1109/MWSCAS.2008.4616836","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616836","url":null,"abstract":"Dynamic-element-matching (DEM) techniques are used to reduce distortions in multi-bit digital-to-analog-converters (DACs), which occur due to the static level mismatch of the switching elements. The common design strategy of established DEM algorithms is to shape the produced mismatch error signal by targeting a uniform usage of the DAC switching elements. In this paper a novel DEM technique is presented, which derives data dependent error signals for each element and shapes their spectra by using delta-sigma modulation techniques. Since the derived data dependent error signals are precisely proportional to the real error signals also for large sample values, this element error shaping DEM algorithm (EES-DEM) is well suited to deal with signals with DC-content and large amplitudes.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123598708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616790
E. Lopez-Gaudana, P. Betancourt, E. Cruz, M. Nakano-Miyatake, H. Perez-Meana
This paper presents a hybrid active noise cancelling (ANC) system, to overcome the acoustic feedback present in most feedforward ANC system, together with an on line secondary path estimation scheme. The ANC system provides a suitable solution to two important problems present in most ANC systems. The acoustic feedback is reduced using two FIR adaptive filters with feedforward and feedback configurations, respectively; while the secondary path modeling is carried out using a modification of the on line estimation method proposed by Akhtar. Computer simulation results show that the combination of the feedback and feedforward stages provides a fairly good acoustic feedback cancellation, while the secondary path estimation method performs fairly well, providing both a fairly good noise cancellation performance.
{"title":"A hybrid active noise cancelling with secondary path modeling","authors":"E. Lopez-Gaudana, P. Betancourt, E. Cruz, M. Nakano-Miyatake, H. Perez-Meana","doi":"10.1109/MWSCAS.2008.4616790","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616790","url":null,"abstract":"This paper presents a hybrid active noise cancelling (ANC) system, to overcome the acoustic feedback present in most feedforward ANC system, together with an on line secondary path estimation scheme. The ANC system provides a suitable solution to two important problems present in most ANC systems. The acoustic feedback is reduced using two FIR adaptive filters with feedforward and feedback configurations, respectively; while the secondary path modeling is carried out using a modification of the on line estimation method proposed by Akhtar. Computer simulation results show that the combination of the feedback and feedforward stages provides a fairly good acoustic feedback cancellation, while the secondary path estimation method performs fairly well, providing both a fairly good noise cancellation performance.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123695445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616857
Liangguo Shen, Zushu Yan, Xing Zhang, Yuanfii Zhao, M. Gao
A power-efficient low-voltage buffer is presented. The proposed buffer contains a low-frequency zero generation circuit to perform frequency compensation and a slew-rate enhancement (SRE) circuit to provide large dynamic current for driving the pass device of the low-dropout (LDO) voltage regulator. Whatpsilas more, the proposed buffer, consuming small quiescent current over full load range, can work at low supply voltage, when comparing to conventional voltage buffer. A 1.2-V, 200-mA LDO with the proposed buffer has been designed in a 0.18-mum standard CMOS process. The low-voltage operation ability, high current efficiency and excellent transient response performance can be achieved. With a 1-muF ceramic output capacitor, the overshoot and undershoot of the output voltages are less than 20-mV when the load step changes between 1 and 200-mA in 100 ns, while the current efficiency is up to 99.99% at full-load current.
{"title":"A fast-response low-dropout regulator based on power-efficient low-voltage buffer","authors":"Liangguo Shen, Zushu Yan, Xing Zhang, Yuanfii Zhao, M. Gao","doi":"10.1109/MWSCAS.2008.4616857","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616857","url":null,"abstract":"A power-efficient low-voltage buffer is presented. The proposed buffer contains a low-frequency zero generation circuit to perform frequency compensation and a slew-rate enhancement (SRE) circuit to provide large dynamic current for driving the pass device of the low-dropout (LDO) voltage regulator. Whatpsilas more, the proposed buffer, consuming small quiescent current over full load range, can work at low supply voltage, when comparing to conventional voltage buffer. A 1.2-V, 200-mA LDO with the proposed buffer has been designed in a 0.18-mum standard CMOS process. The low-voltage operation ability, high current efficiency and excellent transient response performance can be achieved. With a 1-muF ceramic output capacitor, the overshoot and undershoot of the output voltages are less than 20-mV when the load step changes between 1 and 200-mA in 100 ns, while the current efficiency is up to 99.99% at full-load current.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117000869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616743
H. Totsukawa, H. Senou, M. Ohmura
A rectilinear Steiner tree is one of the most important problems that are applied to the global routing in LSI and other designs. In this paper, we propose a parallel genetic algorithm in which the 3-D rectilinear Steiner tree with bounded number of bends is obtained by replacing each edge of the given Euclidean spanning tree by the segments which are parallel to the X-axis, the Y-axis, or the Z-axis. In the proposed method, the algorithm can avoid obstacles flexibly by using, at most, three bends to replace one edge of the Euclidean spanning tree. For the fitness value, a linear sum of the wire length and diameter of the rectilinear Steiner tree is used. In the experimental results, it is shown that our parallel genetic algorithm can avoid obstacles, and obtain the 3-D rectilinear Steiner tree with bounded number of bends.
{"title":"A parallel genetic algorithm for 3-D rectilinear Steiner tree with bounded number of bends","authors":"H. Totsukawa, H. Senou, M. Ohmura","doi":"10.1109/MWSCAS.2008.4616743","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616743","url":null,"abstract":"A rectilinear Steiner tree is one of the most important problems that are applied to the global routing in LSI and other designs. In this paper, we propose a parallel genetic algorithm in which the 3-D rectilinear Steiner tree with bounded number of bends is obtained by replacing each edge of the given Euclidean spanning tree by the segments which are parallel to the X-axis, the Y-axis, or the Z-axis. In the proposed method, the algorithm can avoid obstacles flexibly by using, at most, three bends to replace one edge of the Euclidean spanning tree. For the fitness value, a linear sum of the wire length and diameter of the rectilinear Steiner tree is used. In the experimental results, it is shown that our parallel genetic algorithm can avoid obstacles, and obtain the 3-D rectilinear Steiner tree with bounded number of bends.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616876
H. Nejati, Ahmad Beirami, Y. Massoud
Tent map is a discrete-time piecewise-affine I/O characteristic curve, which is used for chaos-based applications, such as true random number generation. However, tent map suffers from the inability to maintain the output state confined to the input range under noise and process variations. In this paper, we propose a modified tent map, which is interchangeable with the tent map for practical applications. In the proposed modified tent map, the confinement problem is solved while maintaining the functionality of the tent map. We also demonstrate simulation results for the circuit implementation of the presented modified tent map for true random number generation.
{"title":"A realizable modified tent map for true random number generation","authors":"H. Nejati, Ahmad Beirami, Y. Massoud","doi":"10.1109/MWSCAS.2008.4616876","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616876","url":null,"abstract":"Tent map is a discrete-time piecewise-affine I/O characteristic curve, which is used for chaos-based applications, such as true random number generation. However, tent map suffers from the inability to maintain the output state confined to the input range under noise and process variations. In this paper, we propose a modified tent map, which is interchangeable with the tent map for practical applications. In the proposed modified tent map, the confinement problem is solved while maintaining the functionality of the tent map. We also demonstrate simulation results for the circuit implementation of the presented modified tent map for true random number generation.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127119603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616765
JunKyu Lee, G. D. Peterson, R. Harrison, R. Hinde
Monte Carlo methods often demand the generation of many random numbers to provide statistically meaningful results. Because generating random numbers is time consuming and error-prone, the Scalable Parallel Random Number Generators (SPRNG) library is widely used for Monte Carlo simulation. SPRNG supports fast, scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a hardware accelerated version of SPRNG that produces identical results. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we develop a Monte Carlo pi-estimator for the Cray XD1 and XUP platforms. The RC MC pi-estimator shows 8.1 times speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1.
蒙特卡罗方法通常需要生成许多随机数来提供统计上有意义的结果。由于生成随机数耗时且容易出错，可伸缩并行随机数生成器(SPRNG)库被广泛用于蒙特卡罗仿真。spring支持快速、可扩展的随机数生成，具有良好的统计特性。为了加速SPRNG，我们开发了一个硬件加速版本的SPRNG，产生相同的结果。为了演示HASPRNG在可重构计算(RC)应用中的应用，我们为Cray XD1和XUP平台开发了一个蒙特卡罗pi估计器。RC MC pi-estimator显示，在Cray XD1的2.2 GHz AMD Opteron处理器上，速度提高了8.1倍。
{"title":"Hardware accelerated Scalable Parallel Random Number Generators for Monte Carlo methods","authors":"JunKyu Lee, G. D. Peterson, R. Harrison, R. Hinde","doi":"10.1109/MWSCAS.2008.4616765","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616765","url":null,"abstract":"Monte Carlo methods often demand the generation of many random numbers to provide statistically meaningful results. Because generating random numbers is time consuming and error-prone, the Scalable Parallel Random Number Generators (SPRNG) library is widely used for Monte Carlo simulation. SPRNG supports fast, scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a hardware accelerated version of SPRNG that produces identical results. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we develop a Monte Carlo pi-estimator for the Cray XD1 and XUP platforms. The RC MC pi-estimator shows 8.1 times speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127543038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616879
A. Jalili, S. Sayedi
This paper presents a pseudo-background calibration method for the pipelined ADCs in which a main ADC and an extra low resolution, low speed ADC are used. The proposed method uses foreground calibration scheme for the main ADC, but at the same time, it works without any interruption in the normal conversion process by using of the extra ADC for the conversion of the skipped samples. The error associated with the extra ADC, its impact on the overall behavior of the ADC, and its distribution behavior are theoretically analyzed, and the results are verified by simulation. A 12-bit 1.5 bit/stage pipelined ADC and a 12-bit 1.5 bit/stage cyclic ADC are used for the main and the extra ADCs respectively.
{"title":"A digital pseudo background correction method in pipelined ADCs","authors":"A. Jalili, S. Sayedi","doi":"10.1109/MWSCAS.2008.4616879","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616879","url":null,"abstract":"This paper presents a pseudo-background calibration method for the pipelined ADCs in which a main ADC and an extra low resolution, low speed ADC are used. The proposed method uses foreground calibration scheme for the main ADC, but at the same time, it works without any interruption in the normal conversion process by using of the extra ADC for the conversion of the skipped samples. The error associated with the extra ADC, its impact on the overall behavior of the ADC, and its distribution behavior are theoretically analyzed, and the results are verified by simulation. A 12-bit 1.5 bit/stage pipelined ADC and a 12-bit 1.5 bit/stage cyclic ADC are used for the main and the extra ADCs respectively.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"2 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616938
R. Hourani, I. Dalal, W. R. Davis, C. Doss, W. Alexander
This paper presents an efficient implementation of a convolution-based 1D discrete wavelet transform (DWT). The proposed architecture combines several optimizations that improve the performance of the hardware design in terms of throughput and power dissipation. We designed and analyzed the performance of numerous DWT architectures using pertinent metrics and cost functions that assess the impact of the design optimizations. We synthesized our VLSI architectures using a 0.18 mu standard cell library. The final VLSI design combines polyphase decimated FIR filters to reduce power dissipation, pipelined computational cells for higher throughput, and data-interleaving for lower chip area. An analytical comparison with other existing DWT implementations illustrates a two fold improvement in throughput for the proposed architecture.
{"title":"An efficient VLSI implementation for the 1D convolutional discrete wavelet transform","authors":"R. Hourani, I. Dalal, W. R. Davis, C. Doss, W. Alexander","doi":"10.1109/MWSCAS.2008.4616938","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616938","url":null,"abstract":"This paper presents an efficient implementation of a convolution-based 1D discrete wavelet transform (DWT). The proposed architecture combines several optimizations that improve the performance of the hardware design in terms of throughput and power dissipation. We designed and analyzed the performance of numerous DWT architectures using pertinent metrics and cost functions that assess the impact of the design optimizations. We synthesized our VLSI architectures using a 0.18 mu standard cell library. The final VLSI design combines polyphase decimated FIR filters to reduce power dissipation, pipelined computational cells for higher throughput, and data-interleaving for lower chip area. An analytical comparison with other existing DWT implementations illustrates a two fold improvement in throughput for the proposed architecture.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616781
S. Singh, M. Celenk
Three dimensional (3D) shape adaptive cone filter banks are ideally required for selectively filtering of sampled broad band 3D plane wave signals on the basis of their energy distribution. In the proposed design, the shape of each band of the conventional 3D cone filter bank has been adapted based on the energy distribution of the spatio-temporal (ST) 3D plane wave signal. The proposed filter bank is effective for broadband plane wave filtering whose direction of arrival is known a priori. The experimental results prove the robust performance of the proposed shape adaptive 3D cone filter bank in each band of the filter bank.
{"title":"Shape adaptive three dimensional cone filter bank","authors":"S. Singh, M. Celenk","doi":"10.1109/MWSCAS.2008.4616781","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616781","url":null,"abstract":"Three dimensional (3D) shape adaptive cone filter banks are ideally required for selectively filtering of sampled broad band 3D plane wave signals on the basis of their energy distribution. In the proposed design, the shape of each band of the conventional 3D cone filter bank has been adapted based on the energy distribution of the spatio-temporal (ST) 3D plane wave signal. The proposed filter bank is effective for broadband plane wave filtering whose direction of arrival is known a priori. The experimental results prove the robust performance of the proposed shape adaptive 3D cone filter bank in each band of the filter bank.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130988595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616912
Weiqiang Zhang, D. Zhou, Xuanyan Hu, Jianping Hu
The implementations of adiabatic flip-flops and sequential circuits are described in this paper. The flip-flops are realized with the two-phase CPAL (complementary pass-transistor adiabatic logic) circuits. The two-phase non-overlap power-clock generator is used to supply the CPAL sequential circuits, which is realized by using a simple converter and a single-phase sinusoidal power-clock. A power-gating scheme for the adiabatic sequential circuits is proposed. All circuits are implemented using Chartered 0.35 mum CMOS technology, and full-custom layouts are drawn. Based on the post-layout simulation results, the adiabatic sequential circuits with the power-gating scheme attain large energy savings over a wide range of frequencies, as compared with conventional CMOS circuits.
{"title":"The implementations of adiabatic flip-flops and sequential circuits with power-gating schemes","authors":"Weiqiang Zhang, D. Zhou, Xuanyan Hu, Jianping Hu","doi":"10.1109/MWSCAS.2008.4616912","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616912","url":null,"abstract":"The implementations of adiabatic flip-flops and sequential circuits are described in this paper. The flip-flops are realized with the two-phase CPAL (complementary pass-transistor adiabatic logic) circuits. The two-phase non-overlap power-clock generator is used to supply the CPAL sequential circuits, which is realized by using a simple converter and a single-phase sinusoidal power-clock. A power-gating scheme for the adiabatic sequential circuits is proposed. All circuits are implemented using Chartered 0.35 mum CMOS technology, and full-custom layouts are drawn. Based on the post-layout simulation results, the adiabatic sequential circuits with the power-gating scheme attain large energy savings over a wide range of frequencies, as compared with conventional CMOS circuits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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