Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616816
Jun He, R. Geiger, Degang Chen
Until recently a closed-form expression for the output voltage of the most basic bandgap references was not available making it difficult to analytically and systematically determine the effects of the temperature dependence of non-ideal components on the magnitude of the output voltage, on the inflection point location, and on the curvature of these bandgap circuits. In this paper several non-ideal components that can adversely affect the performance of bandgap references are identified. A systematic approach is proposed to analytically determine the effects of the temperature dependence of non-ideal components. Analytical expressions for the effects of two of the most common non-ideal components, the temperature-dependent gain-determining resistors and the amplifier offset voltage, on the temperature characteristics of basic band-gap circuits are developed. The effectiveness of the analytical expression is validated by comparing analytical results with simulation results obtained from Spectre.
{"title":"A detailed analysis of nonideal effects on high precision bandgap voltage references","authors":"Jun He, R. Geiger, Degang Chen","doi":"10.1109/MWSCAS.2008.4616816","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616816","url":null,"abstract":"Until recently a closed-form expression for the output voltage of the most basic bandgap references was not available making it difficult to analytically and systematically determine the effects of the temperature dependence of non-ideal components on the magnitude of the output voltage, on the inflection point location, and on the curvature of these bandgap circuits. In this paper several non-ideal components that can adversely affect the performance of bandgap references are identified. A systematic approach is proposed to analytically determine the effects of the temperature dependence of non-ideal components. Analytical expressions for the effects of two of the most common non-ideal components, the temperature-dependent gain-determining resistors and the amplifier offset voltage, on the temperature characteristics of basic band-gap circuits are developed. The effectiveness of the analytical expression is validated by comparing analytical results with simulation results obtained from Spectre.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125183606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616746
Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong
The multi-threshold-voltage CMOS (MTCMOS) technique is very effective for reducing leakage power. Previously, sleep transistors were connected the virtual ground lines to reduce the power consumption, and a distributed sleep transistor network (DSTN) was proposed to reduce the instantaneous current. This paper presents a research on how to find the near optimal solution for the sleep transistor sizing problem in the DSTN structure. This paper adopts Lagrange successive over-relaxation (SOR) iterative method which is frequently used in the optimization field. The method makes sure the Lagrange multiplier satisfying the extreme conditions during the adjustment in each iteration, in order to find the near-optimum of the problem. Our experimental results are very exciting compared with the nonlinear programming.
{"title":"Sleep transistor sizing for multi-threshold-voltage network using Lagrange SOR iteration","authors":"Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong","doi":"10.1109/MWSCAS.2008.4616746","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616746","url":null,"abstract":"The multi-threshold-voltage CMOS (MTCMOS) technique is very effective for reducing leakage power. Previously, sleep transistors were connected the virtual ground lines to reduce the power consumption, and a distributed sleep transistor network (DSTN) was proposed to reduce the instantaneous current. This paper presents a research on how to find the near optimal solution for the sleep transistor sizing problem in the DSTN structure. This paper adopts Lagrange successive over-relaxation (SOR) iterative method which is frequently used in the optimization field. The method makes sure the Lagrange multiplier satisfying the extreme conditions during the adjustment in each iteration, in order to find the near-optimum of the problem. Our experimental results are very exciting compared with the nonlinear programming.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616940
Yun-Nan Chang, Chien Jung Fu
In this paper, the design of VLSI sorter architecture for the acceleration of data sorting operation is addressed. In order to support the sorting of the variable length sequences, the sorter architecture discussed in this paper is based on a central memory module equipped with some fundamental compare-and-swap (C&S) functional units. Three memory-based sorter designs have been addressed. In addition to the basic single-serial C&S architecture, two parallel approaches have been presented. The first approach based on the direct use of parallel C&S units can lead to the speedup of the sorting process nearly proportional to the number of parallel units being used. However, the second approach based on the multi-step cascaded C&S units can further reduce the number of memory data accesses significantly. The dissipation power due to the memory operation can then be reduced such that this approach will be suitable for low-power applications.
{"title":"Design of VLSI sorting accelerator architecture","authors":"Yun-Nan Chang, Chien Jung Fu","doi":"10.1109/MWSCAS.2008.4616940","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616940","url":null,"abstract":"In this paper, the design of VLSI sorter architecture for the acceleration of data sorting operation is addressed. In order to support the sorting of the variable length sequences, the sorter architecture discussed in this paper is based on a central memory module equipped with some fundamental compare-and-swap (C&S) functional units. Three memory-based sorter designs have been addressed. In addition to the basic single-serial C&S architecture, two parallel approaches have been presented. The first approach based on the direct use of parallel C&S units can lead to the speedup of the sorting process nearly proportional to the number of parallel units being used. However, the second approach based on the multi-step cascaded C&S units can further reduce the number of memory data accesses significantly. The dissipation power due to the memory operation can then be reduced such that this approach will be suitable for low-power applications.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122804933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616817
N. Yamaguchi, Minoru Watanabe
Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. For the laser diode array, a conventional ORGA always required collimated beams, necessitating the use of some lenses and its accurate alignment. Therefore, this paper presents the very compact and simple architecture of a multi-context ORGA that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results of implementation of two configuration contexts and their reconfigurations, in addition to plans for future work.
{"title":"Multi-optical configuration using spreading beams","authors":"N. Yamaguchi, Minoru Watanabe","doi":"10.1109/MWSCAS.2008.4616817","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616817","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. For the laser diode array, a conventional ORGA always required collimated beams, necessitating the use of some lenses and its accurate alignment. Therefore, this paper presents the very compact and simple architecture of a multi-context ORGA that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results of implementation of two configuration contexts and their reconfigurations, in addition to plans for future work.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114261224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616885
S. Yuan, L. G. Johnson, C.C. Liu, C. Hutchens, R. Rennaker
A current biased pseudo-resistor for implantable extracellular neural signal recording applications is introduced in this work. The pseudo-resistor, which is biased in the subthreshold region, is able to realize a very large resistance while keeping the silicon area small. A wide range of resistances can also be implemented by changing the bias current. Issues concerning the linearity of the pseudo-resistor and the frequency response of the pseudo-resistor bias are discussed in this paper. The chips were fabricated in a 0.5 micron 3M2P CMOS process and the test results show that the current biasing method is able to realize more reliable resistance than the voltage biasing method.
{"title":"Current biased pseudo-resistor for implantable neural signal recording applications","authors":"S. Yuan, L. G. Johnson, C.C. Liu, C. Hutchens, R. Rennaker","doi":"10.1109/MWSCAS.2008.4616885","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616885","url":null,"abstract":"A current biased pseudo-resistor for implantable extracellular neural signal recording applications is introduced in this work. The pseudo-resistor, which is biased in the subthreshold region, is able to realize a very large resistance while keeping the silicon area small. A wide range of resistances can also be implemented by changing the bias current. Issues concerning the linearity of the pseudo-resistor and the frequency response of the pseudo-resistor bias are discussed in this paper. The chips were fabricated in a 0.5 micron 3M2P CMOS process and the test results show that the current biasing method is able to realize more reliable resistance than the voltage biasing method.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121875855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616750
Xiong Liu, A. Willson
A linear-in-dB CMOS variable gain amplifier (VGA) targeting a low power read channel front-end is presented. Biased with a less than 2 mA current, this VGA provides 6-18 dB amplification and more than 700 MHz 3-dB bandwidth with less than -45 dB THD in 0.18-mum CMOS. In addition, the 6-18 dB gain is continuously tunable by adjusting the bias current. With such a performance trade-off, it is well suited for mobile storage applications.
提出了一种针对低功耗读通道前端的线性db型CMOS可变增益放大器(VGA)。在小于2 mA电流的偏置下，该VGA提供6-18 dB放大和超过700 MHz的3-dB带宽，在0.18 mA CMOS中THD小于-45 dB。此外，6- 18db增益可通过调整偏置电流连续调谐。有了这样的性能权衡，它非常适合移动存储应用程序。
{"title":"A CMOS linear-in-dB variable gain amplifier for low power read channel front-end","authors":"Xiong Liu, A. Willson","doi":"10.1109/MWSCAS.2008.4616750","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616750","url":null,"abstract":"A linear-in-dB CMOS variable gain amplifier (VGA) targeting a low power read channel front-end is presented. Biased with a less than 2 mA current, this VGA provides 6-18 dB amplification and more than 700 MHz 3-dB bandwidth with less than -45 dB THD in 0.18-mum CMOS. In addition, the 6-18 dB gain is continuously tunable by adjusting the bias current. With such a performance trade-off, it is well suited for mobile storage applications.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129599856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616907
C. Bakula, J. Carletta
A design process for decreasing the average dynamic power consumption of any pulse-shaping filter (PSF) for spread-spectrum communication systems is presented. The process begins with the development of a power consumption approximation function derived from a transistor-level model of the adder used to compute the PSF outputs. This function is then used as the cost function in a simulated annealing search through a set of candidate PSFs produced by perturbing the ideal PSF coefficients. Using a set of PSFs indicative of what would be found in a real application, our process found alternative PSFs with estimated average dynamic power consumption savings ranging from 23.3% to 74.5%. The effects of our process on the frequency response of the PSF, discussed and quantified in this work, are minimal.
{"title":"A hardware-aware process for the design of low-power pulse-shaping filters","authors":"C. Bakula, J. Carletta","doi":"10.1109/MWSCAS.2008.4616907","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616907","url":null,"abstract":"A design process for decreasing the average dynamic power consumption of any pulse-shaping filter (PSF) for spread-spectrum communication systems is presented. The process begins with the development of a power consumption approximation function derived from a transistor-level model of the adder used to compute the PSF outputs. This function is then used as the cost function in a simulated annealing search through a set of candidate PSFs produced by perturbing the ideal PSF coefficients. Using a set of PSFs indicative of what would be found in a real application, our process found alternative PSFs with estimated average dynamic power consumption savings ranging from 23.3% to 74.5%. The effects of our process on the frequency response of the PSF, discussed and quantified in this work, are minimal.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128244223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616906
Shan Wan, Lei Zhang, Qi-jun Zhang
This paper presents an overview of emerging artificial neural network (ANN) techniques and applications for electromagnetic (EM) simulation and design. Accurate time domain EM modeling using recurrent neural networks (RNNs) is reviewed. Advanced robust training algorithm combining particle swarm optimization (PSO) and quasi-Newton method is described through frequency domain EM modeling, showing its ability to avoid ANN training being trapped in local minima to obtain accurate models. ANN applications in computational electromagnetics are also discussed. Great efficiency can be achieved by using ANNs to approximate the computationally intensive calculations in solving Maxwell equations using method of moments (MoM). As illustrated in examples, these ANN-based techniques are capable of fast and accurate EM modeling and MoM computation, and useful for efficient EM based design.
{"title":"Application of artificial neural networks for electromagnetic modeling and computational electromagnetics","authors":"Shan Wan, Lei Zhang, Qi-jun Zhang","doi":"10.1109/MWSCAS.2008.4616906","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616906","url":null,"abstract":"This paper presents an overview of emerging artificial neural network (ANN) techniques and applications for electromagnetic (EM) simulation and design. Accurate time domain EM modeling using recurrent neural networks (RNNs) is reviewed. Advanced robust training algorithm combining particle swarm optimization (PSO) and quasi-Newton method is described through frequency domain EM modeling, showing its ability to avoid ANN training being trapped in local minima to obtain accurate models. ANN applications in computational electromagnetics are also discussed. Great efficiency can be achieved by using ANNs to approximate the computationally intensive calculations in solving Maxwell equations using method of moments (MoM). As illustrated in examples, these ANN-based techniques are capable of fast and accurate EM modeling and MoM computation, and useful for efficient EM based design.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129331414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616861
R. Kumar, V. Kursun
Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra-low power-supply-voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active mode energy consumption. Temperature-adaptive dynamic supply voltage tuning technique is proposed in this paper to reduce the high temperature energy consumption of ultra-low-voltage subthreshold SRAM arrays. Results with a 64-bit times 64-bit memory array in the TSMC 180 nm CMOS technology indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures.
{"title":"Temperature-adaptive dynamic voltage scaling for high temperature energy efficiency in subthreshold memory banks","authors":"R. Kumar, V. Kursun","doi":"10.1109/MWSCAS.2008.4616861","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616861","url":null,"abstract":"Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra-low power-supply-voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active mode energy consumption. Temperature-adaptive dynamic supply voltage tuning technique is proposed in this paper to reduce the high temperature energy consumption of ultra-low-voltage subthreshold SRAM arrays. Results with a 64-bit times 64-bit memory array in the TSMC 180 nm CMOS technology indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616913
A. Sil, Soumik Ghosh, Neeharikha Gogineni, M. Bayoumi
In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the conventional cell. Experimental results show that the write and read energy of the proposed cell are 76.8% and 53% lesser than the conventional cell respectively. Write precharge energy for the proposed cell is almost 81% less than that of conventional cell. During read operation, the proposed cell does not induce any noise at data nodes (dasiaQpsila & dasiaQbarpsila) which makes it a read-SNM-free design.
{"title":"A novel high write speed, low power, read-SNM-free 6T SRAM cell","authors":"A. Sil, Soumik Ghosh, Neeharikha Gogineni, M. Bayoumi","doi":"10.1109/MWSCAS.2008.4616913","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616913","url":null,"abstract":"In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the conventional cell. Experimental results show that the write and read energy of the proposed cell are 76.8% and 53% lesser than the conventional cell respectively. Write precharge energy for the proposed cell is almost 81% less than that of conventional cell. During read operation, the proposed cell does not induce any noise at data nodes (dasiaQpsila & dasiaQbarpsila) which makes it a read-SNM-free design.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"464 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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