Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616883
N. Nambiar, C. Ulaganathan, S. Chen, M. Hale, A. Antonacci, B. Blalock, C. Britton, M. Ericson
A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.
{"title":"SiGe BiCMOS 12-bit 8-channel low power Wilkinson ADC","authors":"N. Nambiar, C. Ulaganathan, S. Chen, M. Hale, A. Antonacci, B. Blalock, C. Britton, M. Ericson","doi":"10.1109/MWSCAS.2008.4616883","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616883","url":null,"abstract":"A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616942
M. Sharawi, D. Aloi
A new signal will be used within the modernized satellites for the global positioning system (GPS) as well as within the launch of the new European global navigation satellite system (GNSS) called Galileo, this signal will use the binary offset carrier (BOC) modulation scheme. BOC signals have very attractive features such as better tracking and immunity to multipath, as well as it will co-exist with current GNSS signals with minimal interference. This paper presents the design and implementation a programmable multi-coded BOC(m,n) signal generator for the use in navigation systems. The design is verified on an FPGA for functionality. Measurements show the correct functionality of this signal generator for both Gold codes and the large set of Kasami codes.
{"title":"A programmable FPGA implementation of a multi-coded BOC(m,n) signal generator for navigation systems","authors":"M. Sharawi, D. Aloi","doi":"10.1109/MWSCAS.2008.4616942","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616942","url":null,"abstract":"A new signal will be used within the modernized satellites for the global positioning system (GPS) as well as within the launch of the new European global navigation satellite system (GNSS) called Galileo, this signal will use the binary offset carrier (BOC) modulation scheme. BOC signals have very attractive features such as better tracking and immunity to multipath, as well as it will co-exist with current GNSS signals with minimal interference. This paper presents the design and implementation a programmable multi-coded BOC(m,n) signal generator for the use in navigation systems. The design is verified on an FPGA for functionality. Measurements show the correct functionality of this signal generator for both Gold codes and the large set of Kasami codes.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"185 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133419488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616734
D. Oshinubi, M. Rocznik, K. Dostert
Micromachined inertial sensors offer new applications and opportunities for improved mobile devices. Especially the consumer market for micromechanical motion sensing through gyroscopes is widely emerging. The integration of inertial sensors within portable devices enforces suitable power management concepts to handle and achieve the tight power budget of the electronic devices. This paper presents a digital system approach to reduce the power consumption for a capacitive micromachined yaw rate sensor and enables an energy efficient frontend operation of the sensor.
{"title":"Undersampling approach for a capacitive micromachined yaw rate sensor","authors":"D. Oshinubi, M. Rocznik, K. Dostert","doi":"10.1109/MWSCAS.2008.4616734","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616734","url":null,"abstract":"Micromachined inertial sensors offer new applications and opportunities for improved mobile devices. Especially the consumer market for micromechanical motion sensing through gyroscopes is widely emerging. The integration of inertial sensors within portable devices enforces suitable power management concepts to handle and achieve the tight power budget of the electronic devices. This paper presents a digital system approach to reduce the power consumption for a capacitive micromachined yaw rate sensor and enables an energy efficient frontend operation of the sensor.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616893
Chi-Chang Lu, Wei-Xiang Tung
A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique, demonstrating its suitability for high-resolution pipelined A/D converter.
{"title":"Switched-capacitor multiply-by-two amplifier for high-resolution pipelined A/D converter","authors":"Chi-Chang Lu, Wei-Xiang Tung","doi":"10.1109/MWSCAS.2008.4616893","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616893","url":null,"abstract":"A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique, demonstrating its suitability for high-resolution pipelined A/D converter.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130393830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616953
I. Sharaa, D. Aloi
This paper provides a methodology to thermally manage an electronic control unit while reducing its radiated emissions. Measurements of the radiated emission levels for a particular electronic control unit revealed excessive levels. Electronic control units utilize pulse width modulated signals to control an external load. The rise and fall times of the pulse width modulated signal impact both the radiated emissions and the thermal behavior of the electronic control unit. The method proposed in this paper establishes a generalized relationship between the rise and fall times of the electronic control unitpsilas pulse width modulated signals to its associated radiated emission levels and thermal behavior.
{"title":"A new method to thermally manage an electronic control unit while reducing radiated emissions","authors":"I. Sharaa, D. Aloi","doi":"10.1109/MWSCAS.2008.4616953","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616953","url":null,"abstract":"This paper provides a methodology to thermally manage an electronic control unit while reducing its radiated emissions. Measurements of the radiated emission levels for a particular electronic control unit revealed excessive levels. Electronic control units utilize pulse width modulated signals to control an external load. The rise and fall times of the pulse width modulated signal impact both the radiated emissions and the thermal behavior of the electronic control unit. The method proposed in this paper establishes a generalized relationship between the rise and fall times of the electronic control unitpsilas pulse width modulated signals to its associated radiated emission levels and thermal behavior.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616873
Xiuli Sun, Jinzhao Wu, Xiaoyu Song
This paper presents a formal refinement model for handshaking expansion based on a powerful strategy of action refinement in the hierarchical design of concurrent systems. The proposed methodology employs wait event structures. It derives a true concurrency model with maximum parallelism, and the refined system conforms to the original specification with respect to a vertical bisimulation relation. Furthermore, the refinement function can preserve correctness and deadlock-freeness of the behavior in the refined system.
{"title":"Handshaking expansion as action refinement","authors":"Xiuli Sun, Jinzhao Wu, Xiaoyu Song","doi":"10.1109/MWSCAS.2008.4616873","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616873","url":null,"abstract":"This paper presents a formal refinement model for handshaking expansion based on a powerful strategy of action refinement in the hierarchical design of concurrent systems. The proposed methodology employs wait event structures. It derives a true concurrency model with maximum parallelism, and the refined system conforms to the original specification with respect to a vertical bisimulation relation. Furthermore, the refinement function can preserve correctness and deadlock-freeness of the behavior in the refined system.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616920
Frank Tuffner, J. Pierre, R. Kubichek
In this paper we introduce a computationally efficient method for updating a weighted Welch periodogram for nonstationary signals. Non-parametric spectral estimation techniques, such as the Welch periodogram, are highly mature topics in signal processing. They have a wide variety of applications in signal analysis including real-time applications with modern test and measurement systems. In many of these real-time applications the data is nonstationary having a power spectrum that is changing over time. This paper introduces a method of generating a weighted update of the Welch periodogram as more data becomes available. We find that for a certain class of weighting functions a computationally efficient algorithm can be found. The paper also presents calculations of the computational complexity of the updating algorithm and simulations for nonstationary signals.
{"title":"Computationally efficient updating of a weighted Welch periodogram for nonstationary signals","authors":"Frank Tuffner, J. Pierre, R. Kubichek","doi":"10.1109/MWSCAS.2008.4616920","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616920","url":null,"abstract":"In this paper we introduce a computationally efficient method for updating a weighted Welch periodogram for nonstationary signals. Non-parametric spectral estimation techniques, such as the Welch periodogram, are highly mature topics in signal processing. They have a wide variety of applications in signal analysis including real-time applications with modern test and measurement systems. In many of these real-time applications the data is nonstationary having a power spectrum that is changing over time. This paper introduces a method of generating a weighted update of the Welch periodogram as more data becomes available. We find that for a certain class of weighting functions a computationally efficient algorithm can be found. The paper also presents calculations of the computational complexity of the updating algorithm and simulations for nonstationary signals.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1049/iet-cds.2008.0324
An Hu, F. Yuan
This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. The proposed current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values for convenient phase comparison. The feedback at the front-end of the receiver minimizes the dependence of the input impedance of the receiver on the direction of the channel current so that signal-dependent impedance mismatch is minimized. Inter-signal timing skew is compensated by inserting a delay line for each channel so that a single sampling clock is needed for all channels. A 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results show that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.
{"title":"Inter-signal timing skew compensation of parallel links with current-mode incremental signaling","authors":"An Hu, F. Yuan","doi":"10.1049/iet-cds.2008.0324","DOIUrl":"https://doi.org/10.1049/iet-cds.2008.0324","url":null,"abstract":"This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. The proposed current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values for convenient phase comparison. The feedback at the front-end of the receiver minimizes the dependence of the input impedance of the receiver on the direction of the channel current so that signal-dependent impedance mismatch is minimized. Inter-signal timing skew is compensated by inserting a delay line for each channel so that a single sampling clock is needed for all channels. A 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results show that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616863
H. Ande, P. Busa, M. Balasubramanian, K. Campbell, R. J. Baker
A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and post-processing of the memory are also discussed.
{"title":"A new approach to the design, fabrication, and testing of chalcogenide-based multi-state phase-change nonvolatile memory","authors":"H. Ande, P. Busa, M. Balasubramanian, K. Campbell, R. J. Baker","doi":"10.1109/MWSCAS.2008.4616863","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616863","url":null,"abstract":"A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and post-processing of the memory are also discussed.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115242723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616895
Y. Haga, I. Kale
This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation.
{"title":"Achieving rail-to-rail input operation using level-shift multiplexing technique for all CMOS op-amps","authors":"Y. Haga, I. Kale","doi":"10.1109/MWSCAS.2008.4616895","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616895","url":null,"abstract":"This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123354887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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