Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616883
N. Nambiar, C. Ulaganathan, S. Chen, M. Hale, A. Antonacci, B. Blalock, C. Britton, M. Ericson
A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.
{"title":"SiGe BiCMOS 12-bit 8-channel low power Wilkinson ADC","authors":"N. Nambiar, C. Ulaganathan, S. Chen, M. Hale, A. Antonacci, B. Blalock, C. Britton, M. Ericson","doi":"10.1109/MWSCAS.2008.4616883","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616883","url":null,"abstract":"A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616942
M. Sharawi, D. Aloi
A new signal will be used within the modernized satellites for the global positioning system (GPS) as well as within the launch of the new European global navigation satellite system (GNSS) called Galileo, this signal will use the binary offset carrier (BOC) modulation scheme. BOC signals have very attractive features such as better tracking and immunity to multipath, as well as it will co-exist with current GNSS signals with minimal interference. This paper presents the design and implementation a programmable multi-coded BOC(m,n) signal generator for the use in navigation systems. The design is verified on an FPGA for functionality. Measurements show the correct functionality of this signal generator for both Gold codes and the large set of Kasami codes.
{"title":"A programmable FPGA implementation of a multi-coded BOC(m,n) signal generator for navigation systems","authors":"M. Sharawi, D. Aloi","doi":"10.1109/MWSCAS.2008.4616942","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616942","url":null,"abstract":"A new signal will be used within the modernized satellites for the global positioning system (GPS) as well as within the launch of the new European global navigation satellite system (GNSS) called Galileo, this signal will use the binary offset carrier (BOC) modulation scheme. BOC signals have very attractive features such as better tracking and immunity to multipath, as well as it will co-exist with current GNSS signals with minimal interference. This paper presents the design and implementation a programmable multi-coded BOC(m,n) signal generator for the use in navigation systems. The design is verified on an FPGA for functionality. Measurements show the correct functionality of this signal generator for both Gold codes and the large set of Kasami codes.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"185 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133419488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616734
D. Oshinubi, M. Rocznik, K. Dostert
Micromachined inertial sensors offer new applications and opportunities for improved mobile devices. Especially the consumer market for micromechanical motion sensing through gyroscopes is widely emerging. The integration of inertial sensors within portable devices enforces suitable power management concepts to handle and achieve the tight power budget of the electronic devices. This paper presents a digital system approach to reduce the power consumption for a capacitive micromachined yaw rate sensor and enables an energy efficient frontend operation of the sensor.
{"title":"Undersampling approach for a capacitive micromachined yaw rate sensor","authors":"D. Oshinubi, M. Rocznik, K. Dostert","doi":"10.1109/MWSCAS.2008.4616734","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616734","url":null,"abstract":"Micromachined inertial sensors offer new applications and opportunities for improved mobile devices. Especially the consumer market for micromechanical motion sensing through gyroscopes is widely emerging. The integration of inertial sensors within portable devices enforces suitable power management concepts to handle and achieve the tight power budget of the electronic devices. This paper presents a digital system approach to reduce the power consumption for a capacitive micromachined yaw rate sensor and enables an energy efficient frontend operation of the sensor.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616893
Chi-Chang Lu, Wei-Xiang Tung
A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique, demonstrating its suitability for high-resolution pipelined A/D converter.
{"title":"Switched-capacitor multiply-by-two amplifier for high-resolution pipelined A/D converter","authors":"Chi-Chang Lu, Wei-Xiang Tung","doi":"10.1109/MWSCAS.2008.4616893","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616893","url":null,"abstract":"A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique, demonstrating its suitability for high-resolution pipelined A/D converter.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130393830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616953
I. Sharaa, D. Aloi
This paper provides a methodology to thermally manage an electronic control unit while reducing its radiated emissions. Measurements of the radiated emission levels for a particular electronic control unit revealed excessive levels. Electronic control units utilize pulse width modulated signals to control an external load. The rise and fall times of the pulse width modulated signal impact both the radiated emissions and the thermal behavior of the electronic control unit. The method proposed in this paper establishes a generalized relationship between the rise and fall times of the electronic control unitpsilas pulse width modulated signals to its associated radiated emission levels and thermal behavior.
{"title":"A new method to thermally manage an electronic control unit while reducing radiated emissions","authors":"I. Sharaa, D. Aloi","doi":"10.1109/MWSCAS.2008.4616953","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616953","url":null,"abstract":"This paper provides a methodology to thermally manage an electronic control unit while reducing its radiated emissions. Measurements of the radiated emission levels for a particular electronic control unit revealed excessive levels. Electronic control units utilize pulse width modulated signals to control an external load. The rise and fall times of the pulse width modulated signal impact both the radiated emissions and the thermal behavior of the electronic control unit. The method proposed in this paper establishes a generalized relationship between the rise and fall times of the electronic control unitpsilas pulse width modulated signals to its associated radiated emission levels and thermal behavior.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616873
Xiuli Sun, Jinzhao Wu, Xiaoyu Song
This paper presents a formal refinement model for handshaking expansion based on a powerful strategy of action refinement in the hierarchical design of concurrent systems. The proposed methodology employs wait event structures. It derives a true concurrency model with maximum parallelism, and the refined system conforms to the original specification with respect to a vertical bisimulation relation. Furthermore, the refinement function can preserve correctness and deadlock-freeness of the behavior in the refined system.
{"title":"Handshaking expansion as action refinement","authors":"Xiuli Sun, Jinzhao Wu, Xiaoyu Song","doi":"10.1109/MWSCAS.2008.4616873","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616873","url":null,"abstract":"This paper presents a formal refinement model for handshaking expansion based on a powerful strategy of action refinement in the hierarchical design of concurrent systems. The proposed methodology employs wait event structures. It derives a true concurrency model with maximum parallelism, and the refined system conforms to the original specification with respect to a vertical bisimulation relation. Furthermore, the refinement function can preserve correctness and deadlock-freeness of the behavior in the refined system.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616800
K. Lin, Yen Hung Lin
Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.
{"title":"A synchronous modular multiplier with variable latency","authors":"K. Lin, Yen Hung Lin","doi":"10.1109/MWSCAS.2008.4616800","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616800","url":null,"abstract":"Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616821
M. E. Heidari, A. Mirzaei, R. Bagheri, S. Chehrazi, A. Abidi
By applying basic geometrical rules we analyze an LC quadrature oscillator. Various oscillation modes and their stabilities are investigated and impacts of mismatches on the quadrature accuracy are calculated.
{"title":"Geometrical analysis of LC quadrature oscillator","authors":"M. E. Heidari, A. Mirzaei, R. Bagheri, S. Chehrazi, A. Abidi","doi":"10.1109/MWSCAS.2008.4616821","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616821","url":null,"abstract":"By applying basic geometrical rules we analyze an LC quadrature oscillator. Various oscillation modes and their stabilities are investigated and impacts of mismatches on the quadrature accuracy are calculated.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131816404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616730
T. Ragheb, J. Laska, H. Nejati, S. Kirolos, Richard Baraniuk, Y. Massoud
In this paper, we utilize recent advances in compressive sensing theory to enable signal acquisition beyond Nyquist sampling constraints. We successfully recover signals sampled at sub-Nyquist sampling rates by exploiting additional structure other than bandlimitedness. We present a working prototype of compressive analog-to-digital converter (CADC) based on a random demodulation architecture. The architecture is particularly suitable for wideband signals that are sparse in the time-frequency plane. CADC has the advantage of enhancing the performance of communication and multimedia systems by increasing the transmission rate for the same bandwidth. We report successful reconstruction of AM modulated signals at sampling rates down to 1/8 of the Nyquist-rate, which represents an up to 87.5% savings in the bandwidth and the storage memory.
{"title":"A prototype hardware for random demodulation based compressive analog-to-digital conversion","authors":"T. Ragheb, J. Laska, H. Nejati, S. Kirolos, Richard Baraniuk, Y. Massoud","doi":"10.1109/MWSCAS.2008.4616730","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616730","url":null,"abstract":"In this paper, we utilize recent advances in compressive sensing theory to enable signal acquisition beyond Nyquist sampling constraints. We successfully recover signals sampled at sub-Nyquist sampling rates by exploiting additional structure other than bandlimitedness. We present a working prototype of compressive analog-to-digital converter (CADC) based on a random demodulation architecture. The architecture is particularly suitable for wideband signals that are sparse in the time-frequency plane. CADC has the advantage of enhancing the performance of communication and multimedia systems by increasing the transmission rate for the same bandwidth. We report successful reconstruction of AM modulated signals at sampling rates down to 1/8 of the Nyquist-rate, which represents an up to 87.5% savings in the bandwidth and the storage memory.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132119392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616882
Jipeng Wang, B. Jalali-Farahani
This paper reports the transistor-level design of a continuous-time 2-1 MASH sigma delta modulator with digital adaptive tuning of the cancellation logic. The modulator is designed for broadband wireless applications and provides 12 bits of resolution for a 10 MHz signal bandwidth. A direct approach to design the CT MASH modulator is used which reduces the coupling between the MASH stages. The problems of excess loop delay and clock jitter are addressed. Excess delay compensation loops are used to overcome the problem of excess loop delay. Multi-bit quantizers with NRZ DACs are used to reduce the effect of clock jitter. It is shown that without calibration, the performance of a CT MASH modulator would be severely degraded due to different analog imperfections such as finite gain and bandwidth of the Opamp, clock jitter and even addition of the excess delay compensation loops. The catastrophic degradation is due to the leakage of lower order noise to the output of the modulator. An adaptive digital tuning of the digital filters is used in this design to regain the performance of the modulator in presence of the above errors. Simulation results show that the modulator provides the required resolution while consuming 20 mW of power from 1.8 V supply voltage.
{"title":"A CT MASH ΣΔ modulator with adaptive digital tuning for analog circuit imperfections","authors":"Jipeng Wang, B. Jalali-Farahani","doi":"10.1109/MWSCAS.2008.4616882","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616882","url":null,"abstract":"This paper reports the transistor-level design of a continuous-time 2-1 MASH sigma delta modulator with digital adaptive tuning of the cancellation logic. The modulator is designed for broadband wireless applications and provides 12 bits of resolution for a 10 MHz signal bandwidth. A direct approach to design the CT MASH modulator is used which reduces the coupling between the MASH stages. The problems of excess loop delay and clock jitter are addressed. Excess delay compensation loops are used to overcome the problem of excess loop delay. Multi-bit quantizers with NRZ DACs are used to reduce the effect of clock jitter. It is shown that without calibration, the performance of a CT MASH modulator would be severely degraded due to different analog imperfections such as finite gain and bandwidth of the Opamp, clock jitter and even addition of the excess delay compensation loops. The catastrophic degradation is due to the leakage of lower order noise to the output of the modulator. An adaptive digital tuning of the digital filters is used in this design to regain the performance of the modulator in presence of the above errors. Simulation results show that the modulator provides the required resolution while consuming 20 mW of power from 1.8 V supply voltage.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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