ETRI Journal最新文献

Anomaly detection in video surveillance is crucial but challenging due to the rarity of irregular events and ambiguity of defining anomalies. We propose a method called AONet that utilizes a spatiotemporal module to extract spatiotemporal features efficiently, as well as a residual autoencoder equipped with an attention network for effective future frame prediction in video anomaly detection. AONet utilizes a novel activation function called OptAF that combines the strengths of the ReLU, leaky ReLU, and sigmoid functions. Furthermore, the proposed method employs a combination of robust loss functions to address various aspects of prediction errors and enhance training effectiveness. The performance of the proposed method is evaluated on three widely used benchmark datasets. The results indicate that the proposed method outperforms existing state-of-the-art methods and demonstrates comparable performance, achieving area under the curve values of 97.0%, 86.9%, and 73.8% on the UCSD Ped2, CUHK Avenue, and ShanghaiTech Campus datasets, respectively. Additionally, the high speed of the proposed method enables its application to real-time tasks.

Deep learning (DL) has significantly advanced artificial intelligence (AI); however, frameworks such as PyTorch, ONNX, and TensorFlow are optimized for general-purpose GPUs, leading to inefficiencies on specialized accelerators such as neural processing units (NPUs) and processing-in-memory (PIM) devices. These accelerators are designed to optimize both throughput and energy efficiency but they require more tailored optimizations. To address these limitations, we propose the NEST compiler (NEST-C), a novel DL framework that improves the deployment and performance of models across various AI accelerators. NEST-C leverages profiling-based quantization, dynamic graph partitioning, and multi-level intermediate representation (IR) integration for efficient execution on diverse hardware platforms. Our results show that NEST-C significantly enhances computational efficiency and adaptability across various AI accelerators, achieving higher throughput, lower latency, improved resource utilization, and greater model portability. These benefits contribute to more efficient DL model deployment in modern AI applications.

In this study, we report a transmitter system for free-space quantum key distribution (QKD) using the BB84 protocol, which does not require an internal alignment process, by using a wavelength-division multiplexing (WDM) filter and polarization-encoding module. With a custom-made WDM filter, the signals required for QKD can be integrated by simply connecting fibers, thus avoiding the laborious internal alignment required for free-space QKD systems using conventional bulk-optic setups. The WDM filter is designed to multiplex the single-mode signals from 785-nm quantum and 1550-nm synchronization channels for spatial-mode matching while maintaining the polarization relations. The measured insertion loss and isolation are 1.8 dB and 32.6 dB for 785 nm and 0.7 dB and 28.3 dB for 1550 nm, respectively. We also evaluate the QKD performance of the proposed system. The sifted key rate and quantum bit error rate are 1.6 Mbps and 0.62%, respectively, at an operating speed of 100 MHz, rendering our system comparable to conventional systems using bulk-optic devices for channel integration.

Lithium niobate on insulator (LNOI) is a promising material platform for applications in integrated quantum photonics. A low optical loss is crucial for preserving fragile quantum states. Therefore, in this study, we have fabricated LNOI rib waveguides with a low optical propagation loss of 0.16 dB/cm by optimizing the etching conditions for various parameters. The symmetry and smoothness of the waveguides on $�x$-cut LNOI are improved by employing a shallow etching process. The proposed method is expected to facilitate the development of on-chip quantum photonic devices based on LNOI.

Fault-tolerant quantum computation requires error-correcting codes that enable reliable universal quantum operations. This study introduces a novel approach that executes the logical Hadamard with low-space requirements while preserving the original definition of logical operators within the framework of the rotated surface codes. Our method leverages a boundary deformation method to rotate the logical qubit transformed by transversal Hadamard. Following this, the original encoding of the logical qubit is reinstated through logical flip-and-shift operations. The estimated space–time cost for a logical Hadamard operation with a code distance d is 5d² + 3d². The efficiency enhancement of the proposed method is approximately four times greater than those of previous approaches, regardless of the code distance. Unlike the traditional method, implementing a logical Hadamard requires only two patches instead of seven. Furthermore, the proposed method ensures the parallelism of quantum circuits by preventing interferences between adjacent logical data qubits.

To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal–oxide–semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.

As computing systems become increasingly larger, high-performance computing (HPC) is gaining importance. In particular, as hyperscale artificial intelligence (AI) applications, such as large language models emerge, HPC has become important even in the field of AI. Important operations in hyperscale AI and HPC are mainly linear algebraic operations based on tensors. An AB21 supercomputing AI processor has been proposed to accelerate such applications. This study proposes a XEM accelerator to accelerate linear algebraic operations in an AB21 processor effectively. The XEM accelerator has outer product-based parallel floating-point units that can efficiently process tensor operations. We provide hardware details of the XEM architecture and introduce new instructions for controlling the XEM accelerator. Additionally, hardware characteristic analyses based on chip fabrication and simulator-based functional verification are conducted. In the future, the performance and functionalities of the XEM accelerator will be verified using an AB21 processor.

The photochemical acid generation is refined from the first principles of quantum electrodynamics. First, we briefly review the formulation of the quantum theory of light based on the quantum electrodynamics framework to establish the probability of acid generation at a given spacetime point. The quantum mechanical acid generation is then combined with the deprotection mechanism to obtain a probabilistic description of the deprotection density directly related to feature formation in a photoresist. A statistical analysis of the random deprotection density is presented to reveal the leading characteristics of stochastic feature formation.

LED-to-LED visible light communication (VLC), which uses LEDs not only for the transmitter but also for the receiver, is being studied as an efficient optical wireless communication technology that uses LED lighting infrastructure. In this paper, we investigate microLED-to-LED VLC, which uses microLEDs as both the transmitter and receiver. In particular, we conducted a study to improve the performance of microLED-to-microLED VLC. For this, we measured the performance depending on the transmitter and receiver LED color combination. In addition, the effects of zero bias and reverse bias at the receiver LED were investigated. We also investigated the improvement in the reverse bias when applying a transimpedance amplifier to the receiver LED. Finally, we experimentally demonstrated a data rate of 360 kbps in the microLED-to-microLED VLC.

This paper presents a membrane computation error-minimized mixed-mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid-node pre-charge scheme to construct a high-precision current-mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28-nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 μW of power consumed. Moreover, the peak-to-peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample-wise random variations.