Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437070
B. Bittel, S. Novak, S. Ramey, S. Padiyar, J. Ryan, J. Campbell, K. Cheung
Charge Pumping (CP) has historically been a widely utilized tool to study reliability-limiting interface and near interface trapping centers in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). However, conventional CP methods are not effective for modern highly scaled devices due to high gate leakage current to CP current ratios. Fortunately, a newly developed CP technique has been developed, called frequency modulated CP (FMCP), which overcomes the limitations of conventional measurements and permits full CP studies to be successfully applied to highly scaled devices. In this work, we evaluate the practicality and usefulness of implementing FMCP to characterize Intel's second generation 14nm tri-gate MOSFETs. This demonstration clearly highlights FMCP's power and ability to provide critical information in current and future highly scaled technology nodes.
{"title":"Novel Charge Pumping method applied to tri-gate MOSFETs for reliability characterization","authors":"B. Bittel, S. Novak, S. Ramey, S. Padiyar, J. Ryan, J. Campbell, K. Cheung","doi":"10.1109/IIRW.2015.7437070","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437070","url":null,"abstract":"Charge Pumping (CP) has historically been a widely utilized tool to study reliability-limiting interface and near interface trapping centers in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). However, conventional CP methods are not effective for modern highly scaled devices due to high gate leakage current to CP current ratios. Fortunately, a newly developed CP technique has been developed, called frequency modulated CP (FMCP), which overcomes the limitations of conventional measurements and permits full CP studies to be successfully applied to highly scaled devices. In this work, we evaluate the practicality and usefulness of implementing FMCP to characterize Intel's second generation 14nm tri-gate MOSFETs. This demonstration clearly highlights FMCP's power and ability to provide critical information in current and future highly scaled technology nodes.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437072
M. Hsieh, T. Yew, Y. Huang, Y. C. Wang, W. Wang, Y. Lee, J. H. Lee
Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.
{"title":"Wafer level test arrays with simple BIST to expedite process development for circuit reliability","authors":"M. Hsieh, T. Yew, Y. Huang, Y. C. Wang, W. Wang, Y. Lee, J. H. Lee","doi":"10.1109/IIRW.2015.7437072","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437072","url":null,"abstract":"Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131453444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2015.7437076
V. Putcha, Marko Simicic, P. Weckx, B. Parvais, J. Franco, B. Kaczer, D. Linten, D. Verkest, A. Thean, G. Groeseneken
Deeply-scaled transistors fabricated in advanced High-k/Metal Gate (HK/MG) technologies have an intrinsic variability, requiring characterization of a large number of transistors to obtain statistically relevant data. A powerful tool in the form of a Smart-array circuit is designed to serve the BTI characterization needs on an industrial scale, where time plays an important role. The Smart-array circuit is designed such that 700 pMOS and nMOS transistors can be measured using the concept of pipelining. A significant reduction of up to 88.5% in time is demonstrated by establishing a pipeline of 15 pMOS transistors and the Measure-Stress-Measure (MSM) scheme of choice.
{"title":"Smart-array for pipelined BTI characterization","authors":"V. Putcha, Marko Simicic, P. Weckx, B. Parvais, J. Franco, B. Kaczer, D. Linten, D. Verkest, A. Thean, G. Groeseneken","doi":"10.1109/IIRW.2015.7437076","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437076","url":null,"abstract":"Deeply-scaled transistors fabricated in advanced High-k/Metal Gate (HK/MG) technologies have an intrinsic variability, requiring characterization of a large number of transistors to obtain statistically relevant data. A powerful tool in the form of a Smart-array circuit is designed to serve the BTI characterization needs on an industrial scale, where time plays an important role. The Smart-array circuit is designed such that 700 pMOS and nMOS transistors can be measured using the concept of pipelining. A significant reduction of up to 88.5% in time is demonstrated by establishing a pipeline of 15 pMOS transistors and the Measure-Stress-Measure (MSM) scheme of choice.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2015.7437060
P. Weckx, B. Kaczer, J. Franco, P. Roussel, E. Bury, A. Subirats, G. Groeseneken, F. Catthoor, D. Linten, P. Raghavan, A. Thean
This paper describes the implications of time-dependent threshold voltage variability, induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), on the reliability and performance of advanced technology nodes. Investigation of time-dependent variability at the individual trap level, e.g. in production environments, is not feasible with approaches such as single device measurements developed in the academic literature. Nonetheless, nFET and pFET time-dependent variability, in addition to standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group. The statistical distributions encompassing both BTI and RTN variability and their correlations are discussed from a defect-centric perspective.
{"title":"Defect-centric perspective of combined BTI and RTN time-dependent variability","authors":"P. Weckx, B. Kaczer, J. Franco, P. Roussel, E. Bury, A. Subirats, G. Groeseneken, F. Catthoor, D. Linten, P. Raghavan, A. Thean","doi":"10.1109/IIRW.2015.7437060","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437060","url":null,"abstract":"This paper describes the implications of time-dependent threshold voltage variability, induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), on the reliability and performance of advanced technology nodes. Investigation of time-dependent variability at the individual trap level, e.g. in production environments, is not feasible with approaches such as single device measurements developed in the academic literature. Nonetheless, nFET and pFET time-dependent variability, in addition to standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group. The statistical distributions encompassing both BTI and RTN variability and their correlations are discussed from a defect-centric perspective.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116003264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2015.7437071
Marko Simicic, V. Putcha, B. Parvais, P. Weckx, B. Kaczer, G. Groeseneken, G. Gielen, D. Linten, A. Thean
Time-zero variability, bias temperature instability (BTI) and random telegraph noise (RTN) are issues that both analog and digital designers using scaled CMOS technologies have to face. In order to address them at design time, access to a sufficiently large number of individual devices is required for statistical technology characterization and modeling. In this paper we present a large MOSFET array designed and fabricated in an advanced 28nm technology, containing both nMOS and pMOS devices of different sizes, both single and stacked. Measurement data for time-zero and time-dependent variability are shown and discussed. Large scale transistor arrays are an indispensable tool to accurately capture the statistics of variability and reliability mechanisms in advanced technology nodes.
{"title":"Advanced MOSFET variability and reliability characterization array","authors":"Marko Simicic, V. Putcha, B. Parvais, P. Weckx, B. Kaczer, G. Groeseneken, G. Gielen, D. Linten, A. Thean","doi":"10.1109/IIRW.2015.7437071","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437071","url":null,"abstract":"Time-zero variability, bias temperature instability (BTI) and random telegraph noise (RTN) are issues that both analog and digital designers using scaled CMOS technologies have to face. In order to address them at design time, access to a sufficiently large number of individual devices is required for statistical technology characterization and modeling. In this paper we present a large MOSFET array designed and fabricated in an advanced 28nm technology, containing both nMOS and pMOS devices of different sizes, both single and stacked. Measurement data for time-zero and time-dependent variability are shown and discussed. Large scale transistor arrays are an indispensable tool to accurately capture the statistics of variability and reliability mechanisms in advanced technology nodes.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128621190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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