Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437081
T. Shaw, X. Liu, E. Misra, D. Questad, G. Bonilla, T. Wassick, M. Lamorey, H. Shobha, G. Osborne, D. Kioussis, J. Wright, R. Bisson, I. Paquin, S. Bouchard, S. Tetreault, D. Stone, C. Muzzy, B. Sundlof, T. Daubenspeck
The paper examines the factors that affect the formation of delaminations under C4 joints during chip joining. Through multiscale finite element modeling and chip joining experiments we find that two important parameters determining the susceptibility to C4 delaminations (white bumps) are the effective modulus of the low-K levels in the BEOL stack and the thickness of the upper level in the stack that are built in an oxide dielectric. A simple effective spring model is developed to estimate the impact of metal loading at the via and line levels of interconnect structure on the effective modulus of the low-K dielectric stack. The importance of the effective modulus as a parameter controlling white bump formation is confirmed using a purpose built chip in which the effective modulus is modulated in each corner of the chip. Based on the observations from chip joining experiments it is demonstrated that failng BEOL structures can be differentiated from safe structures using a fail/safe map that is constructed using the effective modulus of the low-K levels and the thickness of the oxide levels as the two axes of the map.
{"title":"The strength of BEOL structures fabricated using low K materials and its impact on CPI failures","authors":"T. Shaw, X. Liu, E. Misra, D. Questad, G. Bonilla, T. Wassick, M. Lamorey, H. Shobha, G. Osborne, D. Kioussis, J. Wright, R. Bisson, I. Paquin, S. Bouchard, S. Tetreault, D. Stone, C. Muzzy, B. Sundlof, T. Daubenspeck","doi":"10.1109/IIRW.2015.7437081","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437081","url":null,"abstract":"The paper examines the factors that affect the formation of delaminations under C4 joints during chip joining. Through multiscale finite element modeling and chip joining experiments we find that two important parameters determining the susceptibility to C4 delaminations (white bumps) are the effective modulus of the low-K levels in the BEOL stack and the thickness of the upper level in the stack that are built in an oxide dielectric. A simple effective spring model is developed to estimate the impact of metal loading at the via and line levels of interconnect structure on the effective modulus of the low-K dielectric stack. The importance of the effective modulus as a parameter controlling white bump formation is confirmed using a purpose built chip in which the effective modulus is modulated in each corner of the chip. Based on the observations from chip joining experiments it is demonstrated that failng BEOL structures can be differentiated from safe structures using a fail/safe map that is constructed using the effective modulus of the low-K levels and the thickness of the oxide levels as the two axes of the map.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437087
T. Kopley, M. Ring, C. Choi, J. Colbath
We present a gate oxide breakdown analysis method that uses an effective oxide thickness model combined with Time-Dependent Dielectric Breakdown (TDDB) model parameters to assess the reliability of extrinsic gate oxide defects. The method transforms gate breakdown voltage (Vbd), obtained from voltage ramp-to-breakdown measurements, into effective oxide thickness (teff) and compares these to the minimum oxide thickness that gives 10 or 20 years TDDB lifetimes. The analysis allows binning of extrinsic defects (Jedec mode B) into reliable and unreliable populations. It also gives an optimal gate screen voltage that can be used at wafer sort to screen parts with unreliable gate oxides. This method is valid for any CMOS process, but is especially useful for BCDMOS and Power Trench MOSFET technologies that use very large devices and ship in large volumes.
{"title":"Combined Vramp and TDDB analysis for gate oxide reliability assessment and screening","authors":"T. Kopley, M. Ring, C. Choi, J. Colbath","doi":"10.1109/IIRW.2015.7437087","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437087","url":null,"abstract":"We present a gate oxide breakdown analysis method that uses an effective oxide thickness model combined with Time-Dependent Dielectric Breakdown (TDDB) model parameters to assess the reliability of extrinsic gate oxide defects. The method transforms gate breakdown voltage (Vbd), obtained from voltage ramp-to-breakdown measurements, into effective oxide thickness (teff) and compares these to the minimum oxide thickness that gives 10 or 20 years TDDB lifetimes. The analysis allows binning of extrinsic defects (Jedec mode B) into reliable and unreliable populations. It also gives an optimal gate screen voltage that can be used at wafer sort to screen parts with unreliable gate oxides. This method is valid for any CMOS process, but is especially useful for BCDMOS and Power Trench MOSFET technologies that use very large devices and ship in large volumes.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128904247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437085
Dae-Hyun Kim, L. Milor
A memory is a high-density device with low cost per bit. Denser memories are likely to contain more errors. Replacing such errors requires repair schemes with good cells for the yield enhancement of a memory. The yield of a memory, therefore, should be calculated considering the repair scheme that a memory system has incorporated. In this paper, we propose a methodology that estimates the yield and the lifetime of a memory with various failure mechanisms and repair schemes of a memory. In a case study of aging errors in a 2Gb DDR3 SDRAM, we demonstrate the feasibility of our yield and lifetime estimation with various redundancy combinations.
{"title":"Memory yield and lifetime estimation considering aging errors","authors":"Dae-Hyun Kim, L. Milor","doi":"10.1109/IIRW.2015.7437085","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437085","url":null,"abstract":"A memory is a high-density device with low cost per bit. Denser memories are likely to contain more errors. Replacing such errors requires repair schemes with good cells for the yield enhancement of a memory. The yield of a memory, therefore, should be calculated considering the repair scheme that a memory system has incorporated. In this paper, we propose a methodology that estimates the yield and the lifetime of a memory with various failure mechanisms and repair schemes of a memory. In a case study of aging errors in a 2Gb DDR3 SDRAM, we demonstrate the feasibility of our yield and lifetime estimation with various redundancy combinations.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437065
G. Sereni, L. Larcher
In this work we will apply a novel extraction procedure to characterize interfacial states and border traps in InGaAs and Ge MOSFETs. The extraction technique, which will allow profiling the defect distributions in the (E,z) dielectric bandgap, is based on the simultaneous simulation of C-V and G-V characteristic over a wide frequency range. The impact of minority carrier generation mechanisms taking place in the semiconductor will be deeply investigated, as its impact is essential when the technique is applied to direct low-bandgap semiconductors such as InGaAs and Ge. Results will confirm that the minority carrier generation has to carefully consider to avoid overestimating the extracted defect density.
{"title":"Extraction of interface and border traps in beyond-Si devices by accounting for generation and recombination in the semiconductor","authors":"G. Sereni, L. Larcher","doi":"10.1109/IIRW.2015.7437065","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437065","url":null,"abstract":"In this work we will apply a novel extraction procedure to characterize interfacial states and border traps in InGaAs and Ge MOSFETs. The extraction technique, which will allow profiling the defect distributions in the (E,z) dielectric bandgap, is based on the simultaneous simulation of C-V and G-V characteristic over a wide frequency range. The impact of minority carrier generation mechanisms taking place in the semiconductor will be deeply investigated, as its impact is essential when the technique is applied to direct low-bandgap semiconductors such as InGaAs and Ge. Results will confirm that the minority carrier generation has to carefully consider to avoid overestimating the extracted defect density.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115560174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437067
S. Ramey, Y. Lu, I. Meric, S. Mudanai, S. Novak, C. Prasad, J. Hicks
As tri-gate transistor technologies continue to scale to smaller dimensions, a variety of aging mechanisms become important to include in models to accurately predict end-of-life transistor performance. Traditional aging effects such as BTI and hot carrier continue to play a role. However, modeling these mechanisms becomes more complicated with the addition of recovery, variation, and local self-heating. Further, second-order effects are starting to accumulate, such as recovery interactions, minority carrier gate injection, damage localization, and interactions between hot carrier and BTI. This work highlights the roles and impacts of these various effects and how they will need to fit into a comprehensive aging model.
{"title":"Aging model challenges in deeply scaled tri-gate technologies","authors":"S. Ramey, Y. Lu, I. Meric, S. Mudanai, S. Novak, C. Prasad, J. Hicks","doi":"10.1109/IIRW.2015.7437067","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437067","url":null,"abstract":"As tri-gate transistor technologies continue to scale to smaller dimensions, a variety of aging mechanisms become important to include in models to accurately predict end-of-life transistor performance. Traditional aging effects such as BTI and hot carrier continue to play a role. However, modeling these mechanisms becomes more complicated with the addition of recovery, variation, and local self-heating. Further, second-order effects are starting to accumulate, such as recovery interactions, minority carrier gate injection, damage localization, and interactions between hot carrier and BTI. This work highlights the roles and impacts of these various effects and how they will need to fit into a comprehensive aging model.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130288890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437064
A. Grill, G. Rzepa, P. Lagger, C. Ostermaier, H. Ceric, T. Grasser
Charge trapping in the insulating layer of gallium-nitride (GaN) metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) is a serious reliability challenge but is still poorly understood. We demonstrate here that the observed Vth drift and recovery can be understood as charge capture and emission following a non-radiative multi-phonon (NMP) mechanism into traps with widely distributed properties. Furthermore, due to the large amount of trapped charge, the feedback of that charge on the surface potential and thus on the capture and emission times has to be considered self-consistently in order to correctly explain the temporal changes in their distributions.
{"title":"Charge feedback mechanisms at forward threshold voltage stress in GaN/AlGaN HEMTs","authors":"A. Grill, G. Rzepa, P. Lagger, C. Ostermaier, H. Ceric, T. Grasser","doi":"10.1109/IIRW.2015.7437064","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437064","url":null,"abstract":"Charge trapping in the insulating layer of gallium-nitride (GaN) metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) is a serious reliability challenge but is still poorly understood. We demonstrate here that the observed Vth drift and recovery can be understood as charge capture and emission following a non-radiative multi-phonon (NMP) mechanism into traps with widely distributed properties. Furthermore, due to the large amount of trapped charge, the feedback of that charge on the surface potential and thus on the capture and emission times has to be considered self-consistently in order to correctly explain the temporal changes in their distributions.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126381655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437066
A. Kim, C. Christiansen, Baozhen Li, E. Wu, P. McLaughlin
As semiconductor manufacturing process becomes increasingly complex in advanced technologies, time-to-fail characteristics of BEOL TDDB are often significantly affected by within-wafer process variations, especially in early development stages. With the presence of such an effect, an accurate estimation of TDDB model parameters becomes difficult and sometimes erroneous values can be observed, which may lead to an incorrect conclusion. In order to minimize an artifact of process variation effect on TDDB model parameters, we propose and demonstrate a practical approach of ramped-voltage sample screening followed by grouping of unstressed clone samples for TDDB stresses and determination of voltage stress sequence on samples with a dynamically generated stress wafermap instead of using a predetermined checkerboard pattern wafermap. It is also demonstrated that the proposed approach can help greatly improve the accuracy of long-term TDDB stress results, without invoking large sample studies. An example will be given with this sampling approach how a voltage acceleration parameter can be affected depending on the choice of samples.
{"title":"A sampling approach for efficient BEOL TDDB assessment","authors":"A. Kim, C. Christiansen, Baozhen Li, E. Wu, P. McLaughlin","doi":"10.1109/IIRW.2015.7437066","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437066","url":null,"abstract":"As semiconductor manufacturing process becomes increasingly complex in advanced technologies, time-to-fail characteristics of BEOL TDDB are often significantly affected by within-wafer process variations, especially in early development stages. With the presence of such an effect, an accurate estimation of TDDB model parameters becomes difficult and sometimes erroneous values can be observed, which may lead to an incorrect conclusion. In order to minimize an artifact of process variation effect on TDDB model parameters, we propose and demonstrate a practical approach of ramped-voltage sample screening followed by grouping of unstressed clone samples for TDDB stresses and determination of voltage stress sequence on samples with a dynamically generated stress wafermap instead of using a predetermined checkerboard pattern wafermap. It is also demonstrated that the proposed approach can help greatly improve the accuracy of long-term TDDB stress results, without invoking large sample studies. An example will be given with this sampling approach how a voltage acceleration parameter can be affected depending on the choice of samples.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114399887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437088
S. Tyaginov, M. Jech, P. Sharma, J. Franco, B. Kaczer, T. Grasser
We show that - in contrast to previous findings - hot-carrier degradation (HCD) in scaled nMOSFETs with a channel length of 44 nm appears to be weaker at elevated temperatures. However, the distance between degradation traces obtained at 25 and 75° C reduces as the stress voltages increase and at a certain voltage the changes of the linear drain current measured at 25 and 75° C are almost identical in the entire stress time window. We apply our physics-based model for hot-carrier degradation to analyze the temperature behavior of this detrimental phenomenon. This behavior is interpreted in terms of competing single- and multiple-carrier processes of Si-H bond dissociation with the corresponding rates having the opposite temperature dependencies. One of the most important aspects relevant to the temperature behavior of HCD is the bond vibrational life-time which decreases with the temperature.
{"title":"On the temperature behavior of hot-carrier degradation","authors":"S. Tyaginov, M. Jech, P. Sharma, J. Franco, B. Kaczer, T. Grasser","doi":"10.1109/IIRW.2015.7437088","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437088","url":null,"abstract":"We show that - in contrast to previous findings - hot-carrier degradation (HCD) in scaled nMOSFETs with a channel length of 44 nm appears to be weaker at elevated temperatures. However, the distance between degradation traces obtained at 25 and 75° C reduces as the stress voltages increase and at a certain voltage the changes of the linear drain current measured at 25 and 75° C are almost identical in the entire stress time window. We apply our physics-based model for hot-carrier degradation to analyze the temperature behavior of this detrimental phenomenon. This behavior is interpreted in terms of competing single- and multiple-carrier processes of Si-H bond dissociation with the corresponding rates having the opposite temperature dependencies. One of the most important aspects relevant to the temperature behavior of HCD is the bond vibrational life-time which decreases with the temperature.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127163755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437061
Jiezhi Chen, Y. Mitani
In this work, random telegraph signal noise (RTN) is comparatively investigated in HfSiON and HfLaSiON n-type field effect transistors (nFETs) for further understandings on impacts of La incorporation in high-k devices. Constant bias RTN (cRTN) and transient RTN (tRTN) are characterized in detail, including carrier trapping time constants, gate bias couplings of time constant ratios, and carrier trapping/de-trapping induced channel current fluctuations or recoveries. On the one side, in comparison to HfSiON nFETs, it is observed that there exist fewer low energy traps by La incorporation, as well as smaller channel current fluctuations. On the other side, using tRTN measurements, more traps with high energies are observed in HfLaSiON nFETs, which could explain worse PBTI properties in HfLaSiON nFETs under high electric field. Underlying physical mechanisms are also discussed.
{"title":"Further understandings on impacts of La incorporation in HfSiON/TiN nFETs through comprehensive random telegraph noise characterizations","authors":"Jiezhi Chen, Y. Mitani","doi":"10.1109/IIRW.2015.7437061","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437061","url":null,"abstract":"In this work, random telegraph signal noise (RTN) is comparatively investigated in HfSiON and HfLaSiON n-type field effect transistors (nFETs) for further understandings on impacts of La incorporation in high-k devices. Constant bias RTN (cRTN) and transient RTN (tRTN) are characterized in detail, including carrier trapping time constants, gate bias couplings of time constant ratios, and carrier trapping/de-trapping induced channel current fluctuations or recoveries. On the one side, in comparison to HfSiON nFETs, it is observed that there exist fewer low energy traps by La incorporation, as well as smaller channel current fluctuations. On the other side, using tRTN measurements, more traps with high energies are observed in HfLaSiON nFETs, which could explain worse PBTI properties in HfLaSiON nFETs under high electric field. Underlying physical mechanisms are also discussed.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121202654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437073
C. Schlunder, F. Proebster, J. Berthold, W. Gustin, H. Reisinger
NBTI parameter degradation of MOSFETs shows a statistical variation. The distribution of the threshold voltage Vth after NBTI stress originates from a convolution of the distribution of the virgin devices together with the additional distribution of the NBTI degradation itself. The variability of the Vth (and other electrical parameters) of the virgin devices bases on process induced fluctuations of dopant atoms, oxide thickness, channel length, etc. The dependence on the transistor size is proven by several publications [e.g. 1,2]. The variability of the NBTI parameter degradation itself and the convolution is not fully understood yet and need further investigation. In this paper we investigate the dependency of the NBTI variability of Vth on the transistor size and geometry. For the necessary statistical relevance we perform NBTI stress experiments with the help of a smart array test-structure at a large amount of pMOS devices with various geometries. We show that the variability of pMOSFETs after NBTI depends not only on the size of the active area (w×l) but also on its geometry (w/l).
{"title":"Influence of MOSFET geometry on the statistical distribution of NBTI induced parameter degradation","authors":"C. Schlunder, F. Proebster, J. Berthold, W. Gustin, H. Reisinger","doi":"10.1109/IIRW.2015.7437073","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437073","url":null,"abstract":"NBTI parameter degradation of MOSFETs shows a statistical variation. The distribution of the threshold voltage Vth after NBTI stress originates from a convolution of the distribution of the virgin devices together with the additional distribution of the NBTI degradation itself. The variability of the Vth (and other electrical parameters) of the virgin devices bases on process induced fluctuations of dopant atoms, oxide thickness, channel length, etc. The dependence on the transistor size is proven by several publications [e.g. 1,2]. The variability of the NBTI parameter degradation itself and the convolution is not fully understood yet and need further investigation. In this paper we investigate the dependency of the NBTI variability of Vth on the transistor size and geometry. For the necessary statistical relevance we perform NBTI stress experiments with the help of a smart array test-structure at a large amount of pMOS devices with various geometries. We show that the variability of pMOSFETs after NBTI depends not only on the size of the active area (w×l) but also on its geometry (w/l).","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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