Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437079
K. Beckmann, J. Holt, N. Cady, J. V. Van Nostrand
Resistive random access memory (ReRAM) is a novel form of non-volatile memory expected to replace FLASH memory in the near future. To optimize the switching parameters of ReRAM we investigated fab-friendly HfOx based devices with an either amorphous or crystalline active layers. Our devices are fabricated with a copper bottom electrode, a 50 nm sub-stoichiometric hafnia layer, and a platinum top electrode. These devices operate according to the electrochemical metallization model. We compared endurance, reliability and random telegraph noise (RTN) with pulse-based cycling/readout. Initial endurance measurements show 4 million and 70 million consecutive cycles for the amorphous and crystalline hafnia, respectively. The transmission rate was shown to be slightly higher for the amorphous active layer with a confidence of 85%. Furthermore, it is shown that the relative difference in resistance during RTN is not dependent on the crystallinity, but increases with an increase in high resistive state. A high variety of noise patterns were observed, including transition rates from 1 s-1 up to 12000 s-1 and multi-state traps.
{"title":"Comparison of random telegraph noise, endurance and reliability in amorphous and crystalline hafnia-based ReRAM","authors":"K. Beckmann, J. Holt, N. Cady, J. V. Van Nostrand","doi":"10.1109/IIRW.2015.7437079","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437079","url":null,"abstract":"Resistive random access memory (ReRAM) is a novel form of non-volatile memory expected to replace FLASH memory in the near future. To optimize the switching parameters of ReRAM we investigated fab-friendly HfOx based devices with an either amorphous or crystalline active layers. Our devices are fabricated with a copper bottom electrode, a 50 nm sub-stoichiometric hafnia layer, and a platinum top electrode. These devices operate according to the electrochemical metallization model. We compared endurance, reliability and random telegraph noise (RTN) with pulse-based cycling/readout. Initial endurance measurements show 4 million and 70 million consecutive cycles for the amorphous and crystalline hafnia, respectively. The transmission rate was shown to be slightly higher for the amorphous active layer with a confidence of 85%. Furthermore, it is shown that the relative difference in resistance during RTN is not dependent on the crystallinity, but increases with an increase in high resistive state. A high variety of noise patterns were observed, including transition rates from 1 s-1 up to 12000 s-1 and multi-state traps.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124158672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437078
A. P. Nguyen, Ulrike Luders, F. Voiron
In this paper, we study the impact of electrical and thermal stress on line loss and characteristic impedance of a CoPlanar Waveguides (CPWs). The de-rating of the line propagation constants and impedance characteristic are analyzed and discussed with respect to the stress level applied to the dielectric. The physical mechanisms leading to dielectric properties variation is explained.
{"title":"Study of the impact of dielectric aging on coplanar waveguide performance","authors":"A. P. Nguyen, Ulrike Luders, F. Voiron","doi":"10.1109/IIRW.2015.7437078","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437078","url":null,"abstract":"In this paper, we study the impact of electrical and thermal stress on line loss and characteristic impedance of a CoPlanar Waveguides (CPWs). The de-rating of the line propagation constants and impedance characteristic are analyzed and discussed with respect to the stress level applied to the dielectric. The physical mechanisms leading to dielectric properties variation is explained.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132485803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437089
Cherifa Tahanout, H. Tahi, M. Boubaaya, B. Djezzar, M. Marah, B. Nadji, N. Saoula
In this paper, we investigated the magnetic field impact on negative bias temperature instability (NBTI) of commercial power double diffused MOS transistor (VDMOS), using the charge pumping method (CP). We reported that both NBTI induce -interface and- oxide traps are reduced by applying the magnetic field. However, the dynamic of interface trap during the recovery phase is not affected. While, the recovery of oxide trap is accelerated by applied magnetic field.
{"title":"NBTI stress on power VDMOS transistors under low magnetic field","authors":"Cherifa Tahanout, H. Tahi, M. Boubaaya, B. Djezzar, M. Marah, B. Nadji, N. Saoula","doi":"10.1109/IIRW.2015.7437089","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437089","url":null,"abstract":"In this paper, we investigated the magnetic field impact on negative bias temperature instability (NBTI) of commercial power double diffused MOS transistor (VDMOS), using the charge pumping method (CP). We reported that both NBTI induce -interface and- oxide traps are reduced by applying the magnetic field. However, the dynamic of interface trap during the recovery phase is not affected. While, the recovery of oxide trap is accelerated by applied magnetic field.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437090
B. McGowan, J. Lloyd, A. M. Kennedy
The magnitude of the negative magnetoresistance (MR) effect found in the low-k dielectric SiCOH is found to decrease with time on electrical bias and temperature stress (BTS). The MR decay fits an exponential function reasonably well such that the time constant of the fit can be used to compare decays due to different BTS conditions. Higher voltages and higher temperatures are observed to decay more rapidly than relatively lower voltages and temperatures. The time constant of the decay varies with voltage such that it fits a power law with an exponent of about 30 which bears resemblance to the voltage dependence of TDDB time to failure experiments conducted with SiCOH. Assuming an Arrhenius temperature relation, the decay has an activation energy of about 0.3 eV. The apparent activation energy displays a weak dependence on the electric field applied to the device.
{"title":"Decay of magnetoresistance in a low-k dielectric upon application of electrical bias and temperature stress","authors":"B. McGowan, J. Lloyd, A. M. Kennedy","doi":"10.1109/IIRW.2015.7437090","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437090","url":null,"abstract":"The magnitude of the negative magnetoresistance (MR) effect found in the low-k dielectric SiCOH is found to decrease with time on electrical bias and temperature stress (BTS). The MR decay fits an exponential function reasonably well such that the time constant of the fit can be used to compare decays due to different BTS conditions. Higher voltages and higher temperatures are observed to decay more rapidly than relatively lower voltages and temperatures. The time constant of the decay varies with voltage such that it fits a power law with an exponent of about 30 which bears resemblance to the voltage dependence of TDDB time to failure experiments conducted with SiCOH. Assuming an Arrhenius temperature relation, the decay has an activation energy of about 0.3 eV. The apparent activation energy displays a weak dependence on the electric field applied to the device.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127986906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437074
D. Nouguier, M. Rafik, X. Federspiel, G. Ghibaudo
In this paper, we present a statistical analysis of recoverable and permanent NBTI components. Measurements are performed on PFET devices issued from ST Microelectronics 28nm FDSOI technology, covering a wide range of device dimensions W and L. We analyzed NBTI degradation and recovery measured at μs time scale, resulting from AC and DC stress. We were able to confront VTh drift variability during stress and relaxation phase and evidence significant differences of variability between stress and relaxation phase.
{"title":"Comparison between recoverable and permanent NBTI variability components","authors":"D. Nouguier, M. Rafik, X. Federspiel, G. Ghibaudo","doi":"10.1109/IIRW.2015.7437074","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437074","url":null,"abstract":"In this paper, we present a statistical analysis of recoverable and permanent NBTI components. Measurements are performed on PFET devices issued from ST Microelectronics 28nm FDSOI technology, covering a wide range of device dimensions W and L. We analyzed NBTI degradation and recovery measured at μs time scale, resulting from AC and DC stress. We were able to confront VTh drift variability during stress and relaxation phase and evidence significant differences of variability between stress and relaxation phase.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437057
S. Deora
In this work, the important resistive switching memory (RRAM) parameter tunability is studied in DC and AC switching mode. The tradeoff between these parameters for optimized switching are assessed. The variability in low (LRS) and high (HRS) resistance states in each consecutive pulse SET/RESET cycle is studied. It is found that HRS and LRS read current follow the log-normal and normal distributions, respectively. Endurance test from 1million switching cycles demonstrates that in a small percentage of cycles the set operation may fail, which might be missed if not all the HRS and LRS values are read.
{"title":"Reliability challenges in resistive switching memories technology","authors":"S. Deora","doi":"10.1109/IIRW.2015.7437057","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437057","url":null,"abstract":"In this work, the important resistive switching memory (RRAM) parameter tunability is studied in DC and AC switching mode. The tradeoff between these parameters for optimized switching are assessed. The variability in low (LRS) and high (HRS) resistance states in each consecutive pulse SET/RESET cycle is studied. It is found that HRS and LRS read current follow the log-normal and normal distributions, respectively. Endurance test from 1million switching cycles demonstrates that in a small percentage of cycles the set operation may fail, which might be missed if not all the HRS and LRS values are read.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116681842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437077
Y. Tkachev
The processes of trap generation and electron trapping in the tunnel oxide of SuperFlash memory cells have been analyzed. The strongly non-uniform distribution of electric field in the SuperFlash cell allowed us to rule out the electron- or hole-related mechanisms of trap generation. The experimental results of single-trap-induced modulation of the tunneling rate, and the analysis of field and potential distribution in the tunnel oxide, point to the high electric field as a direct cause of electron-trap generation.
{"title":"Field-induced generation of electron traps in the tunnel oxide of flash memory cells","authors":"Y. Tkachev","doi":"10.1109/IIRW.2015.7437077","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437077","url":null,"abstract":"The processes of trap generation and electron trapping in the tunnel oxide of SuperFlash memory cells have been analyzed. The strongly non-uniform distribution of electric field in the SuperFlash cell allowed us to rule out the electron- or hole-related mechanisms of trap generation. The experimental results of single-trap-induced modulation of the tunneling rate, and the analysis of field and potential distribution in the tunnel oxide, point to the high electric field as a direct cause of electron-trap generation.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437056
T. Marquart
As NAND flash memories have scaled the margin between NAND capability and system requirements have been significantly reduced. Understanding Solid-State-Drive (SSD) reliability and qualification requirements has become more critical since these impact the NAND flash design tradeoffs. Unrealistically high expectations result in excessive margin that could have been used in other areas, while too low of a requirement puts the system at risk for excessive field failure. The reliability and qualification requirements for SSDs will be reviewed and discussed in order to give an overview of what constitutes an effective qualification/reliability strategy for SSDs.
{"title":"Solid-State-Drive qualification and reliability strategy","authors":"T. Marquart","doi":"10.1109/IIRW.2015.7437056","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437056","url":null,"abstract":"As NAND flash memories have scaled the margin between NAND capability and system requirements have been significantly reduced. Understanding Solid-State-Drive (SSD) reliability and qualification requirements has become more critical since these impact the NAND flash design tradeoffs. Unrealistically high expectations result in excessive margin that could have been used in other areas, while too low of a requirement puts the system at risk for excessive field failure. The reliability and qualification requirements for SSDs will be reviewed and discussed in order to give an overview of what constitutes an effective qualification/reliability strategy for SSDs.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437063
J. Robertson, Yuzheng Guo
To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First, we discuss traps in HfO2-based Si gate stacks and their reliability.
{"title":"Oxide defects and reliability of high K/Ge and III–V based gate stacks","authors":"J. Robertson, Yuzheng Guo","doi":"10.1109/IIRW.2015.7437063","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437063","url":null,"abstract":"To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First, we discuss traps in HfO2-based Si gate stacks and their reliability.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124379538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437058
J. Ocker, S. Slesazeck, A. Skouris, R. Srowik, S. Buschbeck, S. Günther, R. Hoffmann, V. Beyer, T. Mikolajick
The polarity-dependent device degradation during AC stress of polysicilicon-oxide-nitride-oxide-silicon (SONOS) transistor poses considerable reliability challenges for scaled SONOS gate oxide thicknesses. However, the mechanism responsible for the endurance degradation has been scarcely studied so far. Especially electrons injected from the gate are supposed to be responsible for the degradation. An on-chip test circuit was developed to measure those gate currents. A clear correlation was found with retention-after-cycling experiments and interface degradation measured with the pulsed-capacitance technique. Based on the results, defect generation in the tunnel oxide was identified as the main degradation mechanism. The results are supported by electrical simulation of the transient behavior of the SONOS gate dielectric during program and erase.
{"title":"Investigation of the reliability degradation of scaled SONOS memory transistors","authors":"J. Ocker, S. Slesazeck, A. Skouris, R. Srowik, S. Buschbeck, S. Günther, R. Hoffmann, V. Beyer, T. Mikolajick","doi":"10.1109/IIRW.2015.7437058","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437058","url":null,"abstract":"The polarity-dependent device degradation during AC stress of polysicilicon-oxide-nitride-oxide-silicon (SONOS) transistor poses considerable reliability challenges for scaled SONOS gate oxide thicknesses. However, the mechanism responsible for the endurance degradation has been scarcely studied so far. Especially electrons injected from the gate are supposed to be responsible for the degradation. An on-chip test circuit was developed to measure those gate currents. A clear correlation was found with retention-after-cycling experiments and interface degradation measured with the pulsed-capacitance technique. Based on the results, defect generation in the tunnel oxide was identified as the main degradation mechanism. The results are supported by electrical simulation of the transient behavior of the SONOS gate dielectric during program and erase.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123578117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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