Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415743
K. Natarajan, S. Arun, K. Murugaraj, M. John
This work proposes the implementation of an energy efficient application specific matrix processor for speech enhancement in noisy speech recognition applications. This implementation considers speech enhancement through signal subspace based speech enhancement algorithm based on Frobenius norm constrained Singular Value Decomposition. The Singular Value Decomposition unit is used in time multiplexed fashion to perform noise reduction during feature extraction stage and it is also used for matrix inversion of the block diagonal covariance matrices for the final speech recognition block. This processor along with a 4 state Continuous Hidden Markov Model based hardware speech recognizer achieves a recognition performance improvement of 5% in noisy environments. Word samples from AN4 database is used to test the speech recognizer which has got a recognition accuracy of 96.8%. The FPGA prototyping of the above noise enhancement algorithm using the ASIP accelerator was carried out in Altera FPGA with NIOS processor.
{"title":"An application specific matrix processor for signal subspace based speech enhancement in noise robust speech recognition applications","authors":"K. Natarajan, S. Arun, K. Murugaraj, M. John","doi":"10.1109/ICASIC.2007.4415743","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415743","url":null,"abstract":"This work proposes the implementation of an energy efficient application specific matrix processor for speech enhancement in noisy speech recognition applications. This implementation considers speech enhancement through signal subspace based speech enhancement algorithm based on Frobenius norm constrained Singular Value Decomposition. The Singular Value Decomposition unit is used in time multiplexed fashion to perform noise reduction during feature extraction stage and it is also used for matrix inversion of the block diagonal covariance matrices for the final speech recognition block. This processor along with a 4 state Continuous Hidden Markov Model based hardware speech recognizer achieves a recognition performance improvement of 5% in noisy environments. Word samples from AN4 database is used to test the speech recognizer which has got a recognition accuracy of 96.8%. The FPGA prototyping of the above noise enhancement algorithm using the ASIP accelerator was carried out in Altera FPGA with NIOS processor.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130390465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415822
Jinghong Liang, Xianlong Hong, Tong Jing
With the progress of very large scale integration, using traditional global routing algorithms to solve multi-layer routing problem causes the routing resource waste of lower layers or the lack of higher layers because the pitch size is different in different layer pairs and traditional algorithms use uniform pitch size for all layer pairs. The paper presents a global routing algorithm that performs layer assignment before routing. This algorithm is based on a new flow for multi-layer routing, and uses bounding box of the nets to estimate the congestion, and distributes them to different layer pairs based on the aim of even congestion. The algorithm has been implemented and tested. The experimental results show that the algorithm is more effective.
{"title":"A new multi-layer global routing flow for congestion elimination","authors":"Jinghong Liang, Xianlong Hong, Tong Jing","doi":"10.1109/ICASIC.2007.4415822","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415822","url":null,"abstract":"With the progress of very large scale integration, using traditional global routing algorithms to solve multi-layer routing problem causes the routing resource waste of lower layers or the lack of higher layers because the pitch size is different in different layer pairs and traditional algorithms use uniform pitch size for all layer pairs. The paper presents a global routing algorithm that performs layer assignment before routing. This algorithm is based on a new flow for multi-layer routing, and uses bounding box of the nets to estimate the congestion, and distributes them to different layer pairs based on the aim of even congestion. The algorithm has been implemented and tested. The experimental results show that the algorithm is more effective.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115237075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415887
Quang Dinh, Y. Bresler, Deming Chen
Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with fie Id-program m able gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.
{"title":"Hardware acceleration for sparse fourier image reconstruction","authors":"Quang Dinh, Y. Bresler, Deming Chen","doi":"10.1109/ICASIC.2007.4415887","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415887","url":null,"abstract":"Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with fie Id-program m able gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114338573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415867
Xin Zhang, Dunshan Yu, Shimin Sheng
In this paper, a behavior-oriented simulation tool is proposed for the designing and optimizing of sigma-delta ADCs. We show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system design. The imperfections of the analog cells as integrators, comparator, and the CpAMPs are analyzed in detail, which guides the design towards high performance. Besides, the modeling, simulation, and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool. A peak SNR of 91.5 dB, a 15 bit resolution, and a 57 m W power dissipation are obtained through HSPICE simulation. Currently chip is in the fabrication phase.
本文提出了一种面向行为的仿真工具，用于sigma-delta adc的设计和优化。我们展示了如何在混合信号系统设计的自上而下的设计流程中使用这种仿真工具。详细分析了模拟单元作为积分器、比较器和camp的不足之处，指导了模拟单元的高性能设计。此外，通过对二阶σ - δ调制器的建模、仿真和设计，验证了仿真工具的有效性。通过HSPICE仿真得到的峰值信噪比为91.5 dB，分辨率为15位，功耗为57 m W。目前芯片还处于制造阶段。
{"title":"A behavior-oriented simulation tool for design and optimization of sigma-delta ADCs","authors":"Xin Zhang, Dunshan Yu, Shimin Sheng","doi":"10.1109/ICASIC.2007.4415867","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415867","url":null,"abstract":"In this paper, a behavior-oriented simulation tool is proposed for the designing and optimizing of sigma-delta ADCs. We show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system design. The imperfections of the analog cells as integrators, comparator, and the CpAMPs are analyzed in detail, which guides the design towards high performance. Besides, the modeling, simulation, and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool. A peak SNR of 91.5 dB, a 15 bit resolution, and a 57 m W power dissipation are obtained through HSPICE simulation. Currently chip is in the fabrication phase.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"640 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116085442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415581
Muhua Han, Yufeng Xie, Leibo Liu, Shaojun Wei
Nowadays, multi-objective hierarchical design methodology has received more attention for its applicability to deal with complex SOC design. Reducing decision data across hierarchy levels is crucial to the hierarchical designs. However, previous works overlooked the importance of this feature and just nested the optimizing procedures of multiple levels. This paper discussed the way to compress decision data across hierarchical levels. Pareto-optimal theory was employed and developed to explore the design space of multi-objective hierarchical system. Furthermore, this paper proved that, under the independence condition, optimization in each hierarchical level could be performed independently. This is the very first time to explore the design space of multi-objective hierarchical system formally, which contributes to the promotion of novel hierarchical partition and synthesis methodology.
{"title":"Design space exploration in multi-objective hierarchical SOC design","authors":"Muhua Han, Yufeng Xie, Leibo Liu, Shaojun Wei","doi":"10.1109/ICASIC.2007.4415581","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415581","url":null,"abstract":"Nowadays, multi-objective hierarchical design methodology has received more attention for its applicability to deal with complex SOC design. Reducing decision data across hierarchy levels is crucial to the hierarchical designs. However, previous works overlooked the importance of this feature and just nested the optimizing procedures of multiple levels. This paper discussed the way to compress decision data across hierarchical levels. Pareto-optimal theory was employed and developed to explore the design space of multi-objective hierarchical system. Furthermore, this paper proved that, under the independence condition, optimization in each hierarchical level could be performed independently. This is the very first time to explore the design space of multi-objective hierarchical system formally, which contributes to the promotion of novel hierarchical partition and synthesis methodology.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124738173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415831
Yufeng Zhu, Jun Lu, Z. J. Wu, L. Zhao, Yifei Shen, Xiaoou Tang, F. Huang
In this paper, we present a wide-band inductor model that contains lateral substrate resistance and capacitance. In order to model the non-linear features of substrate characteristic functions, we add a novel substrate parasitic inductance to the model. The extraction is carried out using a set of characteristic functions derived from equivalent circuit without iterative optimization. As verified by a series of inductors fabricated with a 0.18 um CMOS process, the model accurately predicts the equivalent series resistance and inductance over a wide frequency range.
在本文中，我们提出了一个包含横向基板电阻和电容的宽带电感模型。为了模拟衬底特征函数的非线性特征，我们在模型中加入了一种新的衬底寄生电感。利用等效电路导出的一组特征函数进行提取，无需迭代优化。采用0.18 um CMOS工艺制作的一系列电感验证了该模型在较宽的频率范围内准确地预测了等效串联电阻和电感。
{"title":"A novel equivalent circuit and parameter extraction for on-chip spiral inductors","authors":"Yufeng Zhu, Jun Lu, Z. J. Wu, L. Zhao, Yifei Shen, Xiaoou Tang, F. Huang","doi":"10.1109/ICASIC.2007.4415831","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415831","url":null,"abstract":"In this paper, we present a wide-band inductor model that contains lateral substrate resistance and capacitance. In order to model the non-linear features of substrate characteristic functions, we add a novel substrate parasitic inductance to the model. The extraction is carried out using a set of characteristic functions derived from equivalent circuit without iterative optimization. As verified by a series of inductors fabricated with a 0.18 um CMOS process, the model accurately predicts the equivalent series resistance and inductance over a wide frequency range.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123654342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415718
Weidong Yang, Ruzhang Li, Yong Liu, Yonghui Yang, Kaicheng Li
In this paper, the circuit implementation principle, circuit design characteristic and process technology characteristic for a 12-bit voltage output D/A converter with internal reference were described. By using analog unit circuits such as the R-2R resistance switch network optimized in design, the temperature compensation Zener reference voltage, and the BiCMOS output operational amplifier with JFET input, combined with SISC" p-well 3 um LC2MOS process technology, a 12-bit D/A converter was developed. The converter features high conversion resolution, small linear and differential error, low power consumption, fast conversion speed, ease of use, etc.
{"title":"Investigation into the 12-bit DA converter","authors":"Weidong Yang, Ruzhang Li, Yong Liu, Yonghui Yang, Kaicheng Li","doi":"10.1109/ICASIC.2007.4415718","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415718","url":null,"abstract":"In this paper, the circuit implementation principle, circuit design characteristic and process technology characteristic for a 12-bit voltage output D/A converter with internal reference were described. By using analog unit circuits such as the R-2R resistance switch network optimized in design, the temperature compensation Zener reference voltage, and the BiCMOS output operational amplifier with JFET input, combined with SISC\" p-well 3 um LC2MOS process technology, a 12-bit D/A converter was developed. The converter features high conversion resolution, small linear and differential error, low power consumption, fast conversion speed, ease of use, etc.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121562970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IEEE 802.11 b and g standards, which are compatible with each other, are combined to provide higher-performance wireless communication with more options of data rates. In order to meet the upgrading demands of 802.11 standards and other standards using DSSS and OFDM as the pivotal algorithms of physical-layer parts, a SOC (or ASIC+DSP) solution is used to realize the baseband system. The paper firstly introduces the features of the 802.11 b/g PHY, and then gives the architecture and layout of BX501, the chip designed and taped out in SMIC 0.18-micron technology. The paper also presents the testing results that prove the chip can fulfill the modulation/demodulation functions of the 802.11 b/g PHY. At last, a conclusion is made that points out the importance of system-level verification.
{"title":"Design, implementation and testing of an IEEE 802.11 b/g baseband chip","authors":"Yuzhong Jiao, Xin'an Wang, Gaofa Xiao, Hongying Chen","doi":"10.1109/ICASIC.2007.4415785","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415785","url":null,"abstract":"IEEE 802.11 b and g standards, which are compatible with each other, are combined to provide higher-performance wireless communication with more options of data rates. In order to meet the upgrading demands of 802.11 standards and other standards using DSSS and OFDM as the pivotal algorithms of physical-layer parts, a SOC (or ASIC+DSP) solution is used to realize the baseband system. The paper firstly introduces the features of the 802.11 b/g PHY, and then gives the architecture and layout of BX501, the chip designed and taped out in SMIC 0.18-micron technology. The paper also presents the testing results that prove the chip can fulfill the modulation/demodulation functions of the 802.11 b/g PHY. At last, a conclusion is made that points out the importance of system-level verification.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113957280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415618
Zhen Liu, Y. Wang, S. Jia, L. Ji, Xing Zhang
A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65 mW at a 3.3 V supply.
{"title":"Low-power CMOS folding and interpolating ADC with a fully-folding technique","authors":"Zhen Liu, Y. Wang, S. Jia, L. Ji, Xing Zhang","doi":"10.1109/ICASIC.2007.4415618","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415618","url":null,"abstract":"A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65 mW at a 3.3 V supply.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114974920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415635
J. Zheng, P. Ren, C. C. Shao, Yi Yang, Juncheng Wang, Wei Li, Chinglong Lin, Yuhua Cheng, Yangyuan Wang
In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. The proposed SSCG with a third-order sigma-delta modulator can generate clocks with center spread ratios of 0.25%, 1%, 1.75%, 2.5%, 3.5%, 5% and down spread ratios of 0.5%, 2%, 3.5%, 5%, 7%, 10%. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Measurements show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 M with center spread ratio of 5% can be achieved which have a good agreement with the theoretical calculations.
提出了一种三角形调制扩频时钟发生器(SSCG)。采用三阶σ - δ调制器的SSCG可以产生中心扩展比为0.25%、1%、1.75%、2.5%、3.5%、5%和下扩展比为0.5%、2%、3.5%、5%、7%、10%的时钟。SSCG采用中芯0.13 um CMOS工艺在芯片上实现。测量结果表明，在80 MHz和133.3 M频段，下展比分别为10%和12.98 dB, EMI的衰减与理论计算结果吻合较好。
{"title":"A Programmable Spread Spectrum Clock Generation","authors":"J. Zheng, P. Ren, C. C. Shao, Yi Yang, Juncheng Wang, Wei Li, Chinglong Lin, Yuhua Cheng, Yangyuan Wang","doi":"10.1109/ICASIC.2007.4415635","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415635","url":null,"abstract":"In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. The proposed SSCG with a third-order sigma-delta modulator can generate clocks with center spread ratios of 0.25%, 1%, 1.75%, 2.5%, 3.5%, 5% and down spread ratios of 0.5%, 2%, 3.5%, 5%, 7%, 10%. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Measurements show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 M with center spread ratio of 5% can be achieved which have a good agreement with the theoretical calculations.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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