Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415751
Jun Wang, Shen Li, K. Shimizu, T. Ikenaga, S. Goto
As an efficient error resilient tool in H.264, FMO (Flexible Macroblock Ordering) still has 2 disadvantages: (1) unacceptable bitrate overhead, and (2) unsuitable for widely used UEP (unequal error protected) transmission. In this paper, to overcome these 2 disadvantages, a dynamic FMO classification (DFMOC) is proposed. For disadvantage(l), in DFMOC since lots of MBs in the same slice are placed together, thus the bitrate overhead is smaller. For disadvantage^), DFMOC generates 2 slices and each of them takes unequal priority in transmission by the large and small motion area extraction. After employing LDPC coding for UEP transmission strategy, experiment shows DFMOC has a better error robustness while still keeps less bitrate overhead compared with traditional FMO mode: the PSNR has 1 to 2 db outperforming and the bitrate overhead keeps no more than 5% which is about a half of traditional FMO overhead.
{"title":"Unequal error protected transmission with dynamic classification in H.264/AVC","authors":"Jun Wang, Shen Li, K. Shimizu, T. Ikenaga, S. Goto","doi":"10.1109/ICASIC.2007.4415751","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415751","url":null,"abstract":"As an efficient error resilient tool in H.264, FMO (Flexible Macroblock Ordering) still has 2 disadvantages: (1) unacceptable bitrate overhead, and (2) unsuitable for widely used UEP (unequal error protected) transmission. In this paper, to overcome these 2 disadvantages, a dynamic FMO classification (DFMOC) is proposed. For disadvantage(l), in DFMOC since lots of MBs in the same slice are placed together, thus the bitrate overhead is smaller. For disadvantage^), DFMOC generates 2 slices and each of them takes unequal priority in transmission by the large and small motion area extraction. After employing LDPC coding for UEP transmission strategy, experiment shows DFMOC has a better error robustness while still keeps less bitrate overhead compared with traditional FMO mode: the PSNR has 1 to 2 db outperforming and the bitrate overhead keeps no more than 5% which is about a half of traditional FMO overhead.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415666
Sun-Bo Woo, Jae-Hun Jung, K. Kwack
A novel design for a low-power DC-DC converter using high-efficiency charge pump circuits is proposed. It uses a gate pumping circuit to decrease the conduction power loss of the charge pump circuit. The output voltage and current of the proposed DC-DC converter consisting of five charge pump circuits operating at 3.3 V are 18 V and 100 muA. The power efficiency and the ripple voltage of the designed charge pump circuits are 82.3% and 20 mV.
{"title":"Novel low-power DC-DC converter with high-efficiency charge pump circuits","authors":"Sun-Bo Woo, Jae-Hun Jung, K. Kwack","doi":"10.1109/ICASIC.2007.4415666","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415666","url":null,"abstract":"A novel design for a low-power DC-DC converter using high-efficiency charge pump circuits is proposed. It uses a gate pumping circuit to decrease the conduction power loss of the charge pump circuit. The output voltage and current of the proposed DC-DC converter consisting of five charge pump circuits operating at 3.3 V are 18 V and 100 muA. The power efficiency and the ripple voltage of the designed charge pump circuits are 82.3% and 20 mV.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126361327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415694
S. Song, Guoping Yan, Hua Cao
A new CMOS electronically tunable current conveyor (ECCII) based on translinear circuits is presented, with low power voltage (plusmn1.2 V) and continuous programmable current gain and highly linear wide tuning range. The current transfer ratio of the conveyor can be accurately controlled by the ratio of the DC bias currents. HSPICE simulation results using 0.35-mum CMOS process model confirm the expected good performance of the proposed ECCII in terms of linearity, frequency response and tunability.
提出了一种新型的基于跨线性电路的CMOS电子可调谐电流输送机(ECCII)，具有低功率电压(±1.2 V)、连续可编程电流增益和高线性宽调谐范围的特点。通过直流偏置电流的比值可以精确地控制输送机的电流传递比。采用0.35 μ m CMOS工艺模型的HSPICE仿真结果证实了所提出的ECCII在线性度、频率响应和可调性方面的良好性能。
{"title":"A new CMOS electronically tunable current conveyor based on translinear circuits","authors":"S. Song, Guoping Yan, Hua Cao","doi":"10.1109/ICASIC.2007.4415694","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415694","url":null,"abstract":"A new CMOS electronically tunable current conveyor (ECCII) based on translinear circuits is presented, with low power voltage (plusmn1.2 V) and continuous programmable current gain and highly linear wide tuning range. The current transfer ratio of the conveyor can be accurately controlled by the ratio of the DC bias currents. HSPICE simulation results using 0.35-mum CMOS process model confirm the expected good performance of the proposed ECCII in terms of linearity, frequency response and tunability.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125825711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415689
B. Han, Jianhui Wu, Chen Hu
A fully integrated low phase noise LC VCO with tail resistor for current control is presented using 0.35 mum SiGe BiCMOS technology. The structure is used to reduce noise of tail current source. The VCO has a tuning range of 480 MHz, from 2.32 GHz to 2.8 GHz and achieves low phase noise of -104.3 dBc/Hz and -124.3 dBc/Hz at 100 kHz and 1 MHz offset frequency from 2.5 GHz carrier. The oscillator draws 5 mA from 5 V supply voltage. The figure-of-merit (FOM) value at 2.5 GHz is around -178 dBc/Hz at the offset frequency of 100 kHz.
{"title":"A 2.5 GHz low phase noise LC VCO in 0.35μm SiGe BiCMOS technology","authors":"B. Han, Jianhui Wu, Chen Hu","doi":"10.1109/ICASIC.2007.4415689","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415689","url":null,"abstract":"A fully integrated low phase noise LC VCO with tail resistor for current control is presented using 0.35 mum SiGe BiCMOS technology. The structure is used to reduce noise of tail current source. The VCO has a tuning range of 480 MHz, from 2.32 GHz to 2.8 GHz and achieves low phase noise of -104.3 dBc/Hz and -124.3 dBc/Hz at 100 kHz and 1 MHz offset frequency from 2.5 GHz carrier. The oscillator draws 5 mA from 5 V supply voltage. The figure-of-merit (FOM) value at 2.5 GHz is around -178 dBc/Hz at the offset frequency of 100 kHz.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116087034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415600
K. Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, S. Goto
In this paper, an instruction-level power reduction model for the low power system-on-a-chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.
{"title":"Power reduction through specific instruction scheduling based on Hardware/Software Co-Design","authors":"K. Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, S. Goto","doi":"10.1109/ICASIC.2007.4415600","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415600","url":null,"abstract":"In this paper, an instruction-level power reduction model for the low power system-on-a-chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116153212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415885
Yansong Liu, N. Wong
We study model order reduction (MOR) of continuous-time linear time-varying (LTV) systems. Examples include circuit or interconnect models found in VLSI marco-modeling. Specifically, a time-varying version of positive-real balanced truncation (PRBT), called LTV-PRBT, is proposed, which preserves the passivity of LTV systems for stable global simulation. Implementation details are discussed together with a brief outline of a discrete-time counterpart of LTV-PRBT. Dynamically changing state dimension is allowed for accurate modeling at the lowest possible order. Numerical examples then verify the effectiveness of the proposed approach over existing LTV MOR methods.
{"title":"Passivity-preserving model order reduction of linear time-varying macromodels","authors":"Yansong Liu, N. Wong","doi":"10.1109/ICASIC.2007.4415885","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415885","url":null,"abstract":"We study model order reduction (MOR) of continuous-time linear time-varying (LTV) systems. Examples include circuit or interconnect models found in VLSI marco-modeling. Specifically, a time-varying version of positive-real balanced truncation (PRBT), called LTV-PRBT, is proposed, which preserves the passivity of LTV systems for stable global simulation. Implementation details are discussed together with a brief outline of a discrete-time counterpart of LTV-PRBT. Dynamically changing state dimension is allowed for accurate modeling at the lowest possible order. Numerical examples then verify the effectiveness of the proposed approach over existing LTV MOR methods.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115258787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415567
Zhaolin Li, Xinyue Zhang, Gongqiong Li, R. Zhou
A fully pipelined single-precision floating-point unit is proposed in this paper. It is implemented in three pipeline stages. The core of this design is a multiply-add-fused unit. With the assistance of a lookup table and the control logic, it also implements floating-point division and square root operations, besides the basic addition, subtraction and multiply-add-fused operations. It is modeled in VerilogHDL and synthesized in 0.18 mum CMOS technology after verification. Experiment result shows that there is only 3% time penalty compared with the traditional multiply-add-fused unit.
本文提出了一种全流水线的单精度浮点单元。它分三个管道阶段实现。这个设计的核心是一个多加融合单元。在查找表和控制逻辑的帮助下，除了基本的加法、减法和乘加运算外，还实现了浮点除法和平方根运算。采用VerilogHDL进行建模，经验证后采用0.18 μ m CMOS技术进行合成。实验结果表明，与传统的复加融合装置相比，该装置的时间损失仅为3%。
{"title":"Design of a fully pipelined single-precision floating-point unit","authors":"Zhaolin Li, Xinyue Zhang, Gongqiong Li, R. Zhou","doi":"10.1109/ICASIC.2007.4415567","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415567","url":null,"abstract":"A fully pipelined single-precision floating-point unit is proposed in this paper. It is implemented in three pipeline stages. The core of this design is a multiply-add-fused unit. With the assistance of a lookup table and the control logic, it also implements floating-point division and square root operations, besides the basic addition, subtraction and multiply-add-fused operations. It is modeled in VerilogHDL and synthesized in 0.18 mum CMOS technology after verification. Experiment result shows that there is only 3% time penalty compared with the traditional multiply-add-fused unit.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415584
Yingbo Hu, Zhaolin Li, R. Zhou
A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).
提出了一种新型的低阈值电压时钟晶体管脉冲触发真单相时钟触发器及其几种改进结构，用于高性能低功耗应用。由于低时钟摆幅和双边触发，时钟网络的功耗估计降低了78%。采用0.18 mm CMOS技术的HSPICE仿真结果表明，与现有的低摆幅时钟双边触发触发器(LSDFF)相比，它们的延迟、功耗和PDP分别降低了20~44%、40~56%和61~72%。
{"title":"a new type of high-performance low-power low clock-swing TSPC flip-flop","authors":"Yingbo Hu, Zhaolin Li, R. Zhou","doi":"10.1109/ICASIC.2007.4415584","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415584","url":null,"abstract":"A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415819
Zhonghua Jiang, N. Xu, Li Gao, Yuchun Ma, Xianlong Hong
Hierarchical design is employed in the floorplan for scaling to large number modules. The thermal problem has been emerged as one of the key issues for IC design. In this paper, we proposed an efficient hierarchical iterative Gauss-Seidel thermal model to guide the floorplan, which is an efficient algorithm that can reduce the run-time by speeding up the convergence with accurate estimation. Especially, the Gauss-Seidel Iteration is suitable for incremental temperature updating. Compared with inverting Matrix method, the iterative times of incremental Gauss-Seidel thermal model is approximate to 1/5 of the inverting Matrix method. Our method can be 5 times faster than that of the inverting Matrix method.
{"title":"Hierarchical thermal model using gauss-seidel method in floorplanning","authors":"Zhonghua Jiang, N. Xu, Li Gao, Yuchun Ma, Xianlong Hong","doi":"10.1109/ICASIC.2007.4415819","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415819","url":null,"abstract":"Hierarchical design is employed in the floorplan for scaling to large number modules. The thermal problem has been emerged as one of the key issues for IC design. In this paper, we proposed an efficient hierarchical iterative Gauss-Seidel thermal model to guide the floorplan, which is an efficient algorithm that can reduce the run-time by speeding up the convergence with accurate estimation. Especially, the Gauss-Seidel Iteration is suitable for incremental temperature updating. Compared with inverting Matrix method, the iterative times of incremental Gauss-Seidel thermal model is approximate to 1/5 of the inverting Matrix method. Our method can be 5 times faster than that of the inverting Matrix method.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116740856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415577
Wen-ting Zhang, Luofeng Geng, Duoli Zhang, Gaoming Du, Minglun Gao, Wei Zhang, Ning Hou, Yi-Hua Tang
To achieve a balance between high performance and energy efficiency, embedded systems often use heterogeneous multiprocessor platforms which tuned for a well defined application domain. Meanwhile FPGA is known for providing designers with several benefits in system design. One most important is high programmability and low risks. In this paper we demonstrate the design of an FPGA-based heterogeneous multiprocessor system integrating 4 Nios II soft cores and 1 ARM core. ARM core is the central controller of the whole system, and 4 Nios II cores are served as slaves, which are commanded by ARM core and responsible for processing regular and quantity data. ARM core and Nios II cores cooperate and work in parallel to accomplish each task. FPGA utilization of current implementation is 13% requiring 19,593 ALUTs on Altera Stratix II EP2S180.
为了在高性能和能源效率之间取得平衡，嵌入式系统通常使用异构多处理器平台，这些平台针对定义良好的应用领域进行了调优。同时，FPGA在系统设计中为设计人员提供了许多好处。最重要的一点是高可编程性和低风险。本文介绍了一个基于fpga的异构多处理器系统的设计，该系统集成了4个Nios II软核和1个ARM核。ARM内核作为整个系统的中央控制器，4个Nios II内核作为从机，由ARM内核指挥，负责处理常规和定量数据。ARM核心和Nios II核心协同工作，并行完成每项任务。当前实现的FPGA利用率为13%，在Altera Stratix II EP2S180上需要19,593个alut。
{"title":"Design of heterogeneous MPSoC on FPGA","authors":"Wen-ting Zhang, Luofeng Geng, Duoli Zhang, Gaoming Du, Minglun Gao, Wei Zhang, Ning Hou, Yi-Hua Tang","doi":"10.1109/ICASIC.2007.4415577","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415577","url":null,"abstract":"To achieve a balance between high performance and energy efficiency, embedded systems often use heterogeneous multiprocessor platforms which tuned for a well defined application domain. Meanwhile FPGA is known for providing designers with several benefits in system design. One most important is high programmability and low risks. In this paper we demonstrate the design of an FPGA-based heterogeneous multiprocessor system integrating 4 Nios II soft cores and 1 ARM core. ARM core is the central controller of the whole system, and 4 Nios II cores are served as slaves, which are commanded by ARM core and responsible for processing regular and quantity data. ARM core and Nios II cores cooperate and work in parallel to accomplish each task. FPGA utilization of current implementation is 13% requiring 19,593 ALUTs on Altera Stratix II EP2S180.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116757919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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