Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415808
H. Yamauchi
This paper describes what has been happening in SRAM scaling trend in terms of bit-cell size and operating voltage (Vdd) since 65 nm process generation. The key design solutions to extend a 6T SRAM lifetime are reviewed and discussed including a possible bit cell scaling trend comparing with an 8T SRAM as one of the successors. Each dependency of 3 key margins of write margin (WRM), static noise margin (SNM), and cell current (Icell) on the scaling ratio of Vdd and MOSFET channel feature size has been shown to clarify the real issues in the scaling. The bit cell area scaling trends of 6T and 8T SRAMs are predicted. It has been shown that the area of 6T will be getting closer to that of 8T at 32 nm and should cross over around 22 nm. In addition, design solutions to brake on runaway leakage increasing with scaling threshold voltage (Vt) and gate oxide thickness are reviewed and discussed.
{"title":"Embedded SRAM circuit design technologies for a 45nm and beyond","authors":"H. Yamauchi","doi":"10.1109/ICASIC.2007.4415808","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415808","url":null,"abstract":"This paper describes what has been happening in SRAM scaling trend in terms of bit-cell size and operating voltage (Vdd) since 65 nm process generation. The key design solutions to extend a 6T SRAM lifetime are reviewed and discussed including a possible bit cell scaling trend comparing with an 8T SRAM as one of the successors. Each dependency of 3 key margins of write margin (WRM), static noise margin (SNM), and cell current (Icell) on the scaling ratio of Vdd and MOSFET channel feature size has been shown to clarify the real issues in the scaling. The bit cell area scaling trends of 6T and 8T SRAMs are predicted. It has been shown that the area of 6T will be getting closer to that of 8T at 32 nm and should cross over around 22 nm. In addition, design solutions to brake on runaway leakage increasing with scaling threshold voltage (Vt) and gate oxide thickness are reviewed and discussed.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415699
S. Song, Guoping Yan, Hua Cao
This paper introduces a new operational transconductance amplifier (OTA) that maintains a highly linear wide continuous tuning range and wide frequency response range, enabled by splitting linear voltage-to-current conversion and tuning into two different blocks. The input differential pair assures a wide input voltage swing via a fixed bias current, and a programmable-gain current amplifier working in saturation region can assure over three decades Gm tuning range and 119 MHz bandwidth. With plusmn1.5 V supply voltages, HSPICE simulation results using TSMC 0.35-mum CMOS process model confirm the expected good performance of the proposed OTA.
{"title":"A highly linear wide range continuous tuning CMOS OTA","authors":"S. Song, Guoping Yan, Hua Cao","doi":"10.1109/ICASIC.2007.4415699","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415699","url":null,"abstract":"This paper introduces a new operational transconductance amplifier (OTA) that maintains a highly linear wide continuous tuning range and wide frequency response range, enabled by splitting linear voltage-to-current conversion and tuning into two different blocks. The input differential pair assures a wide input voltage swing via a fixed bias current, and a programmable-gain current amplifier working in saturation region can assure over three decades Gm tuning range and 119 MHz bandwidth. With plusmn1.5 V supply voltages, HSPICE simulation results using TSMC 0.35-mum CMOS process model confirm the expected good performance of the proposed OTA.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123184056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415782
Li Hongqin
This paper study a kind of design method about the digital decimation filter design for delta-Sigma ADC with high performance and validated it by simulation using MATLAB tool. A 16-bit digital decimation filter design for stereo audio delta-sigma ADC has been developed. A two-stage decimation filter architecture which can reduce digital switching noise was also introduced in this design. A merged four-stage comb filter is used for the first stage, and a bit-serial finite-impulse-response (FIR) filter is used for the second stage. In addition, a high pass filter is used to compensate filter's DC offset. The design simulated using MATLAB according to this scheme can achieve higher performances.
{"title":"Digital decimation filter design and simulation for delta-sigma ADC with high performance","authors":"Li Hongqin","doi":"10.1109/ICASIC.2007.4415782","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415782","url":null,"abstract":"This paper study a kind of design method about the digital decimation filter design for delta-Sigma ADC with high performance and validated it by simulation using MATLAB tool. A 16-bit digital decimation filter design for stereo audio delta-sigma ADC has been developed. A two-stage decimation filter architecture which can reduce digital switching noise was also introduced in this design. A merged four-stage comb filter is used for the first stage, and a bit-serial finite-impulse-response (FIR) filter is used for the second stage. In addition, a high pass filter is used to compensate filter's DC offset. The design simulated using MATLAB according to this scheme can achieve higher performances.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115788728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415848
Fan Bing, Wang Donghui, Zhang Tiejun, Hou Chaohuan
This paper introduces a behavioral simulation of an open loop architecture pipeline ADC. A behavioral model is developed in MATLAB/SIMULINK. The main error sources that affect the ADC are investigated and various non-idealities in an open loop architecture ADC, such as S/H bandwidth limitation, clock jitter, and interpolator gain mismatch, are analyzed. It also shows the impact of nonlinearities on the performance of the ADC. The results aid the design of open loop pipeline ADCs by providing a comprehensive set of design specifications that must be satisfied by each building block.
{"title":"Modeling and simulation of an open-loop architecture ADC","authors":"Fan Bing, Wang Donghui, Zhang Tiejun, Hou Chaohuan","doi":"10.1109/ICASIC.2007.4415848","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415848","url":null,"abstract":"This paper introduces a behavioral simulation of an open loop architecture pipeline ADC. A behavioral model is developed in MATLAB/SIMULINK. The main error sources that affect the ADC are investigated and various non-idealities in an open loop architecture ADC, such as S/H bandwidth limitation, clock jitter, and interpolator gain mismatch, are analyzed. It also shows the impact of nonlinearities on the performance of the ADC. The results aid the design of open loop pipeline ADCs by providing a comprehensive set of design specifications that must be satisfied by each building block.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124540433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415566
Yong Li, Zhi-Ying Wang, Jian Ruan, Kui Dai
The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. This paper presents a low-power TTA processor using hybrid asynchronous and synchronous function units. This processor is customized for a 1024-point FFT application. We also implement a processor only using synchronous function units. Comparing to the synchronous processor core, the processor core using asynchronous function units has lower average power dissipation and higher performance.
{"title":"Research and implement a low-power configurable embedded processor for 1024-point fast fourier transform","authors":"Yong Li, Zhi-Ying Wang, Jian Ruan, Kui Dai","doi":"10.1109/ICASIC.2007.4415566","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415566","url":null,"abstract":"The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. This paper presents a low-power TTA processor using hybrid asynchronous and synchronous function units. This processor is customized for a 1024-point FFT application. We also implement a processor only using synchronous function units. Comparing to the synchronous processor core, the processor core using asynchronous function units has lower average power dissipation and higher performance.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114399243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415653
Jianfeng Su, Z. Fu, Haiquan Yuan, Minghui Zeng
An UWB (ultra wide band) low noise amplifier (LNA), which is designed with the HJTC's 0.18 mum CMOS process, is presented in this paper. Simulation results show a gain from 10 to 13.3 dB over a bandwidth range from 3 to 5 GHz. This LNA achieves a noise figure less than 5.5 dB and power dissipation less than 12.5 mW under a power supply of 1.8 V. The input/output return loss is higher than 9/14 dB.
{"title":"An Ultra-Wideband CMOS low noise amplifier For 3–5 GHz UWB wireless receivers","authors":"Jianfeng Su, Z. Fu, Haiquan Yuan, Minghui Zeng","doi":"10.1109/ICASIC.2007.4415653","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415653","url":null,"abstract":"An UWB (ultra wide band) low noise amplifier (LNA), which is designed with the HJTC's 0.18 mum CMOS process, is presented in this paper. Simulation results show a gain from 10 to 13.3 dB over a bandwidth range from 3 to 5 GHz. This LNA achieves a noise figure less than 5.5 dB and power dissipation less than 12.5 mW under a power supply of 1.8 V. The input/output return loss is higher than 9/14 dB.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114814304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415641
Hongwei Shen, Lilan Li, Yumei Zhou
A long range passive tag with temperature sensor in 0.35 mu m CMOS process has been presented. It contains five sections: RF front-end circuit, digital logical circuit, temperature sensor, a low power SAR ADC and memory circuit. The RF section contains a voltage rectifier, a voltage regulator, a PWM demodulator, a PSK backscatter modulator, and a local oscillator has been calibrated by the reader's emitting signals. The circuits of the chip work at multi supply voltage for lower power, and the total current dissipation is 15.4 mu A. A low-power 8 bit successive approximation analog to digital converter (ADC) is used to quantize the temperature output. The error of the temperature quantity output is plusmn 2degC in the range of -10 - 120degC.
提出了一种采用0.35 μ m CMOS工艺的带温度传感器的远距离无源标签。它包括五个部分:射频前端电路、数字逻辑电路、温度传感器、低功耗SAR ADC和存储电路。射频部分包含一个电压整流器，一个电压调节器，一个PWM解调器，一个PSK后向散射调制器，和一个本地振荡器已被校准的阅读器的发射信号。该芯片的电路工作在低功率的多电源电压下，总电流耗散为15.4 μ A，采用低功率8位逐次逼近模数转换器(ADC)对温度输出进行量化。在-10 - 120℃范围内，温度量输出误差为±2℃。
{"title":"Fully integrated passive UHF RFID tag with temperature sensor for environment monitoring","authors":"Hongwei Shen, Lilan Li, Yumei Zhou","doi":"10.1109/ICASIC.2007.4415641","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415641","url":null,"abstract":"A long range passive tag with temperature sensor in 0.35 mu m CMOS process has been presented. It contains five sections: RF front-end circuit, digital logical circuit, temperature sensor, a low power SAR ADC and memory circuit. The RF section contains a voltage rectifier, a voltage regulator, a PWM demodulator, a PSK backscatter modulator, and a local oscillator has been calibrated by the reader's emitting signals. The circuits of the chip work at multi supply voltage for lower power, and the total current dissipation is 15.4 mu A. A low-power 8 bit successive approximation analog to digital converter (ADC) is used to quantize the temperature output. The error of the temperature quantity output is plusmn 2degC in the range of -10 - 120degC.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123601975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415837
Zhang Zheng-fan, L. Zhaoji, Tan Kai-zhou, Zhang Jiabin
In this paper, an analytical model of sub-threshold swing for the double-gate accumulation-mode P-channel SOI MOSFET is described. The model is based on Possion's equation and depletion approximation, and the relation of the sub-threshold swing with both the gate oxide capacitance and the interface trap density is obtained. The model is verified by experiment and by numerical simulation. Also an approach to extracting the interface trap density with sub-threshold swing is proposed.
{"title":"Investigation into sub-threshold performance of double-gate accumulation-mode SOI PMOSFET","authors":"Zhang Zheng-fan, L. Zhaoji, Tan Kai-zhou, Zhang Jiabin","doi":"10.1109/ICASIC.2007.4415837","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415837","url":null,"abstract":"In this paper, an analytical model of sub-threshold swing for the double-gate accumulation-mode P-channel SOI MOSFET is described. The model is based on Possion's equation and depletion approximation, and the relation of the sub-threshold swing with both the gate oxide capacitance and the interface trap density is obtained. The model is verified by experiment and by numerical simulation. Also an approach to extracting the interface trap density with sub-threshold swing is proposed.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"338 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124472886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415688
Jincheng Li, Yulin Qiu, Qi-Xian Peng, Y. Liu
The traditional heterodyne wireless receivers are based on frequency-downconversion(FD) topologies, which is hard to be implemented with RF CMOS technologies with high integration level due to the problems caused by mirror suppression, strict matching and DC-offset. We propose a non-frequency-downconversion(NFD) wireless receiver topology. First, we recover the Fourier series coefficients of the modulated RF signal corresponding to a certain time interval by analog circuits. This is followed by feeding the coefficients to a DSP to demodulate the baseband information modulated in the RF signal. Because this new topology does not require mirror suppression and strict matching, it is suitable for the implementation of RF CMOS receivers with high level integration.
{"title":"A new wireless receiver topology","authors":"Jincheng Li, Yulin Qiu, Qi-Xian Peng, Y. Liu","doi":"10.1109/ICASIC.2007.4415688","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415688","url":null,"abstract":"The traditional heterodyne wireless receivers are based on frequency-downconversion(FD) topologies, which is hard to be implemented with RF CMOS technologies with high integration level due to the problems caused by mirror suppression, strict matching and DC-offset. We propose a non-frequency-downconversion(NFD) wireless receiver topology. First, we recover the Fourier series coefficients of the modulated RF signal corresponding to a certain time interval by analog circuits. This is followed by feeding the coefficients to a DSP to demodulate the baseband information modulated in the RF signal. Because this new topology does not require mirror suppression and strict matching, it is suitable for the implementation of RF CMOS receivers with high level integration.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125796396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415750
Jim Wang, Lei Wang, Lili Shen, T. Ikenaga, S. Goto
Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Aimed this problem, non-normative error concealment (EC) is recommended in H.264/AVC to recover the lost image. By analyzing of non-normative inter EC, this paper focused on improvement of it. Firstly, since the "guessed'Vrecovered MV (motion vector) in existing EC is not so close to the real MV, a refined MV recovery is proposed to get a more accurate "guessed" MV. Secondly an improved MV selection criterion (side matching criterion) is proposed, which is trying to "guess'Vapproach a lost MB (macroblock)'s real/original side match distortion, instead of "guess'Vapproach value 0 in traditional inter EC. In addition, for MV refinement scheme, inspired by MV searching in motion estimation, we adopt a diamond searching for MV recovery. Both objective and subjective image quality evaluation in experiments show that our proposal achieves a better image recovery compared with non-normative inter EC.
{"title":"An improved inter frame error concealment in H.264/AVC","authors":"Jim Wang, Lei Wang, Lili Shen, T. Ikenaga, S. Goto","doi":"10.1109/ICASIC.2007.4415750","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415750","url":null,"abstract":"Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Aimed this problem, non-normative error concealment (EC) is recommended in H.264/AVC to recover the lost image. By analyzing of non-normative inter EC, this paper focused on improvement of it. Firstly, since the \"guessed'Vrecovered MV (motion vector) in existing EC is not so close to the real MV, a refined MV recovery is proposed to get a more accurate \"guessed\" MV. Secondly an improved MV selection criterion (side matching criterion) is proposed, which is trying to \"guess'Vapproach a lost MB (macroblock)'s real/original side match distortion, instead of \"guess'Vapproach value 0 in traditional inter EC. In addition, for MV refinement scheme, inspired by MV searching in motion estimation, we adopt a diamond searching for MV recovery. Both objective and subjective image quality evaluation in experiments show that our proposal achieves a better image recovery compared with non-normative inter EC.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125979693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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