Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415634
Ge Ning, Chen Cong
A design of a frequency stabilization circuit for the voltage controlled ring oscillator that can stabilize the voltage source and compensate the temperature and process variation is presented here. A linear voltage source using bandgap voltage reference and a temperature and process compensated circuit used for adjusting the control voltage are introduced into the oscillator. The simulation results show that when the proposed oscillator is set at 620 MHz, the output frequency has a variation of 0.13% for the voltage source in the range 3.0 V to 3.6 V when the temperature is 27degC and the process corner is typical; the output frequency has a variation of 0.8% for the temperature range of 0degC to 120degC when the voltage source is 3.3 V and the process corner is typical; the output frequency variation changes from 34.3% to 19.1% after the compensation circuit is added for all the process corners when the temperature is 27degC.
本文设计了一种稳定电压源、补偿温度和工艺变化的压控环振荡器稳频电路。在振荡器中引入了带隙基准电压的线性电压源和用于调节控制电压的温度和过程补偿电路。仿真结果表明，当所提出的振荡器设置为620 MHz时，当温度为27℃，典型的过程角时，电压源在3.0 V ~ 3.6 V范围内的输出频率变化为0.13%;电压源为3.3 V，典型工艺角时，在0℃~ 120℃温度范围内，输出频率变化为0.8%;在温度为27℃时，对所有工艺角加入补偿电路后，输出频率变化由34.3%增加到19.1%。
{"title":"A Frequency Stabilization Circuit for The Voltage Controlled Ring Oscillator","authors":"Ge Ning, Chen Cong","doi":"10.1109/ICASIC.2007.4415634","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415634","url":null,"abstract":"A design of a frequency stabilization circuit for the voltage controlled ring oscillator that can stabilize the voltage source and compensate the temperature and process variation is presented here. A linear voltage source using bandgap voltage reference and a temperature and process compensated circuit used for adjusting the control voltage are introduced into the oscillator. The simulation results show that when the proposed oscillator is set at 620 MHz, the output frequency has a variation of 0.13% for the voltage source in the range 3.0 V to 3.6 V when the temperature is 27degC and the process corner is typical; the output frequency has a variation of 0.8% for the temperature range of 0degC to 120degC when the voltage source is 3.3 V and the process corner is typical; the output frequency variation changes from 34.3% to 19.1% after the compensation circuit is added for all the process corners when the temperature is 27degC.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126207702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415588
D. Zhou, Jianping Hu, Huiying Dong
This paper presents a new power-gating technique for adiabatic circuits to reduce energy loss during idle state. The power-gating switches based on DTGAL (dual transmission gate adiabatic logic) circuits are used to detach adiabatic logic blocks from power-clocks. The energy overhead optimization for the proposed power-gating scheme is investigated. The 8-bit full adders based on DTGAL circuits are verified using the proposed power-gating technique. All circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss is reduced greatly by shutting down idle adiabatic logic blocks.
{"title":"An energy-efficient power-gating adiabatic circuits using transmission gate switches","authors":"D. Zhou, Jianping Hu, Huiying Dong","doi":"10.1109/ICASIC.2007.4415588","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415588","url":null,"abstract":"This paper presents a new power-gating technique for adiabatic circuits to reduce energy loss during idle state. The power-gating switches based on DTGAL (dual transmission gate adiabatic logic) circuits are used to detach adiabatic logic blocks from power-clocks. The energy overhead optimization for the proposed power-gating scheme is investigated. The 8-bit full adders based on DTGAL circuits are verified using the proposed power-gating technique. All circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss is reduced greatly by shutting down idle adiabatic logic blocks.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126221986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415715
Yuanjie Bin, F. Quanyuan
In this paper, a comparator used for switching regulator is presented. This design uses a bias stage with the structure of negative feedback to get more stable DC bias voltages. The comparator is formed by 3 stages: input stage, a emitter coupled differential pair; middle stage, a folded cascode amplifier and output stage be consisted by a Active Load Inverter. These simulation result shown in this paper is got by Hspice with a 0.6 um CMOS technologies and 3.6 V power supply.
本文介绍了一种用于开关稳压器的比较器。本设计采用负反馈结构的偏置级，以获得更稳定的直流偏置电压。所述比较器由3级组成:输入级、射极耦合差分对;中间级为折叠级联放大器，输出级由有源负载逆变器组成。本文所示的仿真结果是通过Hspice采用0.6 um CMOS技术和3.6 V电源得到的。
{"title":"Design of a voltage comparator using for switching regulator","authors":"Yuanjie Bin, F. Quanyuan","doi":"10.1109/ICASIC.2007.4415715","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415715","url":null,"abstract":"In this paper, a comparator used for switching regulator is presented. This design uses a bias stage with the structure of negative feedback to get more stable DC bias voltages. The comparator is formed by 3 stages: input stage, a emitter coupled differential pair; middle stage, a folded cascode amplifier and output stage be consisted by a Active Load Inverter. These simulation result shown in this paper is got by Hspice with a 0.6 um CMOS technologies and 3.6 V power supply.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126446525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415784
Hao Shen, F. Pétrot
To achieve high performance with relative low power consumption for the embedded system design, architects put more and more emphasis on the heterogeneous multiprocessors SoC (MPSoC) solution. Because there are several different CPU subsystems and OS in one heterogeneous MPSoC, it is complex and time consuming to develop the HW/SW interfaces which can meet all applications requirements. Our group introduces a service-based automatic generation process. In this process, a new model called service dependency graph (SDG) is used to describe all components in HW/SW interfaces. The interface/implementation structure of the SDG makes this model flexible and accurate. The motion-JPEG experimentation case is created to show the advantage of using SDG in building simulation models at different abstraction levels. At the end, we present how SDG can support the communication exploration.
{"title":"Service dependency graph for HW/SW interfaces modeling: The motion-JPEG case study","authors":"Hao Shen, F. Pétrot","doi":"10.1109/ICASIC.2007.4415784","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415784","url":null,"abstract":"To achieve high performance with relative low power consumption for the embedded system design, architects put more and more emphasis on the heterogeneous multiprocessors SoC (MPSoC) solution. Because there are several different CPU subsystems and OS in one heterogeneous MPSoC, it is complex and time consuming to develop the HW/SW interfaces which can meet all applications requirements. Our group introduces a service-based automatic generation process. In this process, a new model called service dependency graph (SDG) is used to describe all components in HW/SW interfaces. The interface/implementation structure of the SDG makes this model flexible and accurate. The motion-JPEG experimentation case is created to show the advantage of using SDG in building simulation models at different abstraction levels. At the end, we present how SDG can support the communication exploration.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126024413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415547
T. Ikenaga
In 1995, MPEG-2 became a video coding international standard. Since then, a wide variety of video compression LSIs have been developed and actually deployed in many applications such as digital HDTV broadcasting, TV conference, mobile and so forth. Since video coding technology is essential to the efficient storage and transmission of video data, it continues to play an important role in ubiquitous (anywhere, anytime, etc) and coming ambient (safe, comfortable, etc) information society. In this talk, I will provide video compression LSI technologies from past, present and future points of view.
{"title":"K-4 Video compression LSI: Past, present, and future trends","authors":"T. Ikenaga","doi":"10.1109/ICASIC.2007.4415547","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415547","url":null,"abstract":"In 1995, MPEG-2 became a video coding international standard. Since then, a wide variety of video compression LSIs have been developed and actually deployed in many applications such as digital HDTV broadcasting, TV conference, mobile and so forth. Since video coding technology is essential to the efficient storage and transmission of video data, it continues to play an important role in ubiquitous (anywhere, anytime, etc) and coming ambient (safe, comfortable, etc) information society. In this talk, I will provide video compression LSI technologies from past, present and future points of view.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124552689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415728
Yongsheng Yin, Minglun Gao, Honghui Deng, Shangquan Liang, Cong Liu
A 14-bit, 130MSPS DAC with 2times FIR interpolation filter simulated in a 0.35 mum CMOS process is described in this paper. The DAC adopts segmented current-steering structure, which combines the characteristic of unit current DAC and the binary weighted DAC to get the balance between area and performance. A 2times FIR interpolation filter is introduced to reduce the complexity of analog reconstruction filter following the DAC. Key circuits and simulation results are presented. The results show that this DAC can deliver up to 20 mA current into a 50Omega load. Power dissipation with 3.3 V supply is 286 mW at 200 MHz DAC update rate. The INL is plusmn3.5LSB, and DNL is plusmn 2.0LSB. SFDR is 76 dB at 100 MSPS and 50 MHz output frequency.
{"title":"A 14-bit 130-MSPS current-steering CMOS DAC with 2 x FIR interpolation filter","authors":"Yongsheng Yin, Minglun Gao, Honghui Deng, Shangquan Liang, Cong Liu","doi":"10.1109/ICASIC.2007.4415728","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415728","url":null,"abstract":"A 14-bit, 130MSPS DAC with 2times FIR interpolation filter simulated in a 0.35 mum CMOS process is described in this paper. The DAC adopts segmented current-steering structure, which combines the characteristic of unit current DAC and the binary weighted DAC to get the balance between area and performance. A 2times FIR interpolation filter is introduced to reduce the complexity of analog reconstruction filter following the DAC. Key circuits and simulation results are presented. The results show that this DAC can deliver up to 20 mA current into a 50Omega load. Power dissipation with 3.3 V supply is 286 mW at 200 MHz DAC update rate. The INL is plusmn3.5LSB, and DNL is plusmn 2.0LSB. SFDR is 76 dB at 100 MSPS and 50 MHz output frequency.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131113828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415630
Yunfeng Wang, Qing Ye, Jiahan Man, Jim Fan, Tianchun Ye
:This paper presents the design of a 4 GHz PLL used in wireless receiver. The Verilog-A models are used in behavioral level simulation and in post-layout simulation. The design is based on SMIC 0.18 um 1P6M CMOS RF process. The settling time is 19us and the reference spur is 42.2 dB, the phase noise of VCO is -115 dBc/Hz@lMHz, the power dissipation of the PLL is 36 mW.
本文介绍了一种用于无线接收机的4ghz锁相环的设计。Verilog-A模型用于行为级仿真和布局后仿真。本设计基于中芯国际0.18 um 1P6M CMOS射频工艺。稳定时间为19us，参考杂散为42.2 dB，压控振荡器相位噪声为-115 dBc/Hz@lMHz，锁相环功耗为36 mW。
{"title":"Design a 4GHz PLL for wireless receiver","authors":"Yunfeng Wang, Qing Ye, Jiahan Man, Jim Fan, Tianchun Ye","doi":"10.1109/ICASIC.2007.4415630","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415630","url":null,"abstract":":This paper presents the design of a 4 GHz PLL used in wireless receiver. The Verilog-A models are used in behavioral level simulation and in post-layout simulation. The design is based on SMIC 0.18 um 1P6M CMOS RF process. The settling time is 19us and the reference spur is 42.2 dB, the phase noise of VCO is -115 dBc/Hz@lMHz, the power dissipation of the PLL is 36 mW.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131295872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415856
Huiping Huang, W. Luk, Wenqing Zhao, Xuan Zeng
An effective algorithm applying the deferred-merge embedding (DME) algorithm is presented for clock tree construction in the presence of obstacles. During the clock routing, a track graph is constructed in order to guarantee the obstacle-avoidance. Similar to the DME algorithm, our method is composed of a bottom-up phase computing possible loci of nodes and a top-down step to determine the exact placement of each node in the clock topology tree. Obstruction is considered in both two phases. Experiment results shows that our algorithm is promising.
{"title":"DME-based clock routing in the presence of obstacles","authors":"Huiping Huang, W. Luk, Wenqing Zhao, Xuan Zeng","doi":"10.1109/ICASIC.2007.4415856","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415856","url":null,"abstract":"An effective algorithm applying the deferred-merge embedding (DME) algorithm is presented for clock tree construction in the presence of obstacles. During the clock routing, a track graph is constructed in order to guarantee the obstacle-avoidance. Similar to the DME algorithm, our method is composed of a bottom-up phase computing possible loci of nodes and a top-down step to determine the exact placement of each node in the clock topology tree. Obstruction is considered in both two phases. Experiment results shows that our algorithm is promising.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130192645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415779
Woojoong Lee, G. Sobelman
In this paper, we propose a novel and flexible codeword assignment technique for a Code Division Multiple Access (CDMA) based Network-on-Chip (NoC). This approach allows bandwidth to be reallocated to ports dynamically on an as-needed basis. In this way, more of the available system bandwidth can be utilized under practical traffic conditions. In addition, wormhole routing is applied to minimize the hardware overhead of the technique. Our switch has been synthesized using a 0.3 mum CMOS high-speed ASIC library. Synthesis results and performance analysis data are provided.
本文提出了一种基于码分多址(CDMA)的片上网络(NoC)的新颖而灵活的码字分配技术。这种方法允许根据需要动态地将带宽重新分配给端口。这样，在实际的流量条件下，可以利用更多的系统可用带宽。此外，虫洞路由被用于最小化该技术的硬件开销。我们的开关是用0.3 μ m CMOS高速ASIC库合成的。给出了综合结果和性能分析数据。
{"title":"Bandwidth-reusable CDMA NoC with flexible codeword assignment","authors":"Woojoong Lee, G. Sobelman","doi":"10.1109/ICASIC.2007.4415779","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415779","url":null,"abstract":"In this paper, we propose a novel and flexible codeword assignment technique for a Code Division Multiple Access (CDMA) based Network-on-Chip (NoC). This approach allows bandwidth to be reallocated to ports dynamically on an as-needed basis. In this way, more of the available system bandwidth can be utilized under practical traffic conditions. In addition, wormhole routing is applied to minimize the hardware overhead of the technique. Our switch has been synthesized using a 0.3 mum CMOS high-speed ASIC library. Synthesis results and performance analysis data are provided.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415849
Xiaocheng Jing, R. Yao
A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.
{"title":"A fast-simulation model for post-layout SRAM","authors":"Xiaocheng Jing, R. Yao","doi":"10.1109/ICASIC.2007.4415849","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415849","url":null,"abstract":"A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121950010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：