Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415733
Jiayi Liang, Yajie Qin, Zhiliang Hong
The proposed algorithm provides fast and accurate auto-exposure capability for digital still cameras. For normal lighting conditions, the number of preview frames and the exposure error are within 3.5 frames and 3.92%. For high contrast lighting conditions, the number of preview frames and the exposure error are within 8.8 frames and 6.56%. Furthermore, it offers accurate detection for both back lit and excessive front lit conditions at the same time and make proper exposure to the main object.
{"title":"An Auto-exposure algorithm for detecting high contrast lighting conditions","authors":"Jiayi Liang, Yajie Qin, Zhiliang Hong","doi":"10.1109/ICASIC.2007.4415733","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415733","url":null,"abstract":"The proposed algorithm provides fast and accurate auto-exposure capability for digital still cameras. For normal lighting conditions, the number of preview frames and the exposure error are within 3.5 frames and 3.92%. For high contrast lighting conditions, the number of preview frames and the exposure error are within 8.8 frames and 6.56%. Furthermore, it offers accurate detection for both back lit and excessive front lit conditions at the same time and make proper exposure to the main object.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132898430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415586
Xu Jian, Wan Peng-jun, Zeng Xiao-yang
Based on the study of clocked transmission gate adiabatic logic (CTGAL) circuit, a new adiabatic multiplier is proposed in this paper. It consists of a partial-product generator, a partial-product compressor and a parallel prefix adder. CTGAL is used in all the circuits to charge and discharge the node capacitances without the threshold value losing and the charge on the output node capacitances can be recovered completely. So the power consumption of the newly designed circuits is significantly reduced. Computer simulation results verify the valid functionality and the significant energy recovery characteristic of the designed circuits.
{"title":"Research of adiabatic multiplier based on CTGAL","authors":"Xu Jian, Wan Peng-jun, Zeng Xiao-yang","doi":"10.1109/ICASIC.2007.4415586","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415586","url":null,"abstract":"Based on the study of clocked transmission gate adiabatic logic (CTGAL) circuit, a new adiabatic multiplier is proposed in this paper. It consists of a partial-product generator, a partial-product compressor and a parallel prefix adder. CTGAL is used in all the circuits to charge and discharge the node capacitances without the threshold value losing and the charge on the output node capacitances can be recovered completely. So the power consumption of the newly designed circuits is significantly reduced. Computer simulation results verify the valid functionality and the significant energy recovery characteristic of the designed circuits.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132958532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415840
S. Balakrishnan
Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the deja-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential equivalence checking opens up possibilities in this area, by enabling performance-tuning related sequential micro-architectural changes to be verified with significantly lower impact on effort estimates and risk. This nascent technology promises to change the way we look at eleventh hour changes.
{"title":"Sequential equivalence techniques for high performance design","authors":"S. Balakrishnan","doi":"10.1109/ICASIC.2007.4415840","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415840","url":null,"abstract":"Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the deja-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential equivalence checking opens up possibilities in this area, by enabling performance-tuning related sequential micro-architectural changes to be verified with significantly lower impact on effort estimates and risk. This nascent technology promises to change the way we look at eleventh hour changes.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"27 41","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415701
Jing Wang, Wenchao Gong, Lenian He
A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.
提出了一种具有脉宽调制(PWM)和脉频调制(PFM)的高效低功耗多模DC-DC变换器。该变换器在重载条件下工作在PWM模式下。为了提高效率，它在轻载状态下切换到PFM模式。通过适当的控制和模式切换方法，仿真和芯片测试结果表明，该变换器可以在PWM和PFM模式之间无缝切换。包括线路和负载调节在内的总输出电压误差小于±2%，最大静态电流小于15 muA，最高效率达到92.6%。在CSMC 0.5 μ m CMOS工艺中进行了仿真和实现。
{"title":"Design and implementation of high-efficiency and low-power DC-DC converter with PWM/PFM modes","authors":"Jing Wang, Wenchao Gong, Lenian He","doi":"10.1109/ICASIC.2007.4415701","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415701","url":null,"abstract":"A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117006259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415618
Zhen Liu, Y. Wang, S. Jia, L. Ji, Xing Zhang
A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65 mW at a 3.3 V supply.
{"title":"Low-power CMOS folding and interpolating ADC with a fully-folding technique","authors":"Zhen Liu, Y. Wang, S. Jia, L. Ji, Xing Zhang","doi":"10.1109/ICASIC.2007.4415618","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415618","url":null,"abstract":"A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65 mW at a 3.3 V supply.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114974920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415822
Jinghong Liang, Xianlong Hong, Tong Jing
With the progress of very large scale integration, using traditional global routing algorithms to solve multi-layer routing problem causes the routing resource waste of lower layers or the lack of higher layers because the pitch size is different in different layer pairs and traditional algorithms use uniform pitch size for all layer pairs. The paper presents a global routing algorithm that performs layer assignment before routing. This algorithm is based on a new flow for multi-layer routing, and uses bounding box of the nets to estimate the congestion, and distributes them to different layer pairs based on the aim of even congestion. The algorithm has been implemented and tested. The experimental results show that the algorithm is more effective.
{"title":"A new multi-layer global routing flow for congestion elimination","authors":"Jinghong Liang, Xianlong Hong, Tong Jing","doi":"10.1109/ICASIC.2007.4415822","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415822","url":null,"abstract":"With the progress of very large scale integration, using traditional global routing algorithms to solve multi-layer routing problem causes the routing resource waste of lower layers or the lack of higher layers because the pitch size is different in different layer pairs and traditional algorithms use uniform pitch size for all layer pairs. The paper presents a global routing algorithm that performs layer assignment before routing. This algorithm is based on a new flow for multi-layer routing, and uses bounding box of the nets to estimate the congestion, and distributes them to different layer pairs based on the aim of even congestion. The algorithm has been implemented and tested. The experimental results show that the algorithm is more effective.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115237075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415867
Xin Zhang, Dunshan Yu, Shimin Sheng
In this paper, a behavior-oriented simulation tool is proposed for the designing and optimizing of sigma-delta ADCs. We show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system design. The imperfections of the analog cells as integrators, comparator, and the CpAMPs are analyzed in detail, which guides the design towards high performance. Besides, the modeling, simulation, and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool. A peak SNR of 91.5 dB, a 15 bit resolution, and a 57 m W power dissipation are obtained through HSPICE simulation. Currently chip is in the fabrication phase.
本文提出了一种面向行为的仿真工具，用于sigma-delta adc的设计和优化。我们展示了如何在混合信号系统设计的自上而下的设计流程中使用这种仿真工具。详细分析了模拟单元作为积分器、比较器和camp的不足之处，指导了模拟单元的高性能设计。此外，通过对二阶σ - δ调制器的建模、仿真和设计，验证了仿真工具的有效性。通过HSPICE仿真得到的峰值信噪比为91.5 dB，分辨率为15位，功耗为57 m W。目前芯片还处于制造阶段。
{"title":"A behavior-oriented simulation tool for design and optimization of sigma-delta ADCs","authors":"Xin Zhang, Dunshan Yu, Shimin Sheng","doi":"10.1109/ICASIC.2007.4415867","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415867","url":null,"abstract":"In this paper, a behavior-oriented simulation tool is proposed for the designing and optimizing of sigma-delta ADCs. We show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system design. The imperfections of the analog cells as integrators, comparator, and the CpAMPs are analyzed in detail, which guides the design towards high performance. Besides, the modeling, simulation, and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool. A peak SNR of 91.5 dB, a 15 bit resolution, and a 57 m W power dissipation are obtained through HSPICE simulation. Currently chip is in the fabrication phase.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"640 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116085442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415863
Runshan Yang, Liji Wu, Jim Guo, Baorong Liu
This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation. A layered architecture is adopted for reusing; the verification vectors are randomly generated and the simulation results can be checked automatically. Further more, genetic algorithm is employed to improve the efficiency of the verification vectors generation. The result of experiments performed on a smart card showed this method to be effective and efficient.
{"title":"The research and implement of an advanced function coverage based verification environment","authors":"Runshan Yang, Liji Wu, Jim Guo, Baorong Liu","doi":"10.1109/ICASIC.2007.4415863","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415863","url":null,"abstract":"This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation. A layered architecture is adopted for reusing; the verification vectors are randomly generated and the simulation results can be checked automatically. Further more, genetic algorithm is employed to improve the efficiency of the verification vectors generation. The result of experiments performed on a smart card showed this method to be effective and efficient.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116358940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415762
Xuerong Yu, Z. Dai, Xiaohui Yang
Based on analyzing the operation character of block ciphers, we set forth a solution for efficient cryptographic processing, and put forward a parallel co-processor architecture for block ciphers , which supports word and sub-word parallel processing, and its micro realization is schemed out too. The design gives attention to two aspects which is flexibility and high performance, including consummate control capability, efficient operation capability, and reconfigurable cipher process capability. Finally, in synthesis, the design is fabricated on 0.18um CMOS cells through design compiler tool, and the performance of this co-processor is compared to other hardware/software implementation.
{"title":"A parallel co-processor architecture for block cipher processing","authors":"Xuerong Yu, Z. Dai, Xiaohui Yang","doi":"10.1109/ICASIC.2007.4415762","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415762","url":null,"abstract":"Based on analyzing the operation character of block ciphers, we set forth a solution for efficient cryptographic processing, and put forward a parallel co-processor architecture for block ciphers , which supports word and sub-word parallel processing, and its micro realization is schemed out too. The design gives attention to two aspects which is flexibility and high performance, including consummate control capability, efficient operation capability, and reconfigurable cipher process capability. Finally, in synthesis, the design is fabricated on 0.18um CMOS cells through design compiler tool, and the performance of this co-processor is compared to other hardware/software implementation.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121463415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415718
Weidong Yang, Ruzhang Li, Yong Liu, Yonghui Yang, Kaicheng Li
In this paper, the circuit implementation principle, circuit design characteristic and process technology characteristic for a 12-bit voltage output D/A converter with internal reference were described. By using analog unit circuits such as the R-2R resistance switch network optimized in design, the temperature compensation Zener reference voltage, and the BiCMOS output operational amplifier with JFET input, combined with SISC" p-well 3 um LC2MOS process technology, a 12-bit D/A converter was developed. The converter features high conversion resolution, small linear and differential error, low power consumption, fast conversion speed, ease of use, etc.
{"title":"Investigation into the 12-bit DA converter","authors":"Weidong Yang, Ruzhang Li, Yong Liu, Yonghui Yang, Kaicheng Li","doi":"10.1109/ICASIC.2007.4415718","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415718","url":null,"abstract":"In this paper, the circuit implementation principle, circuit design characteristic and process technology characteristic for a 12-bit voltage output D/A converter with internal reference were described. By using analog unit circuits such as the R-2R resistance switch network optimized in design, the temperature compensation Zener reference voltage, and the BiCMOS output operational amplifier with JFET input, combined with SISC\" p-well 3 um LC2MOS process technology, a 12-bit D/A converter was developed. The converter features high conversion resolution, small linear and differential error, low power consumption, fast conversion speed, ease of use, etc.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121562970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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