Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415735
Xiao-ming Li, Yi-qi Zhuang
VDMOS integrated in scan driver chip for plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS- DMOS (BCD) process. The key considerations during the design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the VDMOS parameter and chip parameter, the results is favorable for 170 V PDP scan driver chip, which contributes to the competitive cost efficiency.
基于外延双极cmos - DMOS (BCD)工艺，将VDMOS集成在等离子体显示面板(PDP)扫描驱动芯片中。提出了设计过程中的关键考虑因素，并对结构和参数优化进行了大量的仿真和工艺调整，通过对VDMOS参数和芯片参数的测试，结果表明该芯片适合170 V PDP扫描驱动芯片，具有较强的成本效益。
{"title":"Cost-effective VDMOS for PDP scan driver IC","authors":"Xiao-ming Li, Yi-qi Zhuang","doi":"10.1109/ICASIC.2007.4415735","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415735","url":null,"abstract":"VDMOS integrated in scan driver chip for plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS- DMOS (BCD) process. The key considerations during the design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the VDMOS parameter and chip parameter, the results is favorable for 170 V PDP scan driver chip, which contributes to the competitive cost efficiency.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126014064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415662
Ke Liu, Hai-gang Yang
A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include optimization of speed and accuracy. To meet the requirements, a differential flip-around capacitor topology has been used with special care taken in linearization of switches. Gain-boosted OTA with high DC gain and larger bandwidth is designed and optimized. The output of the module can attain over 77dB SFDR, which is suitable for serving as a front-end in a 12bit 100MS/s pipeline ADC.
采用0.35 μ m 2P4M CMOS技术，采用3.3 V电源，为流水线ADC前端设计了一个全差分采样保持模块。关键的设计问题包括速度和精度的优化。为了满足要求，在开关的线性化中特别注意使用了差分翻转电容器拓扑。设计并优化了具有高直流增益和更大带宽的增益增强OTA。该模块的输出可达到77dB以上的SFDR，适合作为12位100MS/s流水线ADC的前端。
{"title":"Optimum design of a fully differential 12bit 100MS/s sample and hold module with over 77dB SFDR","authors":"Ke Liu, Hai-gang Yang","doi":"10.1109/ICASIC.2007.4415662","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415662","url":null,"abstract":"A fully differential sample and hold module has been designed for the front-end of a pipeline ADC using 0.35 mum 2P4M CMOS technology with a power supply of 3.3 V. The key design issues include optimization of speed and accuracy. To meet the requirements, a differential flip-around capacitor topology has been used with special care taken in linearization of switches. Gain-boosted OTA with high DC gain and larger bandwidth is designed and optimized. The output of the module can attain over 77dB SFDR, which is suitable for serving as a front-end in a 12bit 100MS/s pipeline ADC.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124608658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415638
F. Dai, Yin Shi, Jun Yan, Xueqing Hu
This paper presents a low-power single chip WLAN 802.11a transceiver RFIC for personal communication terminal applications. The 5.2 GHz transceiver RFIC is implemented in a 0.5 mum SiGe technology with 16 mm2 die size. It consumes 110/130 mA in receive/transmit mode under a 3.3V supply. The receiver path shows a 6.4 dB noise figure and a -20 dBm IIP3 under a maximal 67 dB gain. The transmitter path OIP3 is measured as 29.7 dBm. The LC-tuned VCO has a tuning range from 4.08 GHz to 4.7 GHz and the measured phase noise is -112 dBc/Hz @ 1 MHz offset. Also discussed are design considerations for multiple-input-multiple-output (MIMO) transceiver RFIC implementations.
{"title":"MIMO RFIC Transceiver Designs for WLAN Applications","authors":"F. Dai, Yin Shi, Jun Yan, Xueqing Hu","doi":"10.1109/ICASIC.2007.4415638","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415638","url":null,"abstract":"This paper presents a low-power single chip WLAN 802.11a transceiver RFIC for personal communication terminal applications. The 5.2 GHz transceiver RFIC is implemented in a 0.5 mum SiGe technology with 16 mm2 die size. It consumes 110/130 mA in receive/transmit mode under a 3.3V supply. The receiver path shows a 6.4 dB noise figure and a -20 dBm IIP3 under a maximal 67 dB gain. The transmitter path OIP3 is measured as 29.7 dBm. The LC-tuned VCO has a tuning range from 4.08 GHz to 4.7 GHz and the measured phase noise is -112 dBc/Hz @ 1 MHz offset. Also discussed are design considerations for multiple-input-multiple-output (MIMO) transceiver RFIC implementations.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415700
Yunxiu Wang, Bing-Zhong Wang, Jian-Peng Wang
A compact microstrip bandpass filter with harmonic suppression is presented in this letter. The filter is composed of two tri-section stepped impedance resonators cascaded and two end-open L-shaped microstrip lines for the input and output feed lines. The harmonic suppression of the bandpass filter may be realized by choosing proper lengths for the L-shaped microstrip lines and proper impedance ratios of the stepped impedance resonator. The filter has been investigated numerically. Simulation results show that the second-order harmonic response is effectively suppressed, and the rejection level is kept below -19 dB.
{"title":"A tri-section stepped impedance bandpass filter with harmonic suppression","authors":"Yunxiu Wang, Bing-Zhong Wang, Jian-Peng Wang","doi":"10.1109/ICASIC.2007.4415700","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415700","url":null,"abstract":"A compact microstrip bandpass filter with harmonic suppression is presented in this letter. The filter is composed of two tri-section stepped impedance resonators cascaded and two end-open L-shaped microstrip lines for the input and output feed lines. The harmonic suppression of the bandpass filter may be realized by choosing proper lengths for the L-shaped microstrip lines and proper impedance ratios of the stepped impedance resonator. The filter has been investigated numerically. Simulation results show that the second-order harmonic response is effectively suppressed, and the rejection level is kept below -19 dB.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129903486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415651
Hua Shen, Guoting Wu, Li-wu Yang, X. Lv
A 264 MHz 6th order Gm-C Chebyshev low-pass filter based on the leapfrog structure for direct conversion UWB receiver is presented. The universal design flow and the topology of this filter are also analyzed. Tuning capacitors digitally and tuning the common-mode reference voltage continuously can calibrate the cutoff frequency to overcome the process variation and temperature dependencies. Simulated results show that the cutoff frequency can adjust from 200 MHz to 320 MHz. The attenuation at 660 MHz and 1.3 GHz are 46 dB and 75 dB respectively, and the total harmonic distortion (THD) of the filter is -39.7 dBc for 200 mVpp differential input signal at 200 MHz. The power dissipation is 11.8 mW under 1.5 V power supply.
{"title":"A 0.13μm CMOS Gm-C LPF for UWB receiver","authors":"Hua Shen, Guoting Wu, Li-wu Yang, X. Lv","doi":"10.1109/ICASIC.2007.4415651","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415651","url":null,"abstract":"A 264 MHz 6th order Gm-C Chebyshev low-pass filter based on the leapfrog structure for direct conversion UWB receiver is presented. The universal design flow and the topology of this filter are also analyzed. Tuning capacitors digitally and tuning the common-mode reference voltage continuously can calibrate the cutoff frequency to overcome the process variation and temperature dependencies. Simulated results show that the cutoff frequency can adjust from 200 MHz to 320 MHz. The attenuation at 660 MHz and 1.3 GHz are 46 dB and 75 dB respectively, and the total harmonic distortion (THD) of the filter is -39.7 dBc for 200 mVpp differential input signal at 200 MHz. The power dissipation is 11.8 mW under 1.5 V power supply.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127061384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415873
Wentao Chen, Depeng Jin, Lieguang Zeng
The NoC (network-on-chip) paradigm is commonly considered as an aggressive long-term approach for on-chip communication. Interconnection networks of regular topologies can be designed as IP cores to reduce the well known design-productivity gap. Therefore, regular topologies are more preferred than irregular topologies. To solve the scalability problem of the NoC designs with homogeneous regular topologies, we propose a new NoC design methodology that uses heterogeneous regular topologies. We illustrate the proposed heterogeneous design methodology with a simple configurable regular interconnect topology set, which consists of three subtopologies with different network performances and silicon overheads. Evaluation of the three subtopologies reveals that subtopologies with more connections result in better network performance and more wire complexity. The contribution of the proposed heterogeneous design methodology is that it provides a flexible way to scale the interconnection networks of regular topologies according to the traffic requirements.
{"title":"Heterogeneous design methodology with configurable regular topology set for scalable Network-on-Chip designs","authors":"Wentao Chen, Depeng Jin, Lieguang Zeng","doi":"10.1109/ICASIC.2007.4415873","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415873","url":null,"abstract":"The NoC (network-on-chip) paradigm is commonly considered as an aggressive long-term approach for on-chip communication. Interconnection networks of regular topologies can be designed as IP cores to reduce the well known design-productivity gap. Therefore, regular topologies are more preferred than irregular topologies. To solve the scalability problem of the NoC designs with homogeneous regular topologies, we propose a new NoC design methodology that uses heterogeneous regular topologies. We illustrate the proposed heterogeneous design methodology with a simple configurable regular interconnect topology set, which consists of three subtopologies with different network performances and silicon overheads. Evaluation of the three subtopologies reveals that subtopologies with more connections result in better network performance and more wire complexity. The contribution of the proposed heterogeneous design methodology is that it provides a flexible way to scale the interconnection networks of regular topologies according to the traffic requirements.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127179410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power gating is effective for reducing leakage power. Previously, a distributed sleep transistors network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the maximum instantaneous current (MIC) through sleep transistors. In this paper, we propose methodologies for determining the size of sleep transistors of the DSTN structure considering charge-balancing effect. We also introduce a new relationship among MIC, IR drops and sleep transistor networks from a temporal viewpoint and improve the sizing results. Our methods achieve significant better results than previous works.
{"title":"Sleep transistor sizing in power gating designs","authors":"De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang","doi":"10.1109/ICASIC.2007.4415882","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415882","url":null,"abstract":"Power gating is effective for reducing leakage power. Previously, a distributed sleep transistors network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the maximum instantaneous current (MIC) through sleep transistors. In this paper, we propose methodologies for determining the size of sleep transistors of the DSTN structure considering charge-balancing effect. We also introduce a new relationship among MIC, IR drops and sleep transistor networks from a temporal viewpoint and improve the sizing results. Our methods achieve significant better results than previous works.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127219660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415719
Lungui Zhong, Haigang Yang, Chong Zhang
This paper presents a Charge Redistribution Successive Approximation Register ADC designed in a 0.35-mum standard CMOS process. The total power consumption is only 4.6 mW, and a resolution of 10 bits is achieved. The ADC maintains a maximum DNL of less than 0.4 LSB, an INL less than 0.5 LSB, and an ENOB of 9.9 bits. It can be integrated with micro-sensors to monolithically form highly sensitive, reliable and intelligent measurement devices.
{"title":"Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC","authors":"Lungui Zhong, Haigang Yang, Chong Zhang","doi":"10.1109/ICASIC.2007.4415719","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415719","url":null,"abstract":"This paper presents a Charge Redistribution Successive Approximation Register ADC designed in a 0.35-mum standard CMOS process. The total power consumption is only 4.6 mW, and a resolution of 10 bits is achieved. The ADC maintains a maximum DNL of less than 0.4 LSB, an INL less than 0.5 LSB, and an ENOB of 9.9 bits. It can be integrated with micro-sensors to monolithically form highly sensitive, reliable and intelligent measurement devices.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125683160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415725
Kaiyang Pan, Jianhui Wu, P. Wang
A high precision bandgap reference is presented. An exponential curvature compensation technique, which exploits the Ic-Vbe temperature characteristic of BJTs, is used to reduce the temperature coefficient (TC). A pre-regulator circuit is adopted to enhance the PSRR (power supply rejection ratio) performance. The bandgap uses the current mode approach to generate a reference voltage around 500 mV. With the conventional first-order compensation, the temperature coefficient is 14.6 ppm/degC over the range from -40degC to 85degC. Due to curvature compensation, an improved temperature drift of 7.04 ppm/degC is obtained. The PSRR of the reference voltage achieves 120 dB at low frequency.
{"title":"A high precision CMOS bandgap reference","authors":"Kaiyang Pan, Jianhui Wu, P. Wang","doi":"10.1109/ICASIC.2007.4415725","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415725","url":null,"abstract":"A high precision bandgap reference is presented. An exponential curvature compensation technique, which exploits the Ic-Vbe temperature characteristic of BJTs, is used to reduce the temperature coefficient (TC). A pre-regulator circuit is adopted to enhance the PSRR (power supply rejection ratio) performance. The bandgap uses the current mode approach to generate a reference voltage around 500 mV. With the conventional first-order compensation, the temperature coefficient is 14.6 ppm/degC over the range from -40degC to 85degC. Due to curvature compensation, an improved temperature drift of 7.04 ppm/degC is obtained. The PSRR of the reference voltage achieves 120 dB at low frequency.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132998380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415696
Shanli Long, Jianhui Wu, Yunzhu Zhang, Longxing Shi
A well known problem of time-interleaved analog-to-digital converters is the matching between the channels of the converter. The random mismatch of components between the channels affects the accuracy of the converter especially for high-resolution converters. In this paper, a digital self-calibration is proposed based on least mean square (LMS) algorithm for canceling the offset and gain mismatches. And a global sampling clock using feed-forward compensates for the bottom-plate sampling skew. Simulations on the four-channel time-interleaved pipelined ADC shows that after calibration, the converter could attain 10-bit accuracy successfully.
{"title":"A calibration architecture for improving the performance of time-interleaved ADC","authors":"Shanli Long, Jianhui Wu, Yunzhu Zhang, Longxing Shi","doi":"10.1109/ICASIC.2007.4415696","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415696","url":null,"abstract":"A well known problem of time-interleaved analog-to-digital converters is the matching between the channels of the converter. The random mismatch of components between the channels affects the accuracy of the converter especially for high-resolution converters. In this paper, a digital self-calibration is proposed based on least mean square (LMS) algorithm for canceling the offset and gain mismatches. And a global sampling clock using feed-forward compensates for the bottom-plate sampling skew. Simulations on the four-channel time-interleaved pipelined ADC shows that after calibration, the converter could attain 10-bit accuracy successfully.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123335758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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