Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892329
S. Alkharabsheh, B. Sammakia, B. Murray, S. Shrivastava, R. Schmidt
This paper evaluates the impact of pressure drop in server racks on the cooling of the IT equipment. The measured impedance curves for servers internal resistance, rack doors, and Cable Management Arms (CMA) are used to estimate the reduction in the cooling airflow rate. In this study, 1 RU and 2 RU servers, and a 9 RU server simulator are used as representative IT equipment. A Computational Fluid Dynamics (CFD) model is used to investigate the influence of the rack structure on the thermal field. The effect of the cooling air flow rate on the temperature of the server's internal components is also studied experimentally.
{"title":"Experimental characterization of pressure drop in a server rack","authors":"S. Alkharabsheh, B. Sammakia, B. Murray, S. Shrivastava, R. Schmidt","doi":"10.1109/ITHERM.2014.6892329","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892329","url":null,"abstract":"This paper evaluates the impact of pressure drop in server racks on the cooling of the IT equipment. The measured impedance curves for servers internal resistance, rack doors, and Cable Management Arms (CMA) are used to estimate the reduction in the cooling airflow rate. In this study, 1 RU and 2 RU servers, and a 9 RU server simulator are used as representative IT equipment. A Computational Fluid Dynamics (CFD) model is used to investigate the influence of the rack structure on the thermal field. The effect of the cooling air flow rate on the temperature of the server's internal components is also studied experimentally.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"31 1","pages":"547-556"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74622908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892277
M. Arik, Kaustubh Kulkarni, C. Royce, S. Weaver
White light emitting diodes (LEDs) are appearing in general illumination applications. Clusters of such LEDs can replace an incandescent light bulb of equal luminosity on the merit of considerably low power consumption. However the optical performance and working life of these LED packages are strongly dependent on the temperature of the p-n junction of the LED. Hence it is very critical to determine the temperature of the junction. Three methods - forward voltage change, peak wavelength shift and infrared thermal imaging are employed to determine the junction temperature. Forward voltage change method is found to be the most accurate method (± 3 °C) for an optimized set of parameters. Analytical model is proposed for the thermal transient behavior of the LED junction and the predictions are compared with experimental results. A good agreement is observed between that of two experimental methods. Thermal resistance of the LED package is estimated analytically and experimentally. Experimental values show a larger variation than expected through material property variation.
{"title":"Developing a standard measurement and calculation procedure for high brightness LED junction temperature","authors":"M. Arik, Kaustubh Kulkarni, C. Royce, S. Weaver","doi":"10.1109/ITHERM.2014.6892277","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892277","url":null,"abstract":"White light emitting diodes (LEDs) are appearing in general illumination applications. Clusters of such LEDs can replace an incandescent light bulb of equal luminosity on the merit of considerably low power consumption. However the optical performance and working life of these LED packages are strongly dependent on the temperature of the p-n junction of the LED. Hence it is very critical to determine the temperature of the junction. Three methods - forward voltage change, peak wavelength shift and infrared thermal imaging are employed to determine the junction temperature. Forward voltage change method is found to be the most accurate method (± 3 °C) for an optimized set of parameters. Analytical model is proposed for the thermal transient behavior of the LED junction and the predictions are compared with experimental results. A good agreement is observed between that of two experimental methods. Thermal resistance of the LED package is estimated analytically and experimentally. Experimental values show a larger variation than expected through material property variation.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"115 1","pages":"170-177"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79000543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892312
Zachary N. Coker, H. Díaz, N. D'Souza, T. Choi
Reliability testing of thermally conductive, high-temperature, high-dielectric strength materials was conducted using newly developed high-temperature thermal conductivity and high-dielectric breakdown voltage characterization instruments based on ASTM Standards. These instruments and tests were used for optimizing thermal conductivity and dielectric breakdown of Bismaleimide Resin (BMI) - Boron Nitride Nanoparticle (BNNP) composites of various weight-percent concentrations for semiconductor packaging. Multiple variations of BMI-BNNP composite samples were fabricated through high-pressure, high-temperature compression molding, and subsequently tested using the developed instruments; it was shown that as the concentration of BN in the composite increased, so did the thermal conductivity and dielectric strength of the material. A near-linear trend was exhibited for thermal conductivity as the BN concentration increased, while the dielectric breakdown voltage showed an exponential increase trend. These thermal conductivity and dielectric breakdown characterization tests were conducted in an effort to develop a high-voltage isolating, high-temperature adhesive that can have tailored thermal conductivity, high dielectric strength, controlled dielectric constant and adhesion to a range of interfaces while retaining mechanical performance and durability.
{"title":"Boron Nitride Nanoparticles-based thermal adhesives for thermal management of high-temperature electronics","authors":"Zachary N. Coker, H. Díaz, N. D'Souza, T. Choi","doi":"10.1109/ITHERM.2014.6892312","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892312","url":null,"abstract":"Reliability testing of thermally conductive, high-temperature, high-dielectric strength materials was conducted using newly developed high-temperature thermal conductivity and high-dielectric breakdown voltage characterization instruments based on ASTM Standards. These instruments and tests were used for optimizing thermal conductivity and dielectric breakdown of Bismaleimide Resin (BMI) - Boron Nitride Nanoparticle (BNNP) composites of various weight-percent concentrations for semiconductor packaging. Multiple variations of BMI-BNNP composite samples were fabricated through high-pressure, high-temperature compression molding, and subsequently tested using the developed instruments; it was shown that as the concentration of BN in the composite increased, so did the thermal conductivity and dielectric strength of the material. A near-linear trend was exhibited for thermal conductivity as the BN concentration increased, while the dielectric breakdown voltage showed an exponential increase trend. These thermal conductivity and dielectric breakdown characterization tests were conducted in an effort to develop a high-voltage isolating, high-temperature adhesive that can have tailored thermal conductivity, high dielectric strength, controlled dielectric constant and adhesion to a range of interfaces while retaining mechanical performance and durability.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"7 1","pages":"421-425"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75437392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892267
Caleb Serafy, Ankur Srivastava, D. Yeung
Core scaling has largely replaced frequency scaling in general purpose microprocessors in the last decade. This is largely because of the high temperature and power dissipation associated with frequency scaling in traditional air cooled systems. In this paper we investigate how this trend changes when micro-fluidic cooling is added to a chip. Compared to traditional air cooling, micro-fluidic cooling can remove significantly more heat from the system, preventing thermal violations and reducing leakage power. This not only makes frequency scaling thermally feasible, but also increases the energy efficiency of higher frequency processors. Vertical integration of circuits (3D ICs) is a promising technology for facilitating a large number of cores, due to the limits on chip footprint size imposed by manufacturing yields. In this work we investigate the advantages of adding micro-fluidic water cooling to 3D stacked DRAM processors and show that such an approach can improve performance an average of 57.4% by making higher frequencies and more cores thermally feasible and improve energy efficiency 13.4% by reducing leakage power.
{"title":"Continued frequency scaling in 3D ICs through micro-fluidic cooling","authors":"Caleb Serafy, Ankur Srivastava, D. Yeung","doi":"10.1109/ITHERM.2014.6892267","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892267","url":null,"abstract":"Core scaling has largely replaced frequency scaling in general purpose microprocessors in the last decade. This is largely because of the high temperature and power dissipation associated with frequency scaling in traditional air cooled systems. In this paper we investigate how this trend changes when micro-fluidic cooling is added to a chip. Compared to traditional air cooling, micro-fluidic cooling can remove significantly more heat from the system, preventing thermal violations and reducing leakage power. This not only makes frequency scaling thermally feasible, but also increases the energy efficiency of higher frequency processors. Vertical integration of circuits (3D ICs) is a promising technology for facilitating a large number of cores, due to the limits on chip footprint size imposed by manufacturing yields. In this work we investigate the advantages of adding micro-fluidic water cooling to 3D stacked DRAM processors and show that such an approach can improve performance an average of 57.4% by making higher frequencies and more cores thermally feasible and improve energy efficiency 13.4% by reducing leakage power.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"26 1","pages":"79-85"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80154680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892407
A. Wemhoff, A. Ortega
A holistic system-level analysis of the energy and mass transfer in a data center cooling system is used to determine the exergy destruction by each component in the system. The analysis, performed using our in-house analysis code, allows for identification of system inefficiencies and comparison of the energy efficiency of different data center cooling strategies. In this paper, we describe a systematic analysis of the exergy destruction in a traditional air-cooled strategy and a hybrid liquid-air system containing rear door heat exchangers (RDHXs). The results show that the exergy destruction by RDHXs increases with the amount of rack heat removal. However, the removal of rack heat concurrently decreases the heat removal and exergy destruction by computer room air handling (CRAH) units. The resultant overall exergy destruction is increased when both RDHX and CRAH units are in operation, but this gain in exergy may be attributed to low heat exchanger effectiveness values. The analysis also shows that when all heat is removed by the RDHX, the exergy destruction is lower than when all heat is removed by the CRAH, suggesting that the data center energy efficiency can be increased through the use of localized hybrid liquid-air cooling schemes as compared to centralized air cooled strategies.
{"title":"An exergy-based analysis of the effects of rear door heat exchange systems on data center energy efficiency","authors":"A. Wemhoff, A. Ortega","doi":"10.1109/ITHERM.2014.6892407","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892407","url":null,"abstract":"A holistic system-level analysis of the energy and mass transfer in a data center cooling system is used to determine the exergy destruction by each component in the system. The analysis, performed using our in-house analysis code, allows for identification of system inefficiencies and comparison of the energy efficiency of different data center cooling strategies. In this paper, we describe a systematic analysis of the exergy destruction in a traditional air-cooled strategy and a hybrid liquid-air system containing rear door heat exchangers (RDHXs). The results show that the exergy destruction by RDHXs increases with the amount of rack heat removal. However, the removal of rack heat concurrently decreases the heat removal and exergy destruction by computer room air handling (CRAH) units. The resultant overall exergy destruction is increased when both RDHX and CRAH units are in operation, but this gain in exergy may be attributed to low heat exchanger effectiveness values. The analysis also shows that when all heat is removed by the RDHX, the exergy destruction is lower than when all heat is removed by the CRAH, suggesting that the data center energy efficiency can be increased through the use of localized hybrid liquid-air cooling schemes as compared to centralized air cooled strategies.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"303 1","pages":"1129-1136"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76439872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892311
Terry G. Davis, D. Rocco, J. Lorenzo
Thermal energy of many electronic components is currently managed using a heat sink cast of a conductive metal alloy. This method requires significant secondary assembly of many sub-components such as fasteners, thermal interface materials and potting compounds. A unique combination of thermally conductive polycarbonate, insulating polyurethane, in-mold electronic component assembly and encapsulation reduces the number of components while creating a finished part in a mold without the need for manual assembly. The benefits vs. traditional manufacturing are reduction in labor cost, increased supplier competition and improved thermal performance through the elimination of thermal interface materials (TIM). In-mold bonding of the printed circuit board (PCB) to the polycarbonate can reduce steady state temperature by creating solid thermal paths eliminating TIM resistance [1]. A second step using polyurethane encapsulation of other PCB's such as driver boards in the assembly replaces the current potting step necessary in some components. A fully automated integrated work cell utilizing the in mold encapsulation technique has the potential to help LED luminaire manufacturers achieve a lower price to market and streamline manufacturing of electronics designs needing passive thermal management.
{"title":"Thermal management of electronic components using Makrolon polycarbonate and Bayflex polyurethane","authors":"Terry G. Davis, D. Rocco, J. Lorenzo","doi":"10.1109/ITHERM.2014.6892311","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892311","url":null,"abstract":"Thermal energy of many electronic components is currently managed using a heat sink cast of a conductive metal alloy. This method requires significant secondary assembly of many sub-components such as fasteners, thermal interface materials and potting compounds. A unique combination of thermally conductive polycarbonate, insulating polyurethane, in-mold electronic component assembly and encapsulation reduces the number of components while creating a finished part in a mold without the need for manual assembly. The benefits vs. traditional manufacturing are reduction in labor cost, increased supplier competition and improved thermal performance through the elimination of thermal interface materials (TIM). In-mold bonding of the printed circuit board (PCB) to the polycarbonate can reduce steady state temperature by creating solid thermal paths eliminating TIM resistance [1]. A second step using polyurethane encapsulation of other PCB's such as driver boards in the assembly replaces the current potting step necessary in some components. A fully automated integrated work cell utilizing the in mold encapsulation technique has the potential to help LED luminaire manufacturers achieve a lower price to market and streamline manufacturing of electronics designs needing passive thermal management.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"31 1","pages":"418-420"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80919432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892309
H. Zhang, S. Li, H. Liu, J. Bunt, F. Pompeo, K. Sikka, K. Rivera, H. Longworth, C. Lian
This paper discusses a thermal reliability testing experiment and failure analysis (FA) in 32nm SOI Si technology chip packages. Thermal performance of the TIM materials is monitored and physical failure analysis is performed on test vehicle packages post thermal reliability test. Thermomechanical modeling is conducted for different test conditions. TIM thermal degradation is observed at the chip center area in the batch of samples post power cycling (PC) test, while the TIM performance remains normal in the other batch of samples post thermal aging (TA) test. Physical FA findings after TIM bond line thickness measurement (at the chip corners and chip center) and unlidding to inspect the TIM surface morphology confirmed the failure mode is TIM to chip tearing. Finite element modeling results indicate significant difference of stress status in TIM and sealband adhesive between PC and TA test. The TIM experiences compressive stress during PC test, while it is in tensile stress during TA test.
本文讨论了32nm SOI Si工艺芯片封装的热可靠性测试实验和失效分析(FA)。对TIM材料的热性能进行了监测，并对热可靠性测试后的测试车辆封装进行了物理失效分析。对不同的试验条件进行了热力学建模。在电源循环(PC)测试后的一批样品中，在芯片中心区域观察到TIM的热退化，而在热老化(TA)测试后的另一批样品中，TIM的性能保持正常。通过测量TIM键合线厚度(在切屑的边角和切屑的中心)和开箱检查TIM表面形貌后的物理FA结果证实了TIM对切屑的撕裂破坏模式。有限元模拟结果表明，PC和TA试验对TIM和密封胶粘剂的应力状态有显著差异。在PC试验中，TIM处于压应力状态，在TA试验中，TIM处于拉应力状态。
{"title":"Failure analysis of thermal degradation of TIM during power cycling","authors":"H. Zhang, S. Li, H. Liu, J. Bunt, F. Pompeo, K. Sikka, K. Rivera, H. Longworth, C. Lian","doi":"10.1109/ITHERM.2014.6892309","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892309","url":null,"abstract":"This paper discusses a thermal reliability testing experiment and failure analysis (FA) in 32nm SOI Si technology chip packages. Thermal performance of the TIM materials is monitored and physical failure analysis is performed on test vehicle packages post thermal reliability test. Thermomechanical modeling is conducted for different test conditions. TIM thermal degradation is observed at the chip center area in the batch of samples post power cycling (PC) test, while the TIM performance remains normal in the other batch of samples post thermal aging (TA) test. Physical FA findings after TIM bond line thickness measurement (at the chip corners and chip center) and unlidding to inspect the TIM surface morphology confirmed the failure mode is TIM to chip tearing. Finite element modeling results indicate significant difference of stress status in TIM and sealband adhesive between PC and TA test. The TIM experiences compressive stress during PC test, while it is in tensile stress during TA test.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"6 1","pages":"404-408"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82221510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892281
B. d'Entremont, J. Marcinichen, J. Thome
Three-dimensional integration of multiple stacked silicon dies using Through-Silicon Vias has been recognized as a likely future direction of integrated circuit design. Yet, in contrast to previous architectures such 3D-ICs require extensive attention to thermal management from the moment of conception. Although such stacks are often associated with integrated, interlayer cooling solutions, it is conceivable that a single microchannel evaporator might provide a simpler cooling solution to support a stack of modest size, especially if made from dies of 50-μm thickness, that are now feasible to manufacture. The current study explores such a solution for a stack of 6 layers, focusing on the interaction of hot spot placement among the layers with the two-phase cooling and flow distribution among the channels of the micro-evaporator. The simulation code is based on numerous methods proven experimentally to work well for the present small size of channels and fluid. The study suggests that such configurations are feasible, yet require careful consideration of the effect of hot spot placement to yield good micro-evaporator performance and safe cooling of the electrical components.
{"title":"Analysis of flow and heat distribution in a 3D stack of chips and memories with back side two-phase cooling","authors":"B. d'Entremont, J. Marcinichen, J. Thome","doi":"10.1109/ITHERM.2014.6892281","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892281","url":null,"abstract":"Three-dimensional integration of multiple stacked silicon dies using Through-Silicon Vias has been recognized as a likely future direction of integrated circuit design. Yet, in contrast to previous architectures such 3D-ICs require extensive attention to thermal management from the moment of conception. Although such stacks are often associated with integrated, interlayer cooling solutions, it is conceivable that a single microchannel evaporator might provide a simpler cooling solution to support a stack of modest size, especially if made from dies of 50-μm thickness, that are now feasible to manufacture. The current study explores such a solution for a stack of 6 layers, focusing on the interaction of hot spot placement among the layers with the two-phase cooling and flow distribution among the channels of the micro-evaporator. The simulation code is based on numerous methods proven experimentally to work well for the present small size of channels and fluid. The study suggests that such configurations are feasible, yet require careful consideration of the effect of hot spot placement to yield good micro-evaporator performance and safe cooling of the electrical components.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"19 1","pages":"193-198"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84233562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892400
R. Kibushi, T. Hatakeyama, S. Nakagawa, M. Ishizuka
This paper describes the effect of cooling from a surface of power Si MOSFET on hot spot temperature. In traditional thermal design of electronics, the temperature distribution of chips is assumed to be uniform for simplicity of thermal design. However, in recent years, thermal problems of electronics are more serious, because electronics have been downsizing. Therefore, we should consider the temperature distribution of the chips. In a chip, semiconductor devices are mounted, and the generation of hot spots in semiconductor devices is widely known. Therefore, the chip has non-uniform temperature distribution. However, the detail of thermal properties of power Si MOSFET, which is one type of transistor, is not clear. Power Si MOSFET has large thermal problems, because high voltage is applied to power Si MOSFET. Therefore, we should obtain thermal properties of power Si MOSFET. Thus, the objective of this study is investigation of thermal properties of power Si MOSFET for high reliability of electronics. In this paper, as a fundamental study, we investigate the effect of cooling from the surfaces of power Si MOSFET on hot spot temperature using electro-thermal analysis. As a result, it was investigated that the effect of cooling from the top surface of the device on hot spot temperature is small.
{"title":"The effect of cooling from surface of power Si MOSFET on hot spot temperature","authors":"R. Kibushi, T. Hatakeyama, S. Nakagawa, M. Ishizuka","doi":"10.1109/ITHERM.2014.6892400","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892400","url":null,"abstract":"This paper describes the effect of cooling from a surface of power Si MOSFET on hot spot temperature. In traditional thermal design of electronics, the temperature distribution of chips is assumed to be uniform for simplicity of thermal design. However, in recent years, thermal problems of electronics are more serious, because electronics have been downsizing. Therefore, we should consider the temperature distribution of the chips. In a chip, semiconductor devices are mounted, and the generation of hot spots in semiconductor devices is widely known. Therefore, the chip has non-uniform temperature distribution. However, the detail of thermal properties of power Si MOSFET, which is one type of transistor, is not clear. Power Si MOSFET has large thermal problems, because high voltage is applied to power Si MOSFET. Therefore, we should obtain thermal properties of power Si MOSFET. Thus, the objective of this study is investigation of thermal properties of power Si MOSFET for high reliability of electronics. In this paper, as a fundamental study, we investigate the effect of cooling from the surfaces of power Si MOSFET on hot spot temperature using electro-thermal analysis. As a result, it was investigated that the effect of cooling from the top surface of the device on hot spot temperature is small.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"48 1","pages":"1074-1078"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86045594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ITHERM.2014.6892388
K. Nishi, T. Hatakeyama, S. Nakagawa, M. Ishizuka
This paper investigates transient temperature prediction of microprocessor hot spot by utilizing one-dimensional thermal network with average temperature nodes. Different from traditional thermal network, introduced one-dimensional thermal network in this paper consists of not only material thermal resistances and material thermal capacitances but also thermal spreading resistances and a thermal local resistance. Basic concept and construction of the thermal network are firstly introduced, one-dimensional thermal network for the microprocessor system is secondly created and transient models for heat sink fan and thermal spreading resistances are thirdly introduced to obtain sufficient temperature transient result in this paper. After that, thermal analysis is conducted with constructed one-dimensional thermal network by applying microprocessor power consumption calculated by power estimation equation which considers voltage and temperature dependency time by time. Transient thermal resistance of heat sink fan and transient thermal spreading resistances are evaluated to discuss temperature transient result. It is found that heat sink thermal resistance need to be considered to obtain more precise temperature result though obtained result has practical accuracy.
{"title":"Transient thermal analysis of the microprocessor system one-dimensional thermal network with power estimation equation","authors":"K. Nishi, T. Hatakeyama, S. Nakagawa, M. Ishizuka","doi":"10.1109/ITHERM.2014.6892388","DOIUrl":"https://doi.org/10.1109/ITHERM.2014.6892388","url":null,"abstract":"This paper investigates transient temperature prediction of microprocessor hot spot by utilizing one-dimensional thermal network with average temperature nodes. Different from traditional thermal network, introduced one-dimensional thermal network in this paper consists of not only material thermal resistances and material thermal capacitances but also thermal spreading resistances and a thermal local resistance. Basic concept and construction of the thermal network are firstly introduced, one-dimensional thermal network for the microprocessor system is secondly created and transient models for heat sink fan and thermal spreading resistances are thirdly introduced to obtain sufficient temperature transient result in this paper. After that, thermal analysis is conducted with constructed one-dimensional thermal network by applying microprocessor power consumption calculated by power estimation equation which considers voltage and temperature dependency time by time. Transient thermal resistance of heat sink fan and transient thermal spreading resistances are evaluated to discuss temperature transient result. It is found that heat sink thermal resistance need to be considered to obtain more precise temperature result though obtained result has practical accuracy.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"13 1","pages":"982-989"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87822938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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