Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525949
Weilun Liu, Hengyang Zhang, B. Zheng, Weiting Gao, Zhikang Qin
In the contention-based MAC protocols of airborne networks, the busy degree of channels can be used as the threshold of different priority services. By limiting access of low priority traffic, we can guarantee the QoS demands of high priority services and solve the problem that the process of packets accessed channels blindly will worsen the protocol performance, so, a multi-channel statistical prediction strategy is proposed in this paper. According to the high reliability demand of the highest priority traffic and the ratio of different types of services, we establish the channel occupancy model and get the channel load interval of different services. Then we use the statistical prediction model to predict the busy degree of channels and channel loads for the next time. Simulation results show that the strategy has a prediction rate of over 95% for channel loads, can provide differential service for different priorities, and it also can significantly improve the performance of contention-based protocol under heavy loads.
{"title":"A Novel Multi-channel Statistical Predicted Strategy for Airborne Networks","authors":"Weilun Liu, Hengyang Zhang, B. Zheng, Weiting Gao, Zhikang Qin","doi":"10.1109/CIRSYSSIM.2018.8525949","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525949","url":null,"abstract":"In the contention-based MAC protocols of airborne networks, the busy degree of channels can be used as the threshold of different priority services. By limiting access of low priority traffic, we can guarantee the QoS demands of high priority services and solve the problem that the process of packets accessed channels blindly will worsen the protocol performance, so, a multi-channel statistical prediction strategy is proposed in this paper. According to the high reliability demand of the highest priority traffic and the ratio of different types of services, we establish the channel occupancy model and get the channel load interval of different services. Then we use the statistical prediction model to predict the busy degree of channels and channel loads for the next time. Simulation results show that the strategy has a prediction rate of over 95% for channel loads, can provide differential service for different priorities, and it also can significantly improve the performance of contention-based protocol under heavy loads.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525967
Jinlong Hu, Jie Sun, Yangbo Bai, Huachao Xu, Tao Du, Guofeng Li, Yao Chen
This paper proposes a novel bandgap voltage reference with an accurate curvature compensation technique for completely compensating the thermal nonlinearity of the emitter-base voltage. With VIS 0.15 standard CMOS process, the proposed bandgap voltage reference circuit achieves temperature coefficient of 1.03 ppm/°C over the temperature range from −55°C to 155°C with the supply voltage of 1.8V. In addition, the circuit achieves line regulation performance of 0.02%/V with the supply voltage from 1.8V to 3V and the power supply rejection (PSR) levels are 83dB, 77dB, 58dB at ultra-low frequency (<200Hz), 1kHz and 10kHz, respectively.
{"title":"A Novel 1.03 ppm/°C Wide-Temperature-Range Curvature-Compensated Bandgap Voltage Reference","authors":"Jinlong Hu, Jie Sun, Yangbo Bai, Huachao Xu, Tao Du, Guofeng Li, Yao Chen","doi":"10.1109/CIRSYSSIM.2018.8525967","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525967","url":null,"abstract":"This paper proposes a novel bandgap voltage reference with an accurate curvature compensation technique for completely compensating the thermal nonlinearity of the emitter-base voltage. With VIS 0.15 standard CMOS process, the proposed bandgap voltage reference circuit achieves temperature coefficient of 1.03 ppm/°C over the temperature range from −55°C to 155°C with the supply voltage of 1.8V. In addition, the circuit achieves line regulation performance of 0.02%/V with the supply voltage from 1.8V to 3V and the power supply rejection (PSR) levels are 83dB, 77dB, 58dB at ultra-low frequency (<200Hz), 1kHz and 10kHz, respectively.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129410508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525958
Yingying Chi, Zhe Zheng
This paper presents a complete Register Transfer Level (RTL) design of Direct Memory Access (DMA) controller which is compliable with the Advanced Highperformance Bus (AHB). The DMA is integrated in Cortex-M3-based system-on-chip (SoC) designed for power-grid-dedicated wireless communication system based on IEEE 802.11ah protocol. The hardware implementation and prototype verification indicate that by allowing hardware devices working at different frequencies to communicate with each other without relying on the heavy outage load of CPU, the proposed DMA controller realizes the good convergence with the whole system and improves the overall performance with low power consumption.
{"title":"A Design of Direct Memory Access Controller for Wireless Communication SoC in Power Grid","authors":"Yingying Chi, Zhe Zheng","doi":"10.1109/CIRSYSSIM.2018.8525958","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525958","url":null,"abstract":"This paper presents a complete Register Transfer Level (RTL) design of Direct Memory Access (DMA) controller which is compliable with the Advanced Highperformance Bus (AHB). The DMA is integrated in Cortex-M3-based system-on-chip (SoC) designed for power-grid-dedicated wireless communication system based on IEEE 802.11ah protocol. The hardware implementation and prototype verification indicate that by allowing hardware devices working at different frequencies to communicate with each other without relying on the heavy outage load of CPU, the proposed DMA controller realizes the good convergence with the whole system and improves the overall performance with low power consumption.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123741429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/CIRSYSSIM.2018.8525876
Jie Liu, Y. Ban
A model-centered design flow and trade-off of a compact size radio frequency (RF) filter has been presented in this paper, which has advantages of reduced schematic-layout iteration and improved design efficiency. The RF bandpass filter achieves a bandwidth of 300 MHz ranging from 3.3 GHz to 3.6 GHz, a reasonably high return loss, and an insertion loss below 2.7 dB throughout the whole bandwidth. Besides, the proposed design provides good separation from nearby bands, such as: UHF band, Wi-Fi and 2.4 GHz ISM applications. In addition, the influence of wire bonding package has been modeled and simulated, in order to minimize the degradation of package on the overall performance during the probe measurements. The filter is implemented in a high resistivity silicon integrated passive device process, featuring a compact die area of 0.75 mm2, including seal ring at each side of the chip.
{"title":"Miniaturized Bandpass Filter Using IPD Technology with a Novel Design Flow","authors":"Jie Liu, Y. Ban","doi":"10.1109/CIRSYSSIM.2018.8525876","DOIUrl":"https://doi.org/10.1109/CIRSYSSIM.2018.8525876","url":null,"abstract":"A model-centered design flow and trade-off of a compact size radio frequency (RF) filter has been presented in this paper, which has advantages of reduced schematic-layout iteration and improved design efficiency. The RF bandpass filter achieves a bandwidth of 300 MHz ranging from 3.3 GHz to 3.6 GHz, a reasonably high return loss, and an insertion loss below 2.7 dB throughout the whole bandwidth. Besides, the proposed design provides good separation from nearby bands, such as: UHF band, Wi-Fi and 2.4 GHz ISM applications. In addition, the influence of wire bonding package has been modeled and simulated, in order to minimize the degradation of package on the overall performance during the probe measurements. The filter is implemented in a high resistivity silicon integrated passive device process, featuring a compact die area of 0.75 mm2, including seal ring at each side of the chip.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124047807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-20DOI: 10.12783/DTETR/ICMEIT2018/23436
Honghui Tang, Tao Qin, Zhijian Hui, Pengyu Cheng, Wensong Bai
Pseudo random number generators (PRNGs) play an important role in many fields such as encryption and hardware testing. One common structure of PRNGs is linear feedback shifting register (LFSR), which generate a n-bit sequence from a specific seed. However, the sequence of random numbers can be predicted given a fixed seed and some sequences of generated numbers. Considering the drawbacks of available LSFR-based PRNGs, in this paper we devised a configurable and aperiodic LSFR-based PRNG, which utilize the unpredictability of metastable state widely existed in digital circuits. In this case, the sequence of random numbers is almost unpredictable and can meet the requirements of most applications especially critical ones. Then we implemented it on FPGA and the simulation results indicate that the proposed PRNG has better performance in generating random numbers with high randomness.
{"title":"Design and Implementation of a Configurable and Aperiodic Pseudo Random Number Generator in FPGA","authors":"Honghui Tang, Tao Qin, Zhijian Hui, Pengyu Cheng, Wensong Bai","doi":"10.12783/DTETR/ICMEIT2018/23436","DOIUrl":"https://doi.org/10.12783/DTETR/ICMEIT2018/23436","url":null,"abstract":"Pseudo random number generators (PRNGs) play an important role in many fields such as encryption and hardware testing. One common structure of PRNGs is linear feedback shifting register (LFSR), which generate a n-bit sequence from a specific seed. However, the sequence of random numbers can be predicted given a fixed seed and some sequences of generated numbers. Considering the drawbacks of available LSFR-based PRNGs, in this paper we devised a configurable and aperiodic LSFR-based PRNG, which utilize the unpredictability of metastable state widely existed in digital circuits. In this case, the sequence of random numbers is almost unpredictable and can meet the requirements of most applications especially critical ones. Then we implemented it on FPGA and the simulation results indicate that the proposed PRNG has better performance in generating random numbers with high randomness.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126719747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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