Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524678
M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov
An approach to analyze PLL jitter under noise excitations of the different origin is considered in the paper. Both internal device noise and external switching noise can be captured by the proposed approach. Jitter evaluation is provided by obtaining phase transfer functions (TF) from any circuit node to the PLL output. Unlike previous works explaining noise folding in PLL by sampling processes, this paper shows that spectrum aliasing in PLL blocks appears in both digital and analog PLL due to principal properties of Linear Periodically Time- Varying (LPTV) systems. Expressions for the evaluation TF of PLL blocks are presented. The PLL macromodel developed in the form of block diagram allowed the authors to derive the set of PLL TFs. Different approaches to the evaluation of the phase TF by additive TFs of electrical harmonics are discussed.
{"title":"Development of Time-Varying PLL Macromodel for Jitter Evaluation","authors":"M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov","doi":"10.1109/EWDTS.2018.8524678","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524678","url":null,"abstract":"An approach to analyze PLL jitter under noise excitations of the different origin is considered in the paper. Both internal device noise and external switching noise can be captured by the proposed approach. Jitter evaluation is provided by obtaining phase transfer functions (TF) from any circuit node to the PLL output. Unlike previous works explaining noise folding in PLL by sampling processes, this paper shows that spectrum aliasing in PLL blocks appears in both digital and analog PLL due to principal properties of Linear Periodically Time- Varying (LPTV) systems. Expressions for the evaluation TF of PLL blocks are presented. The PLL macromodel developed in the form of block diagram allowed the authors to derive the set of PLL TFs. Different approaches to the evaluation of the phase TF by additive TFs of electrical harmonics are discussed.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122039643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524806
A. Drozd, M. Kuznietsov, S. Antoshchuk, Alexander N. Martynyuk, M. Drozd, Y. Sulima
This paper is devoted to a problem of the hidden faults which is shown in digital components of the safety-related systems aimed at providing of the functional safety of objects with the increased risk. These systems are considered on the basis of resource approach as development of computer systems with diversification of an operating mode by its division on normal and emergency. The problem consists in accumulation of faults throughout a continuous normal mode in absence of the input data showing them. In the most responsible emergency mode, accumulated faults are shown in lowering of fault tolerance on which the functional safety is based. The problem of the hidden faults is identified as a problem in development of resources where diversification of a checkability of the circuits contradicts designing of the digital components at the bottom level of resource development - replication. Problem solutions by increase in the level of resource development in designing of the digital components, including a method of a choice of the version in program codes of the FPGA project are suggested.
{"title":"Evolution of a Problem of the Hidden Faults in the Digital Components of Safety-Related Systens","authors":"A. Drozd, M. Kuznietsov, S. Antoshchuk, Alexander N. Martynyuk, M. Drozd, Y. Sulima","doi":"10.1109/EWDTS.2018.8524806","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524806","url":null,"abstract":"This paper is devoted to a problem of the hidden faults which is shown in digital components of the safety-related systems aimed at providing of the functional safety of objects with the increased risk. These systems are considered on the basis of resource approach as development of computer systems with diversification of an operating mode by its division on normal and emergency. The problem consists in accumulation of faults throughout a continuous normal mode in absence of the input data showing them. In the most responsible emergency mode, accumulated faults are shown in lowering of fault tolerance on which the functional safety is based. The problem of the hidden faults is identified as a problem in development of resources where diversification of a checkability of the circuits contradicts designing of the digital components at the bottom level of resource development - replication. Problem solutions by increase in the level of resource development in designing of the digital components, including a method of a choice of the version in program codes of the FPGA project are suggested.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":" 979","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113946597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524602
Valentina Potapova, A.Yu. Tarasov, N. Grinchenko
The article considers image processing methods, such as method of query by content and Bayesian segmentation method. Application of both methods together promotes improvement of image search results.
本文考虑了图像处理方法，如按内容查询法和贝叶斯分割法。两种方法的共同应用促进了图像搜索结果的改善。
{"title":"Image Search by Content System Development","authors":"Valentina Potapova, A.Yu. Tarasov, N. Grinchenko","doi":"10.1109/EWDTS.2018.8524602","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524602","url":null,"abstract":"The article considers image processing methods, such as method of query by content and Bayesian segmentation method. Application of both methods together promotes improvement of image search results.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130007432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524708
Alexey Malvshev, Ivan Malav, M. Ozerov
A method of digital processing of global positioning system navigation signal is proposed. It allows to separate evaluation of spectral and energy characteristics of signal components. Main advantages of the method is: increasing a dynamic range by more than 10 dB, separation of navigation signal components under conditions of a priori information absence about a generating polynomial. The method is based on extracting the spreading sequences of a navigational signal by the method of quadrature heterodyning with filtration of components of one quadrature and subsequent correlation processing of an initial signal.
{"title":"Algorithm for Separating GNSS Signals into Components","authors":"Alexey Malvshev, Ivan Malav, M. Ozerov","doi":"10.1109/EWDTS.2018.8524708","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524708","url":null,"abstract":"A method of digital processing of global positioning system navigation signal is proposed. It allows to separate evaluation of spectral and energy characteristics of signal components. Main advantages of the method is: increasing a dynamic range by more than 10 dB, separation of navigation signal components under conditions of a priori information absence about a generating polynomial. The method is based on extracting the spreading sequences of a navigational signal by the method of quadrature heterodyning with filtration of components of one quadrature and subsequent correlation processing of an initial signal.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130033157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524671
D. Letavin, V. Chechetkin, Y. Mitelman
In this paper, we consider the possibility of miniaturization of a broadband quadrature coupler using low-pass filters that have the same phase shift as the replaced segment of microstrip line. Numerical simulation of the proposed four-stub coupler with a central frequency tuned to 2000 MHz is conducted. The decoupling band at the level of −20 dB of such a device is around 1000 MHz. The dimensions of the coupler are 37 mm × 14 mm = 518 mm2, which is 65.3% less than the standard one. The experimental results coincide with the results of the simulation with a small error.
{"title":"Compact Four-Stub Coupler","authors":"D. Letavin, V. Chechetkin, Y. Mitelman","doi":"10.1109/EWDTS.2018.8524671","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524671","url":null,"abstract":"In this paper, we consider the possibility of miniaturization of a broadband quadrature coupler using low-pass filters that have the same phase shift as the replaced segment of microstrip line. Numerical simulation of the proposed four-stub coupler with a central frequency tuned to 2000 MHz is conducted. The decoupling band at the level of −20 dB of such a device is around 1000 MHz. The dimensions of the coupler are 37 mm × 14 mm = 518 mm2, which is 65.3% less than the standard one. The experimental results coincide with the results of the simulation with a small error.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130939619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524759
P. Belyakov, M. Nikiforov
The variational methods for dense optical flow estimation are widely known and adopted techniques for motion detection, object tracking, 3D reconstruction and autonomous navigation in image processing applications. A non-linear model of variational optical flow estimation is the most accurate but also most complicated and computationally intensive method and its implementation in an FPGA is compromise from both a design complexity and a performance. The article is devoted to the specific FPGA-based solution which has been implemented using Verilog hardware description language. The suggested solution is able to process the non-linear optical flow in real time and might be applied as FPGA -accelerator for optical flow processing.
{"title":"An FPGA-Optimized Architecture of Variational Optical Flow","authors":"P. Belyakov, M. Nikiforov","doi":"10.1109/EWDTS.2018.8524759","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524759","url":null,"abstract":"The variational methods for dense optical flow estimation are widely known and adopted techniques for motion detection, object tracking, 3D reconstruction and autonomous navigation in image processing applications. A non-linear model of variational optical flow estimation is the most accurate but also most complicated and computationally intensive method and its implementation in an FPGA is compromise from both a design complexity and a performance. The article is devoted to the specific FPGA-based solution which has been implemented using Verilog hardware description language. The suggested solution is able to process the non-linear optical flow in real time and might be applied as FPGA -accelerator for optical flow processing.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524640
O. Dvornikov, N. Prokopenko, A. Bugakova, V. Tchekhovski, I. Maliy
Features of the design of operational amplifiers (Op-Amp) on complementary field effect transistors with p-n- junction (junction field-effect transistor, JFET) for operation under the influence of penetrating radiation (PR) and extremely low temperatures up to −197°C are considered. The original circuit of the Op-Amp and the results of its circuit simulation are given.
{"title":"Cryogenic Operational Amplifier on Complementary JFETs","authors":"O. Dvornikov, N. Prokopenko, A. Bugakova, V. Tchekhovski, I. Maliy","doi":"10.1109/EWDTS.2018.8524640","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524640","url":null,"abstract":"Features of the design of operational amplifiers (Op-Amp) on complementary field effect transistors with p-n- junction (junction field-effect transistor, JFET) for operation under the influence of penetrating radiation (PR) and extremely low temperatures up to −197°C are considered. The original circuit of the Op-Amp and the results of its circuit simulation are given.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127984687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524668
V. Kureichik, I. Safronenkova
The present work deals with artificial intelligence research. The problem of engineering software benchmarking study for the purpose of fitting for task type and computational resources is important today. This problem is often solved by the help of intelligence decision support systems (IDSS). Domain ontology is a typical knowledge representation model in such systems. Manual ontology development is a time-consuming and expensive process. Because of a great variety of circuit partitioning problem formulization, clustering is a necessary step of automated circuit partitioning problem ontology development. The problem of automated circuit partitioning problem clustering appears because of integrated data comparison. This data is represented by different dimension structures. The goal of this work is the development of circuit partitioning problem clustering method based on adjacency matrix unification. The hypergraph model of circuit representation was chosen, circuit partitioning problem was formalized. The case of adjacency matrix with different dimension clustering was observed. The novelty of proposed method is the inclusion of matrix with different dimension unification procedure in the generic clustering method.
{"title":"Circuit Partitioning Problem Clustering Method Based on Adjacency Matrix Unification","authors":"V. Kureichik, I. Safronenkova","doi":"10.1109/EWDTS.2018.8524668","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524668","url":null,"abstract":"The present work deals with artificial intelligence research. The problem of engineering software benchmarking study for the purpose of fitting for task type and computational resources is important today. This problem is often solved by the help of intelligence decision support systems (IDSS). Domain ontology is a typical knowledge representation model in such systems. Manual ontology development is a time-consuming and expensive process. Because of a great variety of circuit partitioning problem formulization, clustering is a necessary step of automated circuit partitioning problem ontology development. The problem of automated circuit partitioning problem clustering appears because of integrated data comparison. This data is represented by different dimension structures. The goal of this work is the development of circuit partitioning problem clustering method based on adjacency matrix unification. The hypergraph model of circuit representation was chosen, circuit partitioning problem was formalized. The case of adjacency matrix with different dimension clustering was observed. The novelty of proposed method is the inclusion of matrix with different dimension unification procedure in the generic clustering method.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127437068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524761
N. Bazaev, B. M. Putrya, N. Zhilo, V. Grinval'd
Wearable artificial kidney (WAK) can change the approach to artificial blood purification and overcome disadvantages of hemodialysis and peritoneal dialysis. WAK implements combination of dialysate regeneration methods that are sorption with electrolysis or enzymatic urea elimination. The aim of work is to determine main requirements and basic approaches of WAK development. Tasks: develop test bench and conduct experiments for evaluation of electrochemical and enzymatic dialysate regeneration methods. Results: combination of sorption and electrolysis remove urea more intensively than complex sorption column with urease, while keeping stable ion balance. Scientific novelty: direct comparison of electrolysis and enzymatic method of waste dialysate regeneration in aspects of ion balance and urea elimination.
{"title":"Wearable Artificial Kidney Design Principles","authors":"N. Bazaev, B. M. Putrya, N. Zhilo, V. Grinval'd","doi":"10.1109/EWDTS.2018.8524761","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524761","url":null,"abstract":"Wearable artificial kidney (WAK) can change the approach to artificial blood purification and overcome disadvantages of hemodialysis and peritoneal dialysis. WAK implements combination of dialysate regeneration methods that are sorption with electrolysis or enzymatic urea elimination. The aim of work is to determine main requirements and basic approaches of WAK development. Tasks: develop test bench and conduct experiments for evaluation of electrochemical and enzymatic dialysate regeneration methods. Results: combination of sorption and electrolysis remove urea more intensively than complex sorption column with urease, while keeping stable ion balance. Scientific novelty: direct comparison of electrolysis and enzymatic method of waste dialysate regeneration in aspects of ion balance and urea elimination.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524673
Slimane Boutobza, Sorin Popa, Andrea Costa
With the growing complexity of System-On-Chips (SoCs), and the explosion of test data volume, test patterns validation is becoming a mandatory and crucial step. With modern large designs, detecting most issues at the level of the ATE is no longer a viable solution. Recent approaches rely on dedicated tools and flows prior to tester to validate test patterns, and reserve ATE to only screening real defect issues on the test-chip. This allows for early detection of successive and cumulative modeling and processing steps. In [1] we presented an original simulation-based patterns validation approach. A crucial step in that approach was the translation from cycle-based tester domain to an event-based simulation domain. This paper focuses on that part by presenting an approach for efficient and trustful translation of a STIL file to an equivalent HDL (Verilog) representation. To the best of our knowledge, this is the first paper that describes a full and detailed tester based language (STIL) to an HDL (Verilog) translation, thereby expressing fully and accurately the behavior of cycle based domain into an event-based environment. Such transformation allows porting the problem from tester domain to HDL and logic simulation domain, and exploiting their capabilities for sake of efficient validation, but also, debug, coverage and functional tests. The proposed approach is an industry proven methodology that was successfully implemented and exploited by an EDA tool [2] that is now used by several semiconductors companies for their daily pattern validation flows.
{"title":"A Journey from STIL to Verilog","authors":"Slimane Boutobza, Sorin Popa, Andrea Costa","doi":"10.1109/EWDTS.2018.8524673","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524673","url":null,"abstract":"With the growing complexity of System-On-Chips (SoCs), and the explosion of test data volume, test patterns validation is becoming a mandatory and crucial step. With modern large designs, detecting most issues at the level of the ATE is no longer a viable solution. Recent approaches rely on dedicated tools and flows prior to tester to validate test patterns, and reserve ATE to only screening real defect issues on the test-chip. This allows for early detection of successive and cumulative modeling and processing steps. In [1] we presented an original simulation-based patterns validation approach. A crucial step in that approach was the translation from cycle-based tester domain to an event-based simulation domain. This paper focuses on that part by presenting an approach for efficient and trustful translation of a STIL file to an equivalent HDL (Verilog) representation. To the best of our knowledge, this is the first paper that describes a full and detailed tester based language (STIL) to an HDL (Verilog) translation, thereby expressing fully and accurately the behavior of cycle based domain into an event-based environment. Such transformation allows porting the problem from tester domain to HDL and logic simulation domain, and exploiting their capabilities for sake of efficient validation, but also, debug, coverage and functional tests. The proposed approach is an industry proven methodology that was successfully implemented and exploited by an EDA tool [2] that is now used by several semiconductors companies for their daily pattern validation flows.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：