Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130733
E. Neufeld
The author has suggested earlier that the various nonmonotonic reasoning formalisms are converging towards probability. Here, he discusses the idea of randomness: using a definition by Kyburg as a benchmark, he describes how it appears in various nonmonotonic reasoning formalisms, in particular, circumscription. It is argued that behind the complexity of circumscription lie the simple notions of random sampling and statistically founded beliefs. The latter is implemented through a device known as the abnormality predicate which appears in various guises in the nonmonotonic reasoning literature. Another view of this study is that randomness provides a universal conjecture for nonmonotonic theories. Default theories can be interpreted as jumping to the conclusion that an entity is a random member of a certain class.<>
{"title":"The abnormality predicate","authors":"E. Neufeld","doi":"10.1109/ISMVL.1991.130733","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130733","url":null,"abstract":"The author has suggested earlier that the various nonmonotonic reasoning formalisms are converging towards probability. Here, he discusses the idea of randomness: using a definition by Kyburg as a benchmark, he describes how it appears in various nonmonotonic reasoning formalisms, in particular, circumscription. It is argued that behind the complexity of circumscription lie the simple notions of random sampling and statistically founded beliefs. The latter is implemented through a device known as the abnormality predicate which appears in various guises in the nonmonotonic reasoning literature. Another view of this study is that randomness provides a universal conjecture for nonmonotonic theories. Default theories can be interpreted as jumping to the conclusion that an entity is a random member of a certain class.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125983587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130700
T. Hanyu, T. Higuchi
A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.<>
{"title":"A floating-gate-MOS-based multiple-valued associative memory","authors":"T. Hanyu, T. Higuchi","doi":"10.1109/ISMVL.1991.130700","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130700","url":null,"abstract":"A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"40 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130729
K. Current, M. E. Hurlston
A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2- mu m polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using logical current increments of only 10 mu A, the bidirectional current-mode MVL latch's setup and hold time has been determined to total approximately 44 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 50 ns at these low current levels.<>
{"title":"A bi-directional current-mode CMOS multiple valued logic memory circuit","authors":"K. Current, M. E. Hurlston","doi":"10.1109/ISMVL.1991.130729","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130729","url":null,"abstract":"A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2- mu m polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using logical current increments of only 10 mu A, the bidirectional current-mode MVL latch's setup and hold time has been determined to total approximately 44 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 50 ns at these low current levels.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-23DOI: 10.1109/ISMVL.1991.130738
G. Epstein, H. Rasiowa
For pt.I see Proc. 20/sup th/ International Symposium on Multiple- Valued Logic ISMVL 1990 p42-47. The paper is a continuation of the author's previous work that presents a stronger version of post algebras of order omega + omega whose chain of constants is isomorphic with (0>
{"title":"Theory and uses of Post algebras of order omega + omega *. II","authors":"G. Epstein, H. Rasiowa","doi":"10.1109/ISMVL.1991.130738","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130738","url":null,"abstract":"For pt.I see Proc. 20/sup th/ International Symposium on Multiple- Valued Logic ISMVL 1990 p42-47. The paper is a continuation of the author's previous work that presents a stronger version of post algebras of order omega + omega whose chain of constants is isomorphic with (0<or=1<or=2<or=. . .<or=-3<or=-2<or=-1). The algebras are a generalization of Post algebras of finite order, and preserve more of their properties than any other generalizations of infinite orders.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-29DOI: 10.1109/ISMVL.1991.130696
A. S. Wojcik
The uses of automated reasoning in the process of the design and analysis of digital systems are explored. A discussion of reasoning and automated reasoning is presented. Several examples of successful application of this technology are described, and current research is discussed. The author mentions AURA (automated reasoning assistant), ITP (interactive theorem prover) and flow nets.<>
{"title":"Reasoning about digital systems","authors":"A. S. Wojcik","doi":"10.1109/ISMVL.1991.130696","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130696","url":null,"abstract":"The uses of automated reasoning in the process of the design and analysis of digital systems are explored. A discussion of reasoning and automated reasoning is presented. Several examples of successful application of this technology are described, and current research is discussed. The author mentions AURA (automated reasoning assistant), ITP (interactive theorem prover) and flow nets.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129120767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISMVL.1991.130713
Y. Okura, R. Shimada, T. Hasegawa
A theoretical approach to quarternary cyclic AN codes for burst error correction is provided. After describing quarternary cyclic AN codes and arithmetic bursts, the authors discuss the arithmetic burst correcting ability of codes generated by A=(4/sup c/+or-1)A/sub 2/ and show a decoding method for such codes.<>
{"title":"Quarternary cyclic AN codes for burst error correction","authors":"Y. Okura, R. Shimada, T. Hasegawa","doi":"10.1109/ISMVL.1991.130713","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130713","url":null,"abstract":"A theoretical approach to quarternary cyclic AN codes for burst error correction is provided. After describing quarternary cyclic AN codes and arithmetic bursts, the authors discuss the arithmetic burst correcting ability of codes generated by A=(4/sup c/+or-1)A/sub 2/ and show a decoding method for such codes.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115592199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISMVL.1991.130736
R. Hahnle
A framework for axiomatizing arbitrary finitely valued logics with minimal overhead compared to the classical case is presented. The main idea is to work with tableaux using generalized signs, which makes it possible to express complex assertions regarding the possible truth values of a formula. The class of regular logical connectives which, together with a suitable restriction on queries (i.e. allowed signs) to the system, allow a uniform notation style representation of multiple-valued propositional and first-order logics is introduced. It has been demonstrated that various systems differing in their allowed classes of connectives and complexity, of rules may be formulated. This allows the use of tools and methods that are close to the ones used in classical logic, both on the theoretical (uniform notation in definitions and proofs) and practical (use of classical theorem provers with few modifications) sides.<>
{"title":"Uniform notation of tableau rules for multiple-valued logics","authors":"R. Hahnle","doi":"10.1109/ISMVL.1991.130736","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130736","url":null,"abstract":"A framework for axiomatizing arbitrary finitely valued logics with minimal overhead compared to the classical case is presented. The main idea is to work with tableaux using generalized signs, which makes it possible to express complex assertions regarding the possible truth values of a formula. The class of regular logical connectives which, together with a suitable restriction on queries (i.e. allowed signs) to the system, allow a uniform notation style representation of multiple-valued propositional and first-order logics is introduced. It has been demonstrated that various systems differing in their allowed classes of connectives and complexity, of rules may be formulated. This allows the use of tools and methods that are close to the ones used in classical logic, both on the theoretical (uniform notation in definitions and proofs) and practical (use of classical theorem provers with few modifications) sides.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115733913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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