Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130723
C. Reischer, D. Simovici
Biological computing based on the interactions between engines and substrate is addressed. An upper bound is given on the complexity of the bio-circuits that realize set-valued functions. This bound is based on an equivalence attached to a set-valued function such that the classes of the quotient set of the definition domain with respect to such an equivalence coincide with the maximal sets on which the function can be evaluated by computing a value of a Boolean function.<>
{"title":"On the implementation of set-valued non-Boolean switching functions","authors":"C. Reischer, D. Simovici","doi":"10.1109/ISMVL.1991.130723","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130723","url":null,"abstract":"Biological computing based on the interactions between engines and substrate is addressed. An upper bound is given on the complexity of the bio-circuits that realize set-valued functions. This bound is based on an equivalence attached to a set-valued function such that the classes of the quotient set of the definition domain with respect to such an equivalence coincide with the maximal sets on which the function can be evaluated by computing a value of a Boolean function.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114200992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130755
T. Chiueh
An architecture for implementing fuzzy-logic inference, together with the tools to optimally synthesize fuzzy logic circuits under this architecture, is proposed. The algorithms for finding the parameters for this architecture are presented. The author discusses how, computer-aided-design tools can be built to help fuzzy logic designers to explore the design space. In particular, the design process is divided into two phases, tuning the membership functions and synthesizing hardware implementations. The former is application-dependent, and previously no well-established automatic methods had been developed. A flexible, interactive design environment that allows designers to easily modify the plant model, the inference mechanism, and the membership functions, and quickly find out what the result is will be highly desirable.<>
{"title":"Optimization of fuzzy logic implementation","authors":"T. Chiueh","doi":"10.1109/ISMVL.1991.130755","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130755","url":null,"abstract":"An architecture for implementing fuzzy-logic inference, together with the tools to optimally synthesize fuzzy logic circuits under this architecture, is proposed. The algorithms for finding the parameters for this architecture are presented. The author discusses how, computer-aided-design tools can be built to help fuzzy logic designers to explore the design space. In particular, the design process is divided into two phases, tuning the membership functions and synthesizing hardware implementations. The former is application-dependent, and previously no well-established automatic methods had been developed. A flexible, interactive design environment that allows designers to easily modify the plant model, the inference mechanism, and the membership functions, and quickly find out what the result is will be highly desirable.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130494660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130752
S. Kawahito, K. Mizuno, Tasuro Nakamura
High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation.<>
{"title":"Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations","authors":"S. Kawahito, K. Mizuno, Tasuro Nakamura","doi":"10.1109/ISMVL.1991.130752","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130752","url":null,"abstract":"High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130724
T. Aoki, M. Kameyama, T. Higuchi
A systematic design method for an interconnection-free biomolecular computing system based on parallel distribution of logical information represented by varieties of molecules and parallel selection using specificity of enzymes is presented. A model of a biomolecular switching device is introduced as a universal building block, and the systematic synthesis of biodevice networks is discussed using a set-valued switching algebra. The main advantage is the maximum parallelism based on interconnection-free logic operations. It is possible to exploit the inherent parallelism of given algorithm through biodevice networks by converting the dataflow specification into parallel distribution and selection function.<>
{"title":"Design of interconnection-free biomolecular computing system","authors":"T. Aoki, M. Kameyama, T. Higuchi","doi":"10.1109/ISMVL.1991.130724","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130724","url":null,"abstract":"A systematic design method for an interconnection-free biomolecular computing system based on parallel distribution of logical information represented by varieties of molecules and parallel selection using specificity of enzymes is presented. A model of a biomolecular switching device is introduced as a universal building block, and the systematic synthesis of biodevice networks is discussed using a set-valued switching algebra. The main advantage is the maximum parallelism based on interconnection-free logic operations. It is possible to exploit the inherent parallelism of given algorithm through biodevice networks by converting the dataflow specification into parallel distribution and selection function.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132548221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130744
P. Tirumalai, Varadarajan G. Vadakkencherry
Two versions of a minimization algorithm for multiple-valued programmable logic arrays for shared and distributed memory multiprocessor systems are presented. Both algorithms exploit the considerable parallelism available in the minimization problem. Discussed are communication, synchronization, and load balancing issues under the two machine models. Limited access and the cost of the required computation prevented running of the two parallel algorithms on the actual machines; however, it was possible to run parallel algorithms for a different, but very similar, problem that required less computation. These results indicate that excellent speedups, in some cases superlinear (i.e, more than the number of processors), can be obtained from parallel implementations of this logic minimization algorithm.<>
{"title":"Parallel algorithms for minimizing multiple-valued programmable logic arrays","authors":"P. Tirumalai, Varadarajan G. Vadakkencherry","doi":"10.1109/ISMVL.1991.130744","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130744","url":null,"abstract":"Two versions of a minimization algorithm for multiple-valued programmable logic arrays for shared and distributed memory multiprocessor systems are presented. Both algorithms exploit the considerable parallelism available in the minimization problem. Discussed are communication, synchronization, and load balancing issues under the two machine models. Limited access and the cost of the required computation prevented running of the two parallel algorithms on the actual machines; however, it was possible to run parallel algorithms for a different, but very similar, problem that required less computation. These results indicate that excellent speedups, in some cases superlinear (i.e, more than the number of processors), can be obtained from parallel implementations of this logic minimization algorithm.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124695283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130701
Chia-Lun J. Hu
An M-ary digital multiplier using artificial multi-zero neural networks and elementary analog arithmetic units has been derived. This multiplier should be accurate because its main arithmetic process is digital, while the speed should be very high because it is a free-running, parallel, and M-ary operation. The multi-zero neural network is a feedback artificial neural system consisting of N neurons. Each neuron is a nonlinear amplifier with input-output response function equal to a polynomial function containing 2M+1 real zeros. A unique property possessed by this nonlinear feedback system is that if the connection matrix is programmed correctly, any N-bit analog input vector will always be converged to an N-bit M-valued digital vector at the output. This output will be locked-in in place (or it can be memorized) even when the input is removed.<>
{"title":"Application of multi-zero artificial neural network to the design of an m-valued digital multiplier","authors":"Chia-Lun J. Hu","doi":"10.1109/ISMVL.1991.130701","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130701","url":null,"abstract":"An M-ary digital multiplier using artificial multi-zero neural networks and elementary analog arithmetic units has been derived. This multiplier should be accurate because its main arithmetic process is digital, while the speed should be very high because it is a free-running, parallel, and M-ary operation. The multi-zero neural network is a feedback artificial neural system consisting of N neurons. Each neuron is a nonlinear amplifier with input-output response function equal to a polynomial function containing 2M+1 real zeros. A unique property possessed by this nonlinear feedback system is that if the connection matrix is programmed correctly, any N-bit analog input vector will always be converged to an N-bit M-valued digital vector at the output. This output will be locked-in in place (or it can be memorized) even when the input is removed.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130712
J. T. Butler, Kriss A. Schueller
A symmetric multiple-valued function realized as the disjunction of fundamental symmetric functions is addressed. A simpler disjunction can be formed when the latter functions combine in the same way that minterms combine to form simpler product terms for sum-of-products expressions. The authors solve the problem, posed by J.C. Muzio (1990), that sought the worst-case symmetric function in the sense that the maximum number of fundamental symmetric functions is needed. This problem is solved for general radix, and it is shown that the ratio of the maximum size of the disjunction to the total number of fundamental symmetric functions approaches one-half as the number of variables increases.<>
{"title":"Worst case number of terms in symmetric multiple-valued functions","authors":"J. T. Butler, Kriss A. Schueller","doi":"10.1109/ISMVL.1991.130712","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130712","url":null,"abstract":"A symmetric multiple-valued function realized as the disjunction of fundamental symmetric functions is addressed. A simpler disjunction can be formed when the latter functions combine in the same way that minterms combine to form simpler product terms for sum-of-products expressions. The authors solve the problem, posed by J.C. Muzio (1990), that sought the worst-case symmetric function in the sense that the maximum number of fundamental symmetric functions is needed. This problem is solved for general radix, and it is shown that the ratio of the maximum size of the disjunction to the total number of fundamental symmetric functions approaches one-half as the number of variables increases.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121863198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130746
E. Orlowska
A class of nonclassical relation algebras that correspond to Post logics is introduced and a method of algebraization of those logics is proposed. Relational semantics for Post logics leads to a Rasiowa-Sikorski style proof system for Post logics. A logic LPo intended to provide a formal tool to verify equations in Post relation algebras is defined. Two kinds of rules for the relational logic are defined: decomposition rules enabling the decomposition of relational formulas into some simpler formulas, depending on symbols of relational operations occurring in the formulas; and specific rules, which correspond to semantical postulates assumed in the models of the relational logic. The rules apply to finite sequences of formulas. As a result of application of a rule, a family of new sequences is obtained.<>
{"title":"Post relation algebras and their proof system","authors":"E. Orlowska","doi":"10.1109/ISMVL.1991.130746","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130746","url":null,"abstract":"A class of nonclassical relation algebras that correspond to Post logics is introduced and a method of algebraization of those logics is proposed. Relational semantics for Post logics leads to a Rasiowa-Sikorski style proof system for Post logics. A logic LPo intended to provide a formal tool to verify equations in Post relation algebras is defined. Two kinds of rules for the relational logic are defined: decomposition rules enabling the decomposition of relational formulas into some simpler formulas, depending on symbols of relational operations occurring in the formulas; and specific rules, which correspond to semantical postulates assumed in the models of the relational logic. The rules apply to finite sequences of formulas. As a result of application of a rule, a family of new sequences is obtained.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134633392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130749
C. Lucas, I. Türksen, Kenneth C. Smith
A systolic array implementation of a general-purpose inference processor is presented. The proposed processor can be used as a building block in the inference engine of an expert system or in a rule-based controller where computational speed is of importance. After a brief theoretical review of the approximate-reasoning, a VLSI implementation exploiting the parallelism in that routine is presented. The paper concludes with a discussion of programmability and other problems related to the practical application of the proposed processors.<>
{"title":"A general-purpose inference processor for real-time intelligent controllers using systolic arrays","authors":"C. Lucas, I. Türksen, Kenneth C. Smith","doi":"10.1109/ISMVL.1991.130749","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130749","url":null,"abstract":"A systolic array implementation of a general-purpose inference processor is presented. The proposed processor can be used as a building block in the inference engine of an expert system or in a rule-based controller where computational speed is of importance. After a brief theoretical review of the approximate-reasoning, a VLSI implementation exploiting the parallelism in that routine is presented. The paper concludes with a discussion of programmability and other problems related to the practical application of the proposed processors.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115497195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130704
R. Bignall
A set of operations which can be used to design n-valued switching functions is given. These give rise to a class of algebras which are left-handed skew lattices together with dual implication operation. Such algebras form a decidable discriminator variety, and hence possess a well-behaved structure theory and satisfy many identities. Algorithms for the design and optimization of switching functions are outlined.<>
{"title":"A non-commutative multiple-valued logic","authors":"R. Bignall","doi":"10.1109/ISMVL.1991.130704","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130704","url":null,"abstract":"A set of operations which can be used to design n-valued switching functions is given. These give rise to a class of algebras which are left-handed skew lattices together with dual implication operation. Such algebras form a decidable discriminator variety, and hence possess a well-behaved structure theory and satisfy many identities. Algorithms for the design and optimization of switching functions are outlined.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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