Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130730
B. Taheri
Several approaches to the hardware implementation of an electronic neuron are presented and compared. A hardware implementation of a neuron that uses a voltage-controlled input weights is introduced, and its simulated performance presented. This electronic neuron circuit is ideal for CMOS VLSI implementations of neural networks, because it merges, the advantages of analog and digital techniques. In addition, this pseudoanalog technique utilizes low power, high speed, and small area requirements for variety of applications.<>
{"title":"Proposed CMOS VLSI implementation of an electronic neuron using multivalued signal processing","authors":"B. Taheri","doi":"10.1109/ISMVL.1991.130730","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130730","url":null,"abstract":"Several approaches to the hardware implementation of an electronic neuron are presented and compared. A hardware implementation of a neuron that uses a voltage-controlled input weights is introduced, and its simulated performance presented. This electronic neuron circuit is ideal for CMOS VLSI implementations of neural networks, because it merges, the advantages of analog and digital techniques. In addition, this pseudoanalog technique utilizes low power, high speed, and small area requirements for variety of applications.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123134296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130709
A. Nakamura
A topological fuzzy algebra is defined as a special case of topological soft algebra. This algebra system is obtained from the S5-modal fuzzy logic, which had been previously proposed. The soundness and completeness of this axiomatic system are proved.<>
{"title":"Topological soft algebra for the S5-modal fuzzy logic","authors":"A. Nakamura","doi":"10.1109/ISMVL.1991.130709","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130709","url":null,"abstract":"A topological fuzzy algebra is defined as a special case of topological soft algebra. This algebra system is obtained from the S5-modal fuzzy logic, which had been previously proposed. The soundness and completeness of this axiomatic system are proved.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130735
Neil V. Murray, Erik Rosenthal
Path dissolution is an efficient generalization of the method of analytic tableaux. Both methods feature (in the propositional case) strong completeness, the lack of reliance upon conjunctive normal form (CNF), and the ability to produce a list of essential models (satisfying interpretations) of a formula. Dissolution can speed up every step in a tableau deduction in classical logic. The authors consider means for adapting both techniques to multiple-valued logics, and show that the speed-up theorem applies in this more general setting. These results are pertinent for modeling uncertainty and commonsense reasoning.<>
{"title":"Improving tableau deductions in multiple-valued logics","authors":"Neil V. Murray, Erik Rosenthal","doi":"10.1109/ISMVL.1991.130735","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130735","url":null,"abstract":"Path dissolution is an efficient generalization of the method of analytic tableaux. Both methods feature (in the propositional case) strong completeness, the lack of reliance upon conjunctive normal form (CNF), and the ability to produce a list of essential models (satisfying interpretations) of a formula. Dissolution can speed up every step in a tableau deduction in classical logic. The authors consider means for adapting both techniques to multiple-valued logics, and show that the speed-up theorem applies in this more general setting. These results are pertinent for modeling uncertainty and commonsense reasoning.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130753
T. Damarla, Fiaz Hossain
Canonical representation of multiple valued logic (MVL) functions in any polarity k, k in (0, 1,. . .,p/sup n/ -1), where p is the radix and n denotes the number of variables in a function, was previously presented. The coefficients in a canonical representation are called the spectral coefficients. It is shown that for some MVL functions realizing them as sum of products may not be economical, especially if very few minterms can be combined. Such functions can be efficiently realized as mod-p sum of products in a polarity which provides fewer coefficients. Realization of MVL functions as mod-p sum of products is done using a set of gates which are functionally complete. Implementation of these gates is shown both in I/sup 2/L and CCD technologies. The computation complexity for estimating all the coefficients in the canonical representation is presented.<>
多值逻辑(MVL)函数在任意极性k, k in(0,1，…，p/sup n/ -1)中的规范表示，其中p是基数，n表示函数中的变量数。正则表示中的系数称为谱系数。结果表明，对于某些MVL函数，将它们实现为乘积的和可能并不经济，特别是在极小项很少的情况下。这样的函数可以有效地实现为在提供较少系数的极性上的乘积的模-p和。利用一组功能完备的门，实现了MVL作为产品模和的功能。这些门的实现显示在I/sup 2/L和CCD技术。给出了在规范表示中估计所有系数的计算复杂度
{"title":"Spectral techniques for multiple valued logic circuits","authors":"T. Damarla, Fiaz Hossain","doi":"10.1109/ISMVL.1991.130753","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130753","url":null,"abstract":"Canonical representation of multiple valued logic (MVL) functions in any polarity k, k in (0, 1,. . .,p/sup n/ -1), where p is the radix and n denotes the number of variables in a function, was previously presented. The coefficients in a canonical representation are called the spectral coefficients. It is shown that for some MVL functions realizing them as sum of products may not be economical, especially if very few minterms can be combined. Such functions can be efficiently realized as mod-p sum of products in a polarity which provides fewer coefficients. Realization of MVL functions as mod-p sum of products is done using a set of gates which are functionally complete. Implementation of these gates is shown both in I/sup 2/L and CCD technologies. The computation complexity for estimating all the coefficients in the canonical representation is presented.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132181986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130703
Ingo Schäfer, M. Perkowski
The concept of canonical multiple-valued input generalized Reed-Muller forms (MIGRM), a direct extension of the well-known generalized Reed-Muller (GRM) forms for the logic with multiple-valued inputs, is introduced. Code normalization of single multiple-valued literals (MV-literal) to perform a final transformation is developed. The code normalization is used to make the transformation of the complete function independent on the polarity chosen. This simplifies and speeds up the main transformation step to the final restricted MIGRM form for the transformed single MV-literal. A computer program to realize the MIGRM transform for Boolean functions has been implemented. The direct circuit realization of MIGRMs as AND- EXOR programmable logic arrays with input decoders has excellent testability properties; they have applications to synthesis of other kinds of circuits with EXOR gates, such as the exclusive sums of products (ESOP), and they have image processing capabilities.<>
{"title":"Multiple-valued generalized Reed-Muller forms","authors":"Ingo Schäfer, M. Perkowski","doi":"10.1109/ISMVL.1991.130703","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130703","url":null,"abstract":"The concept of canonical multiple-valued input generalized Reed-Muller forms (MIGRM), a direct extension of the well-known generalized Reed-Muller (GRM) forms for the logic with multiple-valued inputs, is introduced. Code normalization of single multiple-valued literals (MV-literal) to perform a final transformation is developed. The code normalization is used to make the transformation of the complete function independent on the polarity chosen. This simplifies and speeds up the main transformation step to the final restricted MIGRM form for the transformed single MV-literal. A computer program to realize the MIGRM transform for Boolean functions has been implemented. The direct circuit realization of MIGRMs as AND- EXOR programmable logic arrays with input decoders has excellent testability properties; they have applications to synthesis of other kinds of circuits with EXOR gates, such as the exclusive sums of products (ESOP), and they have image processing capabilities.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130705
Y. Hata, Masaharu Yuhara, F. Miyawaki, K. Yamato
Multiple-valued Kleenean functions are represented by multiple-valued AND, OR, NOT, variables and constants. In their previous work (see proc. of 20th Int. Symp. Multiple Valued Logic, IEEE, p.410-17, 1990), the authors pointed out that both mapping from Kleenean functions to some (3,p)-functions and mapping from unate functions to some (2,p)-functions are bijections. In this paper, by using the above relations, 3-up-to-7 valued Kleenean functions of 3-or-less variables are enumerated on a computer. Their exact numbers are tabulated. The results show that as p becomes larger, the number of p-valued Kleenean functions increases stepwise, and that of p-valued unate functions increases smoothly.<>
{"title":"On the complexity of enumerations for multiple-valued Kleenean functions and unate functions","authors":"Y. Hata, Masaharu Yuhara, F. Miyawaki, K. Yamato","doi":"10.1109/ISMVL.1991.130705","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130705","url":null,"abstract":"Multiple-valued Kleenean functions are represented by multiple-valued AND, OR, NOT, variables and constants. In their previous work (see proc. of 20th Int. Symp. Multiple Valued Logic, IEEE, p.410-17, 1990), the authors pointed out that both mapping from Kleenean functions to some (3,p)-functions and mapping from unate functions to some (2,p)-functions are bijections. In this paper, by using the above relations, 3-up-to-7 valued Kleenean functions of 3-or-less variables are enumerated on a computer. Their exact numbers are tabulated. The results show that as p becomes larger, the number of p-valued Kleenean functions increases stepwise, and that of p-valued unate functions increases smoothly.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130728
Sen Jung Wei, H. Lin
Several designs for a high-speed static random access multivalued memory using the folding characteristics of multiple peak resonant tunneling diodes (RTDs) are presented. The different designs are described and studied by comparing their power consumption under different conditions of device parameters and the switching speed. It is shown that the proposed memory cell using a pair of multiple-peak RTDs yields the best result from the standpoint of size, power dissipation, and speed.<>
{"title":"Multiple peak resonant tunneling diode for multi-valued memory","authors":"Sen Jung Wei, H. Lin","doi":"10.1109/ISMVL.1991.130728","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130728","url":null,"abstract":"Several designs for a high-speed static random access multivalued memory using the folding characteristics of multiple peak resonant tunneling diodes (RTDs) are presented. The different designs are described and studied by comparing their power consumption under different conditions of device parameters and the switching speed. It is shown that the proposed memory cell using a pair of multiple-peak RTDs yields the best result from the standpoint of size, power dissipation, and speed.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132109553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130706
N. Takagi, M. Mukaidono
Kleene-Stone algebras have been proposed as an algebra with the properties of both Kleene algebra and Stone algebra. Therefore, they have connections with ambiguity and modality. A Kleene-Stone logic function is defined as a function F:
{"title":"Fundamental properties of Kleene-Stone logic functions","authors":"N. Takagi, M. Mukaidono","doi":"10.1109/ISMVL.1991.130706","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130706","url":null,"abstract":"Kleene-Stone algebras have been proposed as an algebra with the properties of both Kleene algebra and Stone algebra. Therefore, they have connections with ambiguity and modality. A Kleene-Stone logic function is defined as a function F:","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114664719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130748
D. Rine
This research extends techniques for mapping rule-based expert systems into VLSI hardware design notation and provides design procedures for performing the mapping from expert system' production rules to hardware specification rules. Results from this work enhance the applicability of the rule-based expert system approach to a larger class of real-time and control applications.<>
{"title":"An equational logic approach for mapping/multiple-valued rule-based expert systems into hardware specification rules","authors":"D. Rine","doi":"10.1109/ISMVL.1991.130748","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130748","url":null,"abstract":"This research extends techniques for mapping rule-based expert systems into VLSI hardware design notation and provides design procedures for performing the mapping from expert system' production rules to hardware specification rules. Results from this work enhance the applicability of the rule-based expert system approach to a larger class of real-time and control applications.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123833032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130699
T. Hanyu, Yasushi Kojima, T. Higuchi
A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS transistors whose threshold voltages are programmed by multiple ion implants. It is demonstrated that the chip area and power dissipation of 8-valued logic array can be reduced to 30% and 50%, respectively, compared with corresponding binary implementation.<>
{"title":"A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems","authors":"T. Hanyu, Yasushi Kojima, T. Higuchi","doi":"10.1109/ISMVL.1991.130699","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130699","url":null,"abstract":"A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS transistors whose threshold voltages are programmed by multiple ion implants. It is demonstrated that the chip area and power dissipation of 8-valued logic array can be reduced to 30% and 50%, respectively, compared with corresponding binary implementation.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131503976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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