Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130718
Young-hoon Chang, J. T. Butler
A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizations that are almost as good. A cost-table that results in better realizations than obtained with a previous cost-table is proposed.<>
{"title":"The design of current mode CMOS multiple-valued circuits","authors":"Young-hoon Chang, J. T. Butler","doi":"10.1109/ISMVL.1991.130718","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130718","url":null,"abstract":"A vertical partitioning algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique is proposed. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It partitions a given function according to the location of logic zeros. It is significantly faster than exhaustive search while providing realizations that are almost as good. A cost-table that results in better realizations than obtained with a previous cost-table is proposed.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130716
Hiroyuki Watanabe, J. Symon, W. Dettloff, K. E. Yount
The architecture and operational features of a VLSI fuzzy logic inference processor are described. Also described are the architecture and associated high-level software of two VMEbus-board systems based on the fuzzy chip. The VLSI implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. The CMOS chip consists of 688000 transistors, of which 476000 are used for RAM memory. In addition to operating in a robot, the single chip board is installed on a Sun-3 workstation for further research and software development.<>
{"title":"VLSI fuzzy chip and inference accelerator board systems","authors":"Hiroyuki Watanabe, J. Symon, W. Dettloff, K. E. Yount","doi":"10.1109/ISMVL.1991.130716","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130716","url":null,"abstract":"The architecture and operational features of a VLSI fuzzy logic inference processor are described. Also described are the architecture and associated high-level software of two VMEbus-board systems based on the fuzzy chip. The VLSI implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. The CMOS chip consists of 688000 transistors, of which 476000 are used for RAM memory. In addition to operating in a robot, the single chip board is installed on a Sun-3 workstation for further research and software development.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124317802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130743
G. Dueck, G. H. Rees
Some bounds on the maximum number of implicants needed in a minimal sum of products expression using window literals and the truncated sum, operation are investigated. Functions with one input variable require at most r implicants in their minimum sum of products expression, where r is the radix of the function. Two variable functions with radix less than eight are analyzed. No firm bounds could be established for two variable functions with radix greater than four.<>
{"title":"On the maximum number of implicants needed to cover a multiple-valued logic function using window literals","authors":"G. Dueck, G. H. Rees","doi":"10.1109/ISMVL.1991.130743","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130743","url":null,"abstract":"Some bounds on the maximum number of implicants needed in a minimal sum of products expression using window literals and the truncated sum, operation are investigated. Functions with one input variable require at most r implicants in their minimum sum of products expression, where r is the radix of the function. Two variable functions with radix less than eight are analyzed. No firm bounds could be established for two variable functions with radix greater than four.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130731
Xunwei Wu, Xiaowei Deng
According to the action principle of I/sup 2/L circuits, the theory of grounded current switches is proposed to describe the interaction between grounded transistors and current signals in I/sup 2/L circuits. In this theory, the switching state of transistor and the current signal are described separately by two different kinds of variables. Threshold comparison operations and grounding operations are introduced to connect these two kinds of variables. Based on discussions of the properties of operations and syntheses of functions, the design procedure is illustrated using the quaternary level restored complement gate and the quaternary quantizer as examples.<>
{"title":"Theory of grounded current switches and quaternary III circuits","authors":"Xunwei Wu, Xiaowei Deng","doi":"10.1109/ISMVL.1991.130731","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130731","url":null,"abstract":"According to the action principle of I/sup 2/L circuits, the theory of grounded current switches is proposed to describe the interaction between grounded transistors and current signals in I/sup 2/L circuits. In this theory, the switching state of transistor and the current signal are described separately by two different kinds of variables. Threshold comparison operations and grounding operations are introduced to connect these two kinds of variables. Based on discussions of the properties of operations and syntheses of functions, the design procedure is illustrated using the quaternary level restored complement gate and the quaternary quantizer as examples.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133713467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130758
Chyan Yang, Han-Chung Lu, David E. Gilbert
Due to the need for coexistence with binary logic, the implementation of multiple-valued logic must deal with the representations that are conceptually multiple-valued, but physically binary. Some theoretical insights about the VLSI implementation based on a programmable logic array (PLA) approach are presented. The study of these output functions reveals an interesting problem domain that parallels the number theory. It is found that the binary-related radices are not just efficient or direct-packing, but also lower in terms of silicon costs. Implementation of the individual modulo adders and multipliers that form the core for designing a residual number arithmetic unit is discussed. The costs involved in developing these subsystems can then be directly related to the design of the overall system. This tutorial demonstrates that the power-of-two advantage in the implementation costs may be technology-independent.<>
{"title":"An investigation into the implementation costs of residue and high radix arithmetic","authors":"Chyan Yang, Han-Chung Lu, David E. Gilbert","doi":"10.1109/ISMVL.1991.130758","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130758","url":null,"abstract":"Due to the need for coexistence with binary logic, the implementation of multiple-valued logic must deal with the representations that are conceptually multiple-valued, but physically binary. Some theoretical insights about the VLSI implementation based on a programmable logic array (PLA) approach are presented. The study of these output functions reveals an interesting problem domain that parallels the number theory. It is found that the binary-related radices are not just efficient or direct-packing, but also lower in terms of silicon costs. Implementation of the individual modulo adders and multipliers that form the core for designing a residual number arithmetic unit is discussed. The costs involved in developing these subsystems can then be directly related to the design of the overall system. This tutorial demonstrates that the power-of-two advantage in the implementation costs may be technology-independent.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131616312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130750
Y. Tsuchiya
Logic programming using the Horn clause in the field of artificial intelligence is considered. It has been previously reported that the solution of multivalued logic programming with many truth values is obtained by solving the multivalued logic formula expressed in the Postian algebra. In this paper, expanding the idea that unnecessary search can be avoided by using an indeterminate value, an algorithm that solves three-valued logic programming using four-valued logic is obtained. The relation between the Horn clause and Postian algebra is established.<>
{"title":"An algorithm for the solution of multi-valued logic programming","authors":"Y. Tsuchiya","doi":"10.1109/ISMVL.1991.130750","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130750","url":null,"abstract":"Logic programming using the Horn clause in the field of artificial intelligence is considered. It has been previously reported that the solution of multivalued logic programming with many truth values is obtained by solving the multivalued logic formula expressed in the Postian algebra. In this paper, expanding the idea that unnecessary search can be avoided by using an indeterminate value, an algorithm that solves three-valued logic programming using four-valued logic is obtained. The relation between the Horn clause and Postian algebra is established.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131863589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130719
O. Ishizuka, H. Takarabe, Z. Tang, H. Matsumoto
The basic properties of the MOS current-mode circuits are considered, and the network synthesis for realization of unary multivalued functions is discussed. The main concern is the minimization of hardware realization. Functional blocks to compose a current-mode circuit from the viewpoint of a design cost are considered. Some decomposition methods of unary functions are proposed and their circuit realizations with MOS pass transistor networks are presented.<>
{"title":"Synthesis of current-mode pass transistor networks","authors":"O. Ishizuka, H. Takarabe, Z. Tang, H. Matsumoto","doi":"10.1109/ISMVL.1991.130719","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130719","url":null,"abstract":"The basic properties of the MOS current-mode circuits are considered, and the network synthesis for realization of unary multivalued functions is discussed. The main concern is the minimization of hardware realization. Functional blocks to compose a current-mode circuit from the viewpoint of a design cost are considered. Some decomposition methods of unary functions are proposed and their circuit realizations with MOS pass transistor networks are presented.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130597394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130740
F. Börner, L. Haddad, R. Pöschel
Clones of partial operations playing important role in the theory of partial algebras and in computer science are considered. It is shown that the atoms of the lattice Lp/sub A/ of all partial clones are either the atoms of Lo/sub A/ or are generated by partial projections, defined on a totally reflexive and totally symmetric domain.<>
{"title":"A note on minimal partial clones","authors":"F. Börner, L. Haddad, R. Pöschel","doi":"10.1109/ISMVL.1991.130740","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130740","url":null,"abstract":"Clones of partial operations playing important role in the theory of partial algebras and in computer science are considered. It is shown that the atoms of the lattice Lp/sub A/ of all partial clones are either the atoms of Lo/sub A/ or are generated by partial projections, defined on a totally reflexive and totally symmetric domain.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130739
Wen-Ran Zhang
NPN (negative-positive-neutral) calculi, a family of three mathematical structures are introduced for qualitative reasoning. NPN crisp logic extends the usual 4-valued model (+, -, 0, ?) to a 6-valued model (1, 0, +1, (-1, 0), (0, +1), (-1, +1)) and adds one more level of specification to the usual model. NPN fuzzy logic extends the NPN model to the space ( For all (x,y) mod x, y epsilon (-1, 1) and x>
NPN(负-正-中性)微积分，一个由三种数学结构组成的家族被引入定性推理。NPN清晰逻辑将通常的4值模型(+，-，0，?)扩展为6值模型(1,0，+1，(-1,0)，(0，+1)，(-1，+1))，并在通常的模型上增加了一个规格级别。NPN模糊逻辑将NPN模型扩展到空间(For all (x,y) mod x,y epsilon(- 1,1)和x>
{"title":"NPN calculi: a family of three strict Q-algebras","authors":"Wen-Ran Zhang","doi":"10.1109/ISMVL.1991.130739","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130739","url":null,"abstract":"NPN (negative-positive-neutral) calculi, a family of three mathematical structures are introduced for qualitative reasoning. NPN crisp logic extends the usual 4-valued model (+, -, 0, ?) to a 6-valued model (1, 0, +1, (-1, 0), (0, +1), (-1, +1)) and adds one more level of specification to the usual model. NPN fuzzy logic extends the NPN model to the space ( For all (x,y) mod x, y epsilon (-1, 1) and x<or=y) and adds infinite levels of specifications to the usual model. NPN algebra generalizes the NPN model to include algebraic operations on NPN variables defined in the space of (- infinity , infinity ). Based on the three models, NPN relations and NPN matrices are proposed. It is proved that the three models provide three strict qualitative algebras after the usual 4-valued model. Properties of different models are discussed. Potential applications of NPN calculi in qualitative reasoning are outlined.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130726
C. Moraga
Some of the significant achievements of the last ten years in the area of spectral techniques are summarized. The name spectral techniques denotes developments in abstract harmonic analysis oriented to possible applications in switching theory and logic design, fault detection, coding theory, and pattern analysis. A review of pattern analysis, with emphasis on the study of self-similarity of patterns, is presented.<>
{"title":"A decade of spectral techniques","authors":"C. Moraga","doi":"10.1109/ISMVL.1991.130726","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130726","url":null,"abstract":"Some of the significant achievements of the last ten years in the area of spectral techniques are summarized. The name spectral techniques denotes developments in abstract harmonic analysis oriented to possible applications in switching theory and logic design, fault detection, coding theory, and pattern analysis. A review of pattern analysis, with emphasis on the study of self-similarity of patterns, is presented.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121021917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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