Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767207
P. Komarov, P. Raad, M. Burzo, Taehun Lee, Moon J. Kim
The primary purpose of this work was to investigate the relative heat removal effectiveness of various thermal interface and buried oxide materials as they would be used in actual conditions. The thermoreflectance thermography approach was used to measure, non-invasively and with submicron spatial resolution, the surface temperature fields of two types of thermal test devices: (i) Delphi thermal test dies that have been attached to the heat sink with different thermal interface materials and (ii) microresistor test devices built on various buried oxide structures. The temperature maps were used to identify the most thermally efficient material in each of the two types investigated.
{"title":"Thermal mapping of Delphi thermal test dies","authors":"P. Komarov, P. Raad, M. Burzo, Taehun Lee, Moon J. Kim","doi":"10.1109/STHERM.2011.5767207","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767207","url":null,"abstract":"The primary purpose of this work was to investigate the relative heat removal effectiveness of various thermal interface and buried oxide materials as they would be used in actual conditions. The thermoreflectance thermography approach was used to measure, non-invasively and with submicron spatial resolution, the surface temperature fields of two types of thermal test devices: (i) Delphi thermal test dies that have been attached to the heat sink with different thermal interface materials and (ii) microresistor test devices built on various buried oxide structures. The temperature maps were used to identify the most thermally efficient material in each of the two types investigated.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123978448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767219
V. Datsyuk, I. Firkowska, K. Gharagozloo-Hubmann, M. Lisunova, Anna-Maria Vogt, André Boden, M. Kasimir, S. Trotsenko, G. Czempiel, S. Reich
We developed innovative solutions for reaching high performance in carbon-nanotube-filled engineering materials. Electrospinning was applied to improve the thermal conductivity in polymer composites via the alignment of nanotubes in a polymer matrix. Alignment was achieved by flow-confinement and charge-induced alignment during electrospinning. Additionally, the use of liquid crystal polymer as a matrix increased the degree of alignment leading to the remarkable increase of the thermal conductivity in composites by a factor 33. We developed the reduction from method to produce metal-matrix composites filled with carbon nanotubes. We were able to engineer the coefficient of thermal expansion (CTE) of the copper composite, for example 3 wt% of carbon nanotubes added to copper yielded CTEs comparable with ceramics and semiconductors. In situ thermal polymerization of natural oils (plant and fish) was applied to produce nanotubes-based thermal greases. This method creates novel, environmentally friendly thermal grease with excellent thermal conductivity (increased by a factor 12), that is easy to handle compound and to remove. Such thermal greases can be applied to surfaces by various methods, including screen printing, and demonstrate good thermal stability, reduced thermal expansion, and no pumping-out effect.
{"title":"Carbon nanotubes based engineering materials for thermal management applications","authors":"V. Datsyuk, I. Firkowska, K. Gharagozloo-Hubmann, M. Lisunova, Anna-Maria Vogt, André Boden, M. Kasimir, S. Trotsenko, G. Czempiel, S. Reich","doi":"10.1109/STHERM.2011.5767219","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767219","url":null,"abstract":"We developed innovative solutions for reaching high performance in carbon-nanotube-filled engineering materials. Electrospinning was applied to improve the thermal conductivity in polymer composites via the alignment of nanotubes in a polymer matrix. Alignment was achieved by flow-confinement and charge-induced alignment during electrospinning. Additionally, the use of liquid crystal polymer as a matrix increased the degree of alignment leading to the remarkable increase of the thermal conductivity in composites by a factor 33. We developed the reduction from method to produce metal-matrix composites filled with carbon nanotubes. We were able to engineer the coefficient of thermal expansion (CTE) of the copper composite, for example 3 wt% of carbon nanotubes added to copper yielded CTEs comparable with ceramics and semiconductors. In situ thermal polymerization of natural oils (plant and fish) was applied to produce nanotubes-based thermal greases. This method creates novel, environmentally friendly thermal grease with excellent thermal conductivity (increased by a factor 12), that is easy to handle compound and to remove. Such thermal greases can be applied to surfaces by various methods, including screen printing, and demonstrate good thermal stability, reduced thermal expansion, and no pumping-out effect.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767198
C. Biber, C. Coleman
When considering packaging choices for an ASIC, the target system and its lifetime should be considered. In this study, the overall system thermal conditions are included: heat sink available space, bypass, and air speed as well as chip power map, lid presence and material, and thermal interface materials at die and heat sink. The chip is an ASIC in a ball grid array (BGA) package on a multilayer board. Using numerical modeling to derive a linear response model and then analyzing a large number of samples with the Monte Carlo method, the study concludes that an AlSiC lid is beneficial versus a lidless package when used with a standard forged aluminum heat sink; the mean expected life also increases by 43% with a lid versus no lid. A lid also decreases maximum temperature sensitivity to the heat sink interface material resistivity by an order of magnitude.
{"title":"ASIC package lid effects on temperature and lifetime","authors":"C. Biber, C. Coleman","doi":"10.1109/STHERM.2011.5767198","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767198","url":null,"abstract":"When considering packaging choices for an ASIC, the target system and its lifetime should be considered. In this study, the overall system thermal conditions are included: heat sink available space, bypass, and air speed as well as chip power map, lid presence and material, and thermal interface materials at die and heat sink. The chip is an ASIC in a ball grid array (BGA) package on a multilayer board. Using numerical modeling to derive a linear response model and then analyzing a large number of samples with the Monte Carlo method, the study concludes that an AlSiC lid is beneficial versus a lidless package when used with a standard forged aluminum heat sink; the mean expected life also increases by 43% with a lid versus no lid. A lid also decreases maximum temperature sensitivity to the heat sink interface material resistivity by an order of magnitude.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115210444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767184
Pramod Kumar, V. Sundaralingam, Y. Joshi
This paper presents experimental studies on server level rack air distribution for a preset perforated tile air flow rate. A series of experiments are performed using a 22.8 kW server simulator placed in a raised floor data center facility. The rack air flow rate is varied by adjusting the fan speed of the server simulator. Particle Image Velocimetry (PIV) technique is used to capture the air flow pattern at various locations in the cold aisle at the inlet of the server simulator. The PIV images are recorded at various locations and later combined to get the complete air distribution map across the rack inlet. Various cases of rack air flow distributions are investigated by varying the server simulator fan speed settings for given perforated tile air flow rate. A significant change in the air distribution pattern is observed for various cases investigated.
{"title":"Effect of server load variation on rack air flow distribution in a raised floor data center","authors":"Pramod Kumar, V. Sundaralingam, Y. Joshi","doi":"10.1109/STHERM.2011.5767184","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767184","url":null,"abstract":"This paper presents experimental studies on server level rack air distribution for a preset perforated tile air flow rate. A series of experiments are performed using a 22.8 kW server simulator placed in a raised floor data center facility. The rack air flow rate is varied by adjusting the fan speed of the server simulator. Particle Image Velocimetry (PIV) technique is used to capture the air flow pattern at various locations in the cold aisle at the inlet of the server simulator. The PIV images are recorded at various locations and later combined to get the complete air distribution map across the rack inlet. Various cases of rack air flow distributions are investigated by varying the server simulator fan speed settings for given perforated tile air flow rate. A significant change in the air distribution pattern is observed for various cases investigated.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114863875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767181
R. Bornoff, B. Blackmore, J. Parry
Calculation and display of a thermal bottleneck scalar field as an integrated part of a CFD simulation enables a practitioner to interact with and understand the physical mechanisms by which heat is removed from an electronics system. By applying the characteristics of this thermal bottleneck scalar to heat sink design aspects, one can identify near optimal solutions with a minimal number of simulations. This work will detail the principles of using thermal bottleneck information to optimize fin thickness distribution and copper slug design and compare the results to that obtained by more traditional Design of Experiments and numerical optimization techniques.
{"title":"Heat sink design optimization using the thermal bottleneck concept","authors":"R. Bornoff, B. Blackmore, J. Parry","doi":"10.1109/STHERM.2011.5767181","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767181","url":null,"abstract":"Calculation and display of a thermal bottleneck scalar field as an integrated part of a CFD simulation enables a practitioner to interact with and understand the physical mechanisms by which heat is removed from an electronics system. By applying the characteristics of this thermal bottleneck scalar to heat sink design aspects, one can identify near optimal solutions with a minimal number of simulations. This work will detail the principles of using thermal bottleneck information to optimize fin thickness distribution and copper slug design and compare the results to that obtained by more traditional Design of Experiments and numerical optimization techniques.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115285828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767206
Chang Shyy Woei, C. K. Feng, Wang Huiru, H. Chin, Kao Juei Ken
This paper presents the results of a set of numerical and experimental studies for flow and heat transfer in a spiral channel roughened by skew ribs over two opposite endwalls. The experimental Nusselt number (Nu) distributions, pressure drop coefficients (f) and thermal performance factors (η) for the spiral ribbed channel are examined along with the flow structures determined from the CFD analysis. The comparisons of Heat Transfer Enhancement (HTE) ratios measured from the ribbed spiral channel with other passive types of HTE devices confirm the favorable HTE performances for the spiral channel with the in-line skew ribs. A subsequent design and product development for the liquid cooling unit using the ribbed spiral channel is described with the pressure drops and thermal resistances presented. This study confirms the availability of the enhanced liquid cooling performance using the spiral ribbed channel for the electronic chipset(s) with higher power densities.
{"title":"Design and development of compact spiral ribbed cooling unit for electronic chipsets with high power densities","authors":"Chang Shyy Woei, C. K. Feng, Wang Huiru, H. Chin, Kao Juei Ken","doi":"10.1109/STHERM.2011.5767206","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767206","url":null,"abstract":"This paper presents the results of a set of numerical and experimental studies for flow and heat transfer in a spiral channel roughened by skew ribs over two opposite endwalls. The experimental Nusselt number (Nu) distributions, pressure drop coefficients (f) and thermal performance factors (η) for the spiral ribbed channel are examined along with the flow structures determined from the CFD analysis. The comparisons of Heat Transfer Enhancement (HTE) ratios measured from the ribbed spiral channel with other passive types of HTE devices confirm the favorable HTE performances for the spiral channel with the in-line skew ribs. A subsequent design and product development for the liquid cooling unit using the ribbed spiral channel is described with the pressure drops and thermal resistances presented. This study confirms the availability of the enhanced liquid cooling performance using the spiral ribbed channel for the electronic chipset(s) with higher power densities.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116238388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767197
J. Galloway, S. Kanuparthi, Q. Wan
Thermal resistance data were collected using two different style flip chip ball grid array (FCBGA) packages; one with an exposed molded die and a second with a lid. Eleven different heat sink designs and two different thermal interface materials (TIM) were tested to quantify the thermal interaction between heat sink size, base material and TIM resistance as a function of package style. Package style and TIM material did not appreciably change the total thermal resistance (less than 10%) for small heat sinks 50mm × 50mm smaller. The exposed molded die package thermal resistance was 14% smaller than the lidded package when tested with a heat pipe heat sink. An understanding of the long term performance impact of TIM II degradation was investigated using conduction based models. Lidded style packages may increase safety margin when TIM II materials experience pump-out, dry-out or voiding.
{"title":"Thermal performance of FCMBGA: Exposed molded die compared to lidded package","authors":"J. Galloway, S. Kanuparthi, Q. Wan","doi":"10.1109/STHERM.2011.5767197","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767197","url":null,"abstract":"Thermal resistance data were collected using two different style flip chip ball grid array (FCBGA) packages; one with an exposed molded die and a second with a lid. Eleven different heat sink designs and two different thermal interface materials (TIM) were tested to quantify the thermal interaction between heat sink size, base material and TIM resistance as a function of package style. Package style and TIM material did not appreciably change the total thermal resistance (less than 10%) for small heat sinks 50mm × 50mm smaller. The exposed molded die package thermal resistance was 14% smaller than the lidded package when tested with a heat pipe heat sink. An understanding of the long term performance impact of TIM II degradation was investigated using conduction based models. Lidded style packages may increase safety margin when TIM II materials experience pump-out, dry-out or voiding.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767220
M. Nguyen, J. Brandi
The cure reactions for conventional flexible epoxy resins are generally slow and have out-gassing and branching site reactions. As a result, these resin types have significant hardening after long-term, high-temperature exposure which makes them unsuitable for thermal interface applications. To address these challenges, a new epoxy resin system has been developed for thermal interface materials (TIMs). The main characteristics of the new resin are: — High thermal stability — No branching — Hydrophobic — Stable at room temperature Development and characterization of a new type of TIM will be discussed.
{"title":"Development of an advanced thermal interface material for high power devices","authors":"M. Nguyen, J. Brandi","doi":"10.1109/STHERM.2011.5767220","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767220","url":null,"abstract":"The cure reactions for conventional flexible epoxy resins are generally slow and have out-gassing and branching site reactions. As a result, these resin types have significant hardening after long-term, high-temperature exposure which makes them unsuitable for thermal interface applications. To address these challenges, a new epoxy resin system has been developed for thermal interface materials (TIMs). The main characteristics of the new resin are: — High thermal stability — No branching — Hydrophobic — Stable at room temperature Development and characterization of a new type of TIM will be discussed.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767187
C. Green, A. Fedorov, Y. Joshi
While 3D stacked multi-processor technology offers the potential for significant computing advantages, these architectures also face with the significant challenge of small, localized hotspots with very large power dissipation due to the placement of asymmetric cores, heterogeneous devices and performance driven layouts. In this paper, a new thermal management solution is proposed that seeks to maximize the performance of microprocessors with dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profiles resulting from the dynamic power maps, phase change materials (PCMs) with an embedded heat spreader network are strategically positioned near localized hotspots, resulting in a large increase in the local thermal capacitance in these problematic areas. We show that this results in an up-to-twenty-fold increase in the time that a thermally constrained core can operate before a power gating or core migration event is required.
{"title":"Thermal capacitance matching in 3D many-core architectures","authors":"C. Green, A. Fedorov, Y. Joshi","doi":"10.1109/STHERM.2011.5767187","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767187","url":null,"abstract":"While 3D stacked multi-processor technology offers the potential for significant computing advantages, these architectures also face with the significant challenge of small, localized hotspots with very large power dissipation due to the placement of asymmetric cores, heterogeneous devices and performance driven layouts. In this paper, a new thermal management solution is proposed that seeks to maximize the performance of microprocessors with dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profiles resulting from the dynamic power maps, phase change materials (PCMs) with an embedded heat spreader network are strategically positioned near localized hotspots, resulting in a large increase in the local thermal capacitance in these problematic areas. We show that this results in an up-to-twenty-fold increase in the time that a thermally constrained core can operate before a power gating or core migration event is required.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121378016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767224
P. Tuma
There is renewed interest in passive 2-phase immersion for cooling power electronics and high performance computers. This can be attributed to recent research showing its performance potential compared with more complex and costly techniques, to innovations that simplify its application and to a general trend toward higher power densities. Though the thermal performance capabilities of passive 2-phase immersion cooling are well documented, the technique is not widely practiced and system designers will find little published information concerning subtler and very critical aspects of system design. There is no manual, for example, concerning practical details like material compatibility, electrical signal integrity (SI), fluid decomposition, management of moisture and light gases, and so on. This paper presents a useful material compatibility test method and explains the mechanisms of distillation and extraction that are intrinsic to a refluxing 2-phase system and by which wetted materials interact with the fluid and each other. It discusses sources, implications and techniques for removal of organic contaminants, water, non-condensable air and fluid thermal decomposition products. Data are presented from sub-20GHz SI experiments conducted with backplane connectors and microstrip transmission lines submerged in two classes of environmentally sustainable working fluids. It is hoped that this overview will demystify these subjects for designers unfamiliar with passive 2-phase immersion cooling and encourage more widespread adoption of this elegant and proven technology.
{"title":"Design considerations relating to non-thermal aspects of passive 2-phase immersion cooling","authors":"P. Tuma","doi":"10.1109/STHERM.2011.5767224","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767224","url":null,"abstract":"There is renewed interest in passive 2-phase immersion for cooling power electronics and high performance computers. This can be attributed to recent research showing its performance potential compared with more complex and costly techniques, to innovations that simplify its application and to a general trend toward higher power densities. Though the thermal performance capabilities of passive 2-phase immersion cooling are well documented, the technique is not widely practiced and system designers will find little published information concerning subtler and very critical aspects of system design. There is no manual, for example, concerning practical details like material compatibility, electrical signal integrity (SI), fluid decomposition, management of moisture and light gases, and so on. This paper presents a useful material compatibility test method and explains the mechanisms of distillation and extraction that are intrinsic to a refluxing 2-phase system and by which wetted materials interact with the fluid and each other. It discusses sources, implications and techniques for removal of organic contaminants, water, non-condensable air and fluid thermal decomposition products. Data are presented from sub-20GHz SI experiments conducted with backplane connectors and microstrip transmission lines submerged in two classes of environmentally sustainable working fluids. It is hoped that this overview will demystify these subjects for designers unfamiliar with passive 2-phase immersion cooling and encourage more widespread adoption of this elegant and proven technology.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121074313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：