Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767200
M. Janicki, Z. Kulesza, T. Torzewicz, A. Napieralski
This paper presents the design and the practical realization of a measurement stand dedicated to thermal characterization of electronic packages. The standard Dual Cold Plate (DCP) solution is enhanced with the Peltier Thermo-Electric Modules (TEMs) and a tensometer bridge. The TEMs are automatically controlled by a special circuit so as to provide either constant case temperature or constant thermal resistance to ambient. The tensometers are used to assure parallel alignment of the layers and to adjust contact thermal resistance between them. The realized stand is thoroughly tested and verified during the measurements of a power diode.
{"title":"Automated stand for thermal characterization of electronic packages","authors":"M. Janicki, Z. Kulesza, T. Torzewicz, A. Napieralski","doi":"10.1109/STHERM.2011.5767200","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767200","url":null,"abstract":"This paper presents the design and the practical realization of a measurement stand dedicated to thermal characterization of electronic packages. The standard Dual Cold Plate (DCP) solution is enhanced with the Peltier Thermo-Electric Modules (TEMs) and a tensometer bridge. The TEMs are automatically controlled by a special circuit so as to provide either constant case temperature or constant thermal resistance to ambient. The tensometers are used to assure parallel alignment of the layers and to adjust contact thermal resistance between them. The realized stand is thoroughly tested and verified during the measurements of a power diode.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132315387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767174
Xudong Tang, R. Bonner, T. Desai, A. Fan
A novel thermal management technology was explored to lower the peak temperature associated with high power GaN transistors in pulse application. The technology involves the use of an embedded microscale PCM heat storage device within the chip (near the active channels of the GaN device), which effectively increases the heat capacity of the material by taking advantage of the latent heat of the PCM. In this study, 2-D transient thermal models were developed to characterize the thermal behavior of GaN transistors with micro-scale PCM heat storage device. The model is capable of computing the spatial-temporal temperature distribution of the GaN transistor as it is rapidly pulsed and captures the formation and evolution of hot spots that form within the device. The model also captures the PCM melting behavior and latent heat absorption during the transient. The use of a PCM can effectively control the hot spot temperature by absorbing a significant portion of the transient heat input. As shown in this modeling study, the use of PCM heat storage in GaN transistors reduces the GaN hot spot temperature for a given heat input. Alternatively, the maximum allowable GaN heat input can be increased with the use of PCM. At a given heat input flux of 5×105 W/cm2, for example, the use of PCM heat storage can lower the peak temperature by 21∼22°C, relative to transistors without PCM (baseline), regardless of the duty cycle ratio. In addition, a transistor with PCM heat storage can accommodate much higher joule heat generation without exceeding the maximum allowable temperature limit, 180°C. In this study, the modeling results show that by integrating a PCM that has a 140°C melting point in a 5μm×6μm groove configuration, the critical heat flux can be increased from 13.34×105 W/cm2 (baseline) to 16.8×105 W/cm2 (with PCM), a 26% improvement. Key PCM design parameters were identified in this modeling study: (1) PCM amount; (2) PCM melting point; and (3) PCM groove structure. Their coupling and the impact on design optimization require further investigation.
{"title":"A 2-D numerical study of microscale phase change material thermal storage for GaN transistor thermal management","authors":"Xudong Tang, R. Bonner, T. Desai, A. Fan","doi":"10.1109/STHERM.2011.5767174","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767174","url":null,"abstract":"A novel thermal management technology was explored to lower the peak temperature associated with high power GaN transistors in pulse application. The technology involves the use of an embedded microscale PCM heat storage device within the chip (near the active channels of the GaN device), which effectively increases the heat capacity of the material by taking advantage of the latent heat of the PCM. In this study, 2-D transient thermal models were developed to characterize the thermal behavior of GaN transistors with micro-scale PCM heat storage device. The model is capable of computing the spatial-temporal temperature distribution of the GaN transistor as it is rapidly pulsed and captures the formation and evolution of hot spots that form within the device. The model also captures the PCM melting behavior and latent heat absorption during the transient. The use of a PCM can effectively control the hot spot temperature by absorbing a significant portion of the transient heat input. As shown in this modeling study, the use of PCM heat storage in GaN transistors reduces the GaN hot spot temperature for a given heat input. Alternatively, the maximum allowable GaN heat input can be increased with the use of PCM. At a given heat input flux of 5×105 W/cm2, for example, the use of PCM heat storage can lower the peak temperature by 21∼22°C, relative to transistors without PCM (baseline), regardless of the duty cycle ratio. In addition, a transistor with PCM heat storage can accommodate much higher joule heat generation without exceeding the maximum allowable temperature limit, 180°C. In this study, the modeling results show that by integrating a PCM that has a 140°C melting point in a 5μm×6μm groove configuration, the critical heat flux can be increased from 13.34×105 W/cm2 (baseline) to 16.8×105 W/cm2 (with PCM), a 26% improvement. Key PCM design parameters were identified in this modeling study: (1) PCM amount; (2) PCM melting point; and (3) PCM groove structure. Their coupling and the impact on design optimization require further investigation.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"187 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133321423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767193
J. Goicochea, B. Michel
In this work, we study the impact of the phonon thermal conductivity of Silver (Ag) and Gold (Au) on the interface resistance of metal-nonmetal contacts at room temperature. The thermal conductivity of both metals is determined for bulk and thin films of varying thickness using non-equilibrium molecular dynamics (NEMD) simulations. Likewise, we determine the thermal interface resistance due to phonons of metal films embedded in a nonmetal layer composed of Silicon (Si). Based on a two-temperature model (TTM) for electrons and phonons, we determine the thermal resistance due to electron-phonon interactions and the variation of the film resistance of Ag and Au layers as a function of their thickness. The latter considering the estimated phonon contribution to the thermal conductivity of the studied metals obtained with our NEMD simulations. Two important results are presented in this work. First, we have found for the studied metals that at room temperature phonons contribute less than 1.0 % to the bulk thermal conductivity; and that their relative contribution to the conductivity and its variation with the film thickness significantly impacts the overall film resistance of metallic films.
{"title":"Impact of electron-phonon transport on the thermal resistance of metal-nonmetal interfaces","authors":"J. Goicochea, B. Michel","doi":"10.1109/STHERM.2011.5767193","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767193","url":null,"abstract":"In this work, we study the impact of the phonon thermal conductivity of Silver (Ag) and Gold (Au) on the interface resistance of metal-nonmetal contacts at room temperature. The thermal conductivity of both metals is determined for bulk and thin films of varying thickness using non-equilibrium molecular dynamics (NEMD) simulations. Likewise, we determine the thermal interface resistance due to phonons of metal films embedded in a nonmetal layer composed of Silicon (Si). Based on a two-temperature model (TTM) for electrons and phonons, we determine the thermal resistance due to electron-phonon interactions and the variation of the film resistance of Ag and Au layers as a function of their thickness. The latter considering the estimated phonon contribution to the thermal conductivity of the studied metals obtained with our NEMD simulations. Two important results are presented in this work. First, we have found for the studied metals that at room temperature phonons contribute less than 1.0 % to the bulk thermal conductivity; and that their relative contribution to the conductivity and its variation with the film thickness significantly impacts the overall film resistance of metallic films.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122356563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767189
Keiji Matsumoto, S. Ibaraki, K. Sueoka, K. Sakuma, H. Kikuchi, Y. Orii, F. Yamada
To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37–41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37–41W/mC) and its adequacy is examined.
{"title":"Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack","authors":"Keiji Matsumoto, S. Ibaraki, K. Sueoka, K. Sakuma, H. Kikuchi, Y. Orii, F. Yamada","doi":"10.1109/STHERM.2011.5767189","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767189","url":null,"abstract":"To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37–41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37–41W/mC) and its adequacy is examined.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129929640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767208
C. Ortloff, M. Vogel
Spray cooling of high temperature surfaces subject to large internal heat generation is analyzed by computational fluid dynamics (CFD) methods to determine heat transfer coefficients and the micro-physical details of coolant droplet-heated surface interactions governed by evaporative processes. A high speed, high magnification digital camera (6000 frames/sec) is used to provide test data for micron scale spray droplet size distribution and droplet velocity from a spray nozzle for different supply pressures for HFE 7100 and water coolants. Droplet test data are then applied to construct FLOW-3D CFD models [1] of numerous translating spherical droplets impacting a heated surface with internal volume heat generation and the transient, free-surface fluid dynamics and heat transfer processes computed. Transient, expanding/collapsing, chaotic coolant vapor regions generated by evaporative processes during successive multiple droplet impacts on flat and roughened surfaces sustaining large heat fluxes (from 30 to 300 W/cm2) are generated from the CFD solutions and shown to reproduce qualitative phase transition features observed from test photography. A computer program is provided to calculate heat transfer coefficients for different combinations of coolant droplet size, droplet velocity, droplet spatial distribution in nozzle sprays, heat flux magnitude, evaporation temperature and coolant flow rate incorporating the thermophysical coolant and wall properties for both flat and surface roughness cases. CFD results for a wide variety of droplet sizes, translation velocities, magnitudes of heat flux for flat and surface roughness patterns, coolant flow rates, coolant types and prescribed wall surface temperatures are used to provide physical insights into best ways to achieve maximum spray cooling heat transfer coefficients and avoid surface flooding and dry spotting. Use of high speed photographic micro-details of droplet impingement and evaporation structures on heated walls is made to qualitatively substantiate the CFD methodology by comparison of computed to test observations.
{"title":"Spray cooling heat transfer — Test and CFD analysis","authors":"C. Ortloff, M. Vogel","doi":"10.1109/STHERM.2011.5767208","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767208","url":null,"abstract":"Spray cooling of high temperature surfaces subject to large internal heat generation is analyzed by computational fluid dynamics (CFD) methods to determine heat transfer coefficients and the micro-physical details of coolant droplet-heated surface interactions governed by evaporative processes. A high speed, high magnification digital camera (6000 frames/sec) is used to provide test data for micron scale spray droplet size distribution and droplet velocity from a spray nozzle for different supply pressures for HFE 7100 and water coolants. Droplet test data are then applied to construct FLOW-3D CFD models [1] of numerous translating spherical droplets impacting a heated surface with internal volume heat generation and the transient, free-surface fluid dynamics and heat transfer processes computed. Transient, expanding/collapsing, chaotic coolant vapor regions generated by evaporative processes during successive multiple droplet impacts on flat and roughened surfaces sustaining large heat fluxes (from 30 to 300 W/cm2) are generated from the CFD solutions and shown to reproduce qualitative phase transition features observed from test photography. A computer program is provided to calculate heat transfer coefficients for different combinations of coolant droplet size, droplet velocity, droplet spatial distribution in nozzle sprays, heat flux magnitude, evaporation temperature and coolant flow rate incorporating the thermophysical coolant and wall properties for both flat and surface roughness cases. CFD results for a wide variety of droplet sizes, translation velocities, magnitudes of heat flux for flat and surface roughness patterns, coolant flow rates, coolant types and prescribed wall surface temperatures are used to provide physical insights into best ways to achieve maximum spray cooling heat transfer coefficients and avoid surface flooding and dry spotting. Use of high speed photographic micro-details of droplet impingement and evaporation structures on heated walls is made to qualitatively substantiate the CFD methodology by comparison of computed to test observations.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128776222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767183
A. Balandin
As the electronic industry moves towards few-nanometer-scale CMOS and 3D IC designs thermal management becomes crucially important for achieving high performance and reliability of advanced electronic chips [1]. One approach for mitigating the self-heating problems is finding materials with very high thermal conductivity, which can be integrated with Si ICs or used as fillers in the next generation of the thermal interface materials (TIMs). In 2008, we discovered that graphene reveals extremely high intrinsic thermal conductivity, which can exceed that of bulk graphite [2–3]. To measure the thermal conductivity of an object with a thickness of just one atomic layer, we developed an original experimental technique and applied it to graphene flake suspended across trenches in Si wafers. In this technique, the micro-Raman spectrometer performed the function of a thermometer measuring the local temperature rise from the shift in the spectral position of the Raman G peak. We explained the fact that the intrinsic thermal conductivity of graphene can be larger than that of graphite by the fundamental difference in the low-energy phonon transport in 2D graphene and 3D graphite [4–6]. The extremely high thermal conductivity of “free” suspended graphene does not mean that it will be automatically preserved when graphene is incorporated inside semiconductor chips or composite TIMs. Thermal conductivity of graphene layers depends strongly on their geometrical size, coupling to the adjacent substrate or capping layers, edges roughness and defect concentration. I will overview the experimental and theoretical results for the thermal conductivity evolution of the few-layer graphene (FLG) considering two limiting cases of the phonon transport limited by the intrinsic and extrinsic effects. The use of graphene as interconnects and heat spreaders in advanced 2D and 3D computer chips will also be discussed. The last section of the talk will have a description of the data for graphene TIM materials. We found that thermal conductivity of several types of epoxy TIMs can be significantly increased by an addition of the chemically derived graphene even at very small graphene's loading fractions. The increase in the effective thermal conductivity of graphene TIMs is much stronger than that for conventional filler materials [7]. A general outlook at the prospects of graphene electronics will conclude the talk.
{"title":"Heat conduction properties of graphene: Prospects of thermal management applications","authors":"A. Balandin","doi":"10.1109/STHERM.2011.5767183","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767183","url":null,"abstract":"As the electronic industry moves towards few-nanometer-scale CMOS and 3D IC designs thermal management becomes crucially important for achieving high performance and reliability of advanced electronic chips [1]. One approach for mitigating the self-heating problems is finding materials with very high thermal conductivity, which can be integrated with Si ICs or used as fillers in the next generation of the thermal interface materials (TIMs). In 2008, we discovered that graphene reveals extremely high intrinsic thermal conductivity, which can exceed that of bulk graphite [2–3]. To measure the thermal conductivity of an object with a thickness of just one atomic layer, we developed an original experimental technique and applied it to graphene flake suspended across trenches in Si wafers. In this technique, the micro-Raman spectrometer performed the function of a thermometer measuring the local temperature rise from the shift in the spectral position of the Raman G peak. We explained the fact that the intrinsic thermal conductivity of graphene can be larger than that of graphite by the fundamental difference in the low-energy phonon transport in 2D graphene and 3D graphite [4–6]. The extremely high thermal conductivity of “free” suspended graphene does not mean that it will be automatically preserved when graphene is incorporated inside semiconductor chips or composite TIMs. Thermal conductivity of graphene layers depends strongly on their geometrical size, coupling to the adjacent substrate or capping layers, edges roughness and defect concentration. I will overview the experimental and theoretical results for the thermal conductivity evolution of the few-layer graphene (FLG) considering two limiting cases of the phonon transport limited by the intrinsic and extrinsic effects. The use of graphene as interconnects and heat spreaders in advanced 2D and 3D computer chips will also be discussed. The last section of the talk will have a description of the data for graphene TIM materials. We found that thermal conductivity of several types of epoxy TIMs can be significantly increased by an addition of the chemically derived graphene even at very small graphene's loading fractions. The increase in the effective thermal conductivity of graphene TIMs is much stronger than that for conventional filler materials [7]. A general outlook at the prospects of graphene electronics will conclude the talk.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134113373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767201
M. Fontaine, E. Joubert, O. Latry, C. Gauthier, C. Regard, H. Polaert, P. Eudeline, M. Ketata
In this paper is presented a new approach for measuring physical values of micro-electronic compounds. Indeed an optical system is used to quantify simultaneously surface temperature and expansion of a component. This is done with a Michelson interferometer. To compare the method, the measured temperature was correlated with two other methods, IR camera and ESD diode.
{"title":"Simultaneous measures of temperature and expansion on electronic compound","authors":"M. Fontaine, E. Joubert, O. Latry, C. Gauthier, C. Regard, H. Polaert, P. Eudeline, M. Ketata","doi":"10.1109/STHERM.2011.5767201","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767201","url":null,"abstract":"In this paper is presented a new approach for measuring physical values of micro-electronic compounds. Indeed an optical system is used to quantify simultaneously surface temperature and expansion of a component. This is done with a Michelson interferometer. To compare the method, the measured temperature was correlated with two other methods, IR camera and ESD diode.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767217
M. Faqir, T. Batten, T. Mrotzek, S. Knippscheer, M. Massiot, L. Letteron, S. Rochette, O. Vendier, J. Desmarres, F. Courtade, Martin Kuball
In this work, thermo-mechanical stability of silver diamond composite materials, with thermal conductivities as high as 830 W/mK, was studied. These novel materials have great potential for applications in thermal management and electronic packaging industry. As demonstrated in our previous work, an improvement of 50% in terms of thermal management can be obtained with silver diamond composite with respect to the traditional CuW when used as base plates; however, to date their thermo-mechanical stability has not been assessed yet. Their stability is important for application such as space where thermal cycling is typical. Samples were submitted to ten thermal cycles from room temperature to 350°C, and then to 200 thermal cycles from −55°C to 125°C. Thermal properties such as thermal conductivity and coefficient of thermal expansion as well as diamond particles stress were measured before and after thermal cycles. We found that after thermal cycling, thermal conductivity decreased from 830 W/mK to 760 W/mK at room temperature. An increase in the coefficient of thermal expansion from 6 ppm/K to 7.5 ppm/K, and a diamond stress partial relaxation were also observed after thermal shock. Furthermore, some samples were submitted to a much higher temperature, namely, 780°C and slightly more pronounced degradations were obtained. Such changes in thermal properties are acceptable for many applications and still nevertheless provide a significant improvement to standard CuW heat-sinking materials. Changes in the silver-diamond interface are likely the underlying reasons for the material properties change observed. We can conclude that this material presents a good stability given the harsh conditions under which the tests were performed.
{"title":"Silver diamond composite as a new packaging solution: A thermo-mechanical stability study","authors":"M. Faqir, T. Batten, T. Mrotzek, S. Knippscheer, M. Massiot, L. Letteron, S. Rochette, O. Vendier, J. Desmarres, F. Courtade, Martin Kuball","doi":"10.1109/STHERM.2011.5767217","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767217","url":null,"abstract":"In this work, thermo-mechanical stability of silver diamond composite materials, with thermal conductivities as high as 830 W/mK, was studied. These novel materials have great potential for applications in thermal management and electronic packaging industry. As demonstrated in our previous work, an improvement of 50% in terms of thermal management can be obtained with silver diamond composite with respect to the traditional CuW when used as base plates; however, to date their thermo-mechanical stability has not been assessed yet. Their stability is important for application such as space where thermal cycling is typical. Samples were submitted to ten thermal cycles from room temperature to 350°C, and then to 200 thermal cycles from −55°C to 125°C. Thermal properties such as thermal conductivity and coefficient of thermal expansion as well as diamond particles stress were measured before and after thermal cycles. We found that after thermal cycling, thermal conductivity decreased from 830 W/mK to 760 W/mK at room temperature. An increase in the coefficient of thermal expansion from 6 ppm/K to 7.5 ppm/K, and a diamond stress partial relaxation were also observed after thermal shock. Furthermore, some samples were submitted to a much higher temperature, namely, 780°C and slightly more pronounced degradations were obtained. Such changes in thermal properties are acceptable for many applications and still nevertheless provide a significant improvement to standard CuW heat-sinking materials. Changes in the silver-diamond interface are likely the underlying reasons for the material properties change observed. We can conclude that this material presents a good stability given the harsh conditions under which the tests were performed.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122211007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The long term thermal stability of the die attach is a crucial issue for high brightness light emitting diodes (HB LEDs), which affects the junction-to-case thermal resistance, luminous flux and life time seriously. In this paper, an improved power and temperature cycling method is proposed to evaluate the thermal stability of the die attach materials for HB LEDs. The structure function method is adopted to monitor the degradation of the die attach level thermal resistance during the cycling process instead of the traditional junction-to-case thermal resistance measurement, which provides more accurate, quick and intuitive results. The experimental results indicate that the forming of solder voids is the main degradation mechanism of the die attach for HB LEDs, which is also supported by the scan acoustic microscope (C-SAM) measurement. Comparing thermal stability of different die attach materials, Au/Sn eutectic soldered LED samples present better performance than Ag paste soldered samples in this experiment.
{"title":"Thermal stability evaluation of die attach for high brightness LEDs","authors":"Guangchen Zhang, Shiwei Feng, H. Deng, Jingwan Li, Zhou Zhou, Chunsheng Guo","doi":"10.1109/STHERM.2011.5767215","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767215","url":null,"abstract":"The long term thermal stability of the die attach is a crucial issue for high brightness light emitting diodes (HB LEDs), which affects the junction-to-case thermal resistance, luminous flux and life time seriously. In this paper, an improved power and temperature cycling method is proposed to evaluate the thermal stability of the die attach materials for HB LEDs. The structure function method is adopted to monitor the degradation of the die attach level thermal resistance during the cycling process instead of the traditional junction-to-case thermal resistance measurement, which provides more accurate, quick and intuitive results. The experimental results indicate that the forming of solder voids is the main degradation mechanism of the die attach for HB LEDs, which is also supported by the scan acoustic microscope (C-SAM) measurement. Comparing thermal stability of different die attach materials, Au/Sn eutectic soldered LED samples present better performance than Ag paste soldered samples in this experiment.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767182
Ruben Gielen, F. Rogiers, Y. Joshi, M. Baelmans
This paper discusses the use of the second law in heat sink design. A new entropy-based cost function is proposed and compared with existing heat sink cost functions. A case study of a plate fin heat sink points out that this newly developed cost function offers a heat sink which is more than twice as efficient as a heat sink designed with the traditional thermal resistance minimization objective. The effects of this new heat sink design on data center cooling systems are considered and found to be significantly improving the system efficiency and waste heat recovery.
{"title":"On the use of second law based cost functions in plate fin heat sink design","authors":"Ruben Gielen, F. Rogiers, Y. Joshi, M. Baelmans","doi":"10.1109/STHERM.2011.5767182","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767182","url":null,"abstract":"This paper discusses the use of the second law in heat sink design. A new entropy-based cost function is proposed and compared with existing heat sink cost functions. A case study of a plate fin heat sink points out that this newly developed cost function offers a heat sink which is more than twice as efficient as a heat sink designed with the traditional thermal resistance minimization objective. The effects of this new heat sink design on data center cooling systems are considered and found to be significantly improving the system efficiency and waste heat recovery.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115318860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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