Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767176
Steven M. Harrington
Uptime, operating cost and serviceability are the major concerns for data center cooling. This paper will describe an air and liquid cooling system that is optimized for data centers and does not involve major infrastructure changes. This system uses a minimum heat exchanger volume and coolant volume in order to simplify the installation at the server and data center level. The goal is to reduce chiller and server power, and removing heat from the CPU and the air in the server achieves that goal. Secondary goals include reducing the volume of liquid inside the server and making it easy to swap out racks, servers or components. The proposed system uses a normal base plate and fin heat sink, with a high performance liquid cooled heat exchanger built into it. This allows heat to be extracted from the CPU as well as the air that flows through the heat sink, removing up to 100% of the heat from the entire server with the liquid cooled heat sink which makes it a literal ‘heat sink’.
{"title":"Optimal heat transfer for liquid cooling with minimal coolant volume","authors":"Steven M. Harrington","doi":"10.1109/STHERM.2011.5767176","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767176","url":null,"abstract":"Uptime, operating cost and serviceability are the major concerns for data center cooling. This paper will describe an air and liquid cooling system that is optimized for data centers and does not involve major infrastructure changes. This system uses a minimum heat exchanger volume and coolant volume in order to simplify the installation at the server and data center level. The goal is to reduce chiller and server power, and removing heat from the CPU and the air in the server achieves that goal. Secondary goals include reducing the volume of liquid inside the server and making it easy to swap out racks, servers or components. The proposed system uses a normal base plate and fin heat sink, with a high performance liquid cooled heat exchanger built into it. This allows heat to be extracted from the CPU as well as the air that flows through the heat sink, removing up to 100% of the heat from the entire server with the liquid cooled heat sink which makes it a literal ‘heat sink’.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126835129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767213
T. Treurniet, Karel Joop Bosschaart
In order to ensure the exchangeability of LED light engines in LED based luminaires, the Zhaga consortium develops standard specifications for the interfaces of LED light engines. The complete interface definition consists of the description of a mechanical, optical, electrical and thermal interface. The thermal interface has to ensure a good thermal contact between the engine and the fixture. Next to that, the heat spreading capabilities of both the engine and the fixture have to be taken into account in order to ensure sufficient heat spreading capabilities of complete luminaire. In order to come to a practical interface definition, a number of tests and test devices are proposed. Engines and fixture have to pass these tests in order to become Zhaga compliant. One test is the heat flux measurement on the LED light engine in order to determine the amount of heat that has to be transferred from the engine via the fixture. The second test is a test with a reference thermal engine in order to determine the heat spreading capabilities and the thermal resistance of a fixture. The final test is a test with a reference luminaire in order to determine the heat spreading capabilities of the LED light engine. With these three tests, we can realize a practical thermal interface definition.
{"title":"Method for heat flux measurement on LED light engines","authors":"T. Treurniet, Karel Joop Bosschaart","doi":"10.1109/STHERM.2011.5767213","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767213","url":null,"abstract":"In order to ensure the exchangeability of LED light engines in LED based luminaires, the Zhaga consortium develops standard specifications for the interfaces of LED light engines. The complete interface definition consists of the description of a mechanical, optical, electrical and thermal interface. The thermal interface has to ensure a good thermal contact between the engine and the fixture. Next to that, the heat spreading capabilities of both the engine and the fixture have to be taken into account in order to ensure sufficient heat spreading capabilities of complete luminaire. In order to come to a practical interface definition, a number of tests and test devices are proposed. Engines and fixture have to pass these tests in order to become Zhaga compliant. One test is the heat flux measurement on the LED light engine in order to determine the amount of heat that has to be transferred from the engine via the fixture. The second test is a test with a reference thermal engine in order to determine the heat spreading capabilities and the thermal resistance of a fixture. The final test is a test with a reference luminaire in order to determine the heat spreading capabilities of the LED light engine. With these three tests, we can realize a practical thermal interface definition.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132310937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767194
K. Petrosyants, N. I. Rjabov
The computational model of the temperature sensors integrated on the IC chip with power transistors is developed. The 2D/3D problem of sensor placement is mathematically described by the classic heat transfer equation coupled with the equation for current density distribution. It is shown that parasitic effects of sensor current displacement and thermo-emf generation resulting from a temperature gradients (Seebeck effect) must be taken into account. For this purpose the special differential equation is introduced. The examples of point- and strip-like temperature sensors modeling for power BJTs and ICs are demonstrated.
{"title":"Temperature sensors modeling for smart power ICs","authors":"K. Petrosyants, N. I. Rjabov","doi":"10.1109/STHERM.2011.5767194","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767194","url":null,"abstract":"The computational model of the temperature sensors integrated on the IC chip with power transistors is developed. The 2D/3D problem of sensor placement is mathematically described by the classic heat transfer equation coupled with the equation for current density distribution. It is shown that parasitic effects of sensor current displacement and thermo-emf generation resulting from a temperature gradients (Seebeck effect) must be taken into account. For this purpose the special differential equation is introduced. The examples of point- and strip-like temperature sensors modeling for power BJTs and ICs are demonstrated.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129220629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767172
S. Alavi, K. Yazawa, G. Alers, B. Vermeersch, J. Christofferson, A. Shakouri
Microelectronic integrated circuits experience nonuniform high temperatures during normal operation. Thermal expansion mismatch among the different materials comprising the device lead to a large tensile stress after high temperature cycles. Voiding and open-circuit failure from cracking of interconnects are often observed during isothermal aging and thermal fatigue tests with or without electric current. Thermoreflectance microscopy as a high resolution, non-contact imaging technique is applied for thermal profiling and reliability analysis of 500nm diameter copper interconnects under temperature stress tests. In addition to external electrical measurements which can show the aggregate change in material's or device's electrical properties, we are able to detect local temperature rise at each via. While techniques such as scanning electron microscopy can be used to locate opened circuits; thermal imaging can detect the local change in via's resistance and in the thermal resistance of the surrounding material before the complete failure. We discuss how the thermal profile could be used to identify the location of the failure and the time-to-failure of a given via in a chain.
{"title":"Thermal imaging for reliability characterization of copper vias","authors":"S. Alavi, K. Yazawa, G. Alers, B. Vermeersch, J. Christofferson, A. Shakouri","doi":"10.1109/STHERM.2011.5767172","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767172","url":null,"abstract":"Microelectronic integrated circuits experience nonuniform high temperatures during normal operation. Thermal expansion mismatch among the different materials comprising the device lead to a large tensile stress after high temperature cycles. Voiding and open-circuit failure from cracking of interconnects are often observed during isothermal aging and thermal fatigue tests with or without electric current. Thermoreflectance microscopy as a high resolution, non-contact imaging technique is applied for thermal profiling and reliability analysis of 500nm diameter copper interconnects under temperature stress tests. In addition to external electrical measurements which can show the aggregate change in material's or device's electrical properties, we are able to detect local temperature rise at each via. While techniques such as scanning electron microscopy can be used to locate opened circuits; thermal imaging can detect the local change in via's resistance and in the thermal resistance of the surrounding material before the complete failure. We discuss how the thermal profile could be used to identify the location of the failure and the time-to-failure of a given via in a chain.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767179
S. Gurrum, Matt Romig, Sandra J. Horton, D. Edwards
Thermal design of PCBs (Printed Circuit Boards) is important for electronic packages which are intended to be primarily cooled by heat flow into the PCB. Designing the required PCB coverage area through detailed numerical simulations can be computationally expensive. This article presents a quick approach to predict Junction-to-Air thermal resistance of exposed pad packages based on pre-generated detailed thermal simulations and interpolation methodology. The modeling methodology is derived from validated measurements on Quad and Inline packages with different PCB copper coverage areas. Thermal data is pre-generated through parametric simulations conducted with varying package sizes, pad sizes, and PCB copper coverage areas. The interpolation methodology quickly provides a thermal resistance versus copper coverage area curve. The interpolation approach is validated through detailed simulations on cases not included in the pre-generated thermal data. Such a quick prediction capability of temperature rise of exposed pad packages for different PCB copper coverage areas can be a valuable tool for thermal design of PCB layout.
{"title":"A quick PCB thermal calculator to aid system design of exposed pad packages","authors":"S. Gurrum, Matt Romig, Sandra J. Horton, D. Edwards","doi":"10.1109/STHERM.2011.5767179","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767179","url":null,"abstract":"Thermal design of PCBs (Printed Circuit Boards) is important for electronic packages which are intended to be primarily cooled by heat flow into the PCB. Designing the required PCB coverage area through detailed numerical simulations can be computationally expensive. This article presents a quick approach to predict Junction-to-Air thermal resistance of exposed pad packages based on pre-generated detailed thermal simulations and interpolation methodology. The modeling methodology is derived from validated measurements on Quad and Inline packages with different PCB copper coverage areas. Thermal data is pre-generated through parametric simulations conducted with varying package sizes, pad sizes, and PCB copper coverage areas. The interpolation methodology quickly provides a thermal resistance versus copper coverage area curve. The interpolation approach is validated through detailed simulations on cases not included in the pre-generated thermal data. Such a quick prediction capability of temperature rise of exposed pad packages for different PCB copper coverage areas can be a valuable tool for thermal design of PCB layout.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126610389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767190
H. Oprins, V. Cherman, M. Stucchi, B. Vandevelde, G. V. D. Plas, P. Marchal, E. Beyne
3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behavior of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, a steady state and transient analysis is presented for hot spots in 3D stacked structures. For this analysis, dedicated test chips with integrated heaters and temperature sensors are used to assess the temperature profile in the different tiers of the stack and to investigate the impact of TSVs on the temperature profile. This experimental set-up is used to evaluated and improve the thermal models for the 3D stacks.
{"title":"Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips","authors":"H. Oprins, V. Cherman, M. Stucchi, B. Vandevelde, G. V. D. Plas, P. Marchal, E. Beyne","doi":"10.1109/STHERM.2011.5767190","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767190","url":null,"abstract":"3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behavior of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, a steady state and transient analysis is presented for hot spots in 3D stacked structures. For this analysis, dedicated test chips with integrated heaters and temperature sensors are used to assess the temperature profile in the different tiers of the stack and to investigate the impact of TSVs on the temperature profile. This experimental set-up is used to evaluated and improve the thermal models for the 3D stacks.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127987548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767202
Q. Wan, J. Galloway
Measuring the case temperature is one of the most challenging measurements for determining the junction-to-case thermal resistance (Theta jc) in high power packages. This is especially true for low Theta jc measurement, in which high power is necessary to control accuracy. Inaccurate case temperature measurement would lead to an inaccurate Theta jc value. This study explores different methods for measuring case temperature and quantifies their impact on Theta jc. A new method of cold-plate protruded thermocouple is proposed and compared with commonly adopted method of lid embedded thermistor both experimentally and numerically. It is found correction is not negligible for low Theta jc measurement in both methods due to the temperature difference between the case surface and the thermal probe location. A standard test jig is also proposed to determine the correction for the cold-plate protruded thermocouple experimentally.
{"title":"Accurate Theta jc measurement for high power packages","authors":"Q. Wan, J. Galloway","doi":"10.1109/STHERM.2011.5767202","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767202","url":null,"abstract":"Measuring the case temperature is one of the most challenging measurements for determining the junction-to-case thermal resistance (Theta jc) in high power packages. This is especially true for low Theta jc measurement, in which high power is necessary to control accuracy. Inaccurate case temperature measurement would lead to an inaccurate Theta jc value. This study explores different methods for measuring case temperature and quantifies their impact on Theta jc. A new method of cold-plate protruded thermocouple is proposed and compared with commonly adopted method of lid embedded thermistor both experimentally and numerically. It is found correction is not negligible for low Theta jc measurement in both methods due to the temperature difference between the case surface and the thermal probe location. A standard test jig is also proposed to determine the correction for the cold-plate protruded thermocouple experimentally.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767195
Z. Qi, Hua-jun Dong, Yahong Wang, J. Reif
MOSFETs in an RF amplifier dissipate high heat flux due to switching and conduction loss. MOSFET's junction temperature affects product reliability adversely. This paper presents a thermal management method used in an RF amplifier development with junction to case temperature rise transient analysis, Thermal Interface Material (TIM) testing, clamping structural Finite Element Analysis (FEA), and Computational Fluid Dynamics (CFD) aided cold plate optimization. Using the systematic method presented in this paper, thermal management of MOSFET junction temperature can be implemented with clear insights of temperature budget consumption in each section, and optimization options.
{"title":"Thermal management of MOSFET junction temperature in RF amplifier","authors":"Z. Qi, Hua-jun Dong, Yahong Wang, J. Reif","doi":"10.1109/STHERM.2011.5767195","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767195","url":null,"abstract":"MOSFETs in an RF amplifier dissipate high heat flux due to switching and conduction loss. MOSFET's junction temperature affects product reliability adversely. This paper presents a thermal management method used in an RF amplifier development with junction to case temperature rise transient analysis, Thermal Interface Material (TIM) testing, clamping structural Finite Element Analysis (FEA), and Computational Fluid Dynamics (CFD) aided cold plate optimization. Using the systematic method presented in this paper, thermal management of MOSFET junction temperature can be implemented with clear insights of temperature budget consumption in each section, and optimization options.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126341560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767174
Xudong Tang, R. Bonner, T. Desai, A. Fan
A novel thermal management technology was explored to lower the peak temperature associated with high power GaN transistors in pulse application. The technology involves the use of an embedded microscale PCM heat storage device within the chip (near the active channels of the GaN device), which effectively increases the heat capacity of the material by taking advantage of the latent heat of the PCM. In this study, 2-D transient thermal models were developed to characterize the thermal behavior of GaN transistors with micro-scale PCM heat storage device. The model is capable of computing the spatial-temporal temperature distribution of the GaN transistor as it is rapidly pulsed and captures the formation and evolution of hot spots that form within the device. The model also captures the PCM melting behavior and latent heat absorption during the transient. The use of a PCM can effectively control the hot spot temperature by absorbing a significant portion of the transient heat input. As shown in this modeling study, the use of PCM heat storage in GaN transistors reduces the GaN hot spot temperature for a given heat input. Alternatively, the maximum allowable GaN heat input can be increased with the use of PCM. At a given heat input flux of 5×105 W/cm2, for example, the use of PCM heat storage can lower the peak temperature by 21∼22°C, relative to transistors without PCM (baseline), regardless of the duty cycle ratio. In addition, a transistor with PCM heat storage can accommodate much higher joule heat generation without exceeding the maximum allowable temperature limit, 180°C. In this study, the modeling results show that by integrating a PCM that has a 140°C melting point in a 5μm×6μm groove configuration, the critical heat flux can be increased from 13.34×105 W/cm2 (baseline) to 16.8×105 W/cm2 (with PCM), a 26% improvement. Key PCM design parameters were identified in this modeling study: (1) PCM amount; (2) PCM melting point; and (3) PCM groove structure. Their coupling and the impact on design optimization require further investigation.
{"title":"A 2-D numerical study of microscale phase change material thermal storage for GaN transistor thermal management","authors":"Xudong Tang, R. Bonner, T. Desai, A. Fan","doi":"10.1109/STHERM.2011.5767174","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767174","url":null,"abstract":"A novel thermal management technology was explored to lower the peak temperature associated with high power GaN transistors in pulse application. The technology involves the use of an embedded microscale PCM heat storage device within the chip (near the active channels of the GaN device), which effectively increases the heat capacity of the material by taking advantage of the latent heat of the PCM. In this study, 2-D transient thermal models were developed to characterize the thermal behavior of GaN transistors with micro-scale PCM heat storage device. The model is capable of computing the spatial-temporal temperature distribution of the GaN transistor as it is rapidly pulsed and captures the formation and evolution of hot spots that form within the device. The model also captures the PCM melting behavior and latent heat absorption during the transient. The use of a PCM can effectively control the hot spot temperature by absorbing a significant portion of the transient heat input. As shown in this modeling study, the use of PCM heat storage in GaN transistors reduces the GaN hot spot temperature for a given heat input. Alternatively, the maximum allowable GaN heat input can be increased with the use of PCM. At a given heat input flux of 5×105 W/cm2, for example, the use of PCM heat storage can lower the peak temperature by 21∼22°C, relative to transistors without PCM (baseline), regardless of the duty cycle ratio. In addition, a transistor with PCM heat storage can accommodate much higher joule heat generation without exceeding the maximum allowable temperature limit, 180°C. In this study, the modeling results show that by integrating a PCM that has a 140°C melting point in a 5μm×6μm groove configuration, the critical heat flux can be increased from 13.34×105 W/cm2 (baseline) to 16.8×105 W/cm2 (with PCM), a 26% improvement. Key PCM design parameters were identified in this modeling study: (1) PCM amount; (2) PCM melting point; and (3) PCM groove structure. Their coupling and the impact on design optimization require further investigation.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"187 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133321423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767191
R. Mandel, M. Ohadi, A. Shooshtari, S. Dessiatoun
A model was developed to simulate the performance of a microgrooved surface undergoing steady thin film evaporation subject to a specified superheat on the groove wall. A theoretical thin film model was coupled with a meniscus curve model to accurately model the complete system. A numerical routine was successfully implemented to solve the governing non-linear differential equations of an evaporating thin film subject to a specified set of groove wall superheat and fluid/interface properties. The resulting thin film profile was used to correlate the heat transfer characteristics as a function of radius of curvature of the intrinsic meniscus. These correlations were then used by another numerical routine to solve for the meniscus curve profile as a function of groove geometry and fluid properties. The total heat, wetted length, heat transfer coefficient, and if desired, 3-D surface plot of the liquid bulk in the microgroove were then extracted from the results. The model results were then compared to the available experimental results. Results of the preliminary comparison with the experiments, as well as future planned tasks, are discussed in this paper.
{"title":"Thin film evaporation on microstructured surfaces — Application to cooling high heat flux electronics","authors":"R. Mandel, M. Ohadi, A. Shooshtari, S. Dessiatoun","doi":"10.1109/STHERM.2011.5767191","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767191","url":null,"abstract":"A model was developed to simulate the performance of a microgrooved surface undergoing steady thin film evaporation subject to a specified superheat on the groove wall. A theoretical thin film model was coupled with a meniscus curve model to accurately model the complete system. A numerical routine was successfully implemented to solve the governing non-linear differential equations of an evaporating thin film subject to a specified set of groove wall superheat and fluid/interface properties. The resulting thin film profile was used to correlate the heat transfer characteristics as a function of radius of curvature of the intrinsic meniscus. These correlations were then used by another numerical routine to solve for the meniscus curve profile as a function of groove geometry and fluid properties. The total heat, wetted length, heat transfer coefficient, and if desired, 3-D surface plot of the liquid bulk in the microgroove were then extracted from the results. The model results were then compared to the available experimental results. Results of the preliminary comparison with the experiments, as well as future planned tasks, are discussed in this paper.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129902997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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