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2022 International Symposium on Semiconductor Manufacturing (ISSM)最新文献

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Deposition rate dependence of the 5 nm-thick ferroelectric nondoped HfO2 on MFSFET characteristics 5nm厚铁电非掺杂HfO2沉积速率对mfset特性的影响
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10026898
Masakazu Tanuma, Joong‐Won Shin, S. Ohmi
In this research, deposition rate dependence of 5 nm-thick ferroelectric nondoped HfO2 (FeND-HfO2) on the device characteristics was investigated. The equivalent oxide thickness (EOT) and leakage current were decreased by increasing deposition rate of HfO2 from 5.0 nm/min to 6.0 nm/min. The subthreshold swing (SS) of 107 mV/dec. and saturation mobility (μsat) of 150 cm2/(Vs) were obtained with deposition rate of 6.0 nm/min. Furthermore, the threshold voltage (VTH) was controllable as the number of identical erase pulse of 4 V/1 μs was increased, which suggested the VTH control of approximately 10 mV.
在本研究中,研究了5nm厚铁电非掺杂HfO2 (FeND-HfO2)沉积速率对器件特性的依赖关系。当HfO2的沉积速率由5.0 nm/min提高到6.0 nm/min时,等效氧化厚度(EOT)和漏电流降低。阈下摆幅(SS)为107 mV/dec。饱和迁移率(μsat)为150 cm2/(Vs),沉积速率为6.0 nm/min。阈值电压(VTH)随着相同擦除脉冲数(4 V/1 μs)的增加而可控,表明阈值电压可控制在10 mV左右。
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引用次数: 1
Practical Load Impedance Monitoring System Externally Installed in Plasma Etching Equipment 等离子蚀刻设备外接实用负载阻抗监测系统
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10027105
Y. Kasashima, Shinji Kuniie, Toshiyuki Sayama, T. Tabaru
We have developed the load impedance monitoring method for plasma etching process, which can be externally installed in mass-production equipment. The monitoring system can detect micro-arc discharge and monitor the condition of the film deposited on inner wall of process chamber. In this study, we have upgraded the monitoring system to enhance precision, practicality, and versatility. The system can be used as an effective method for real-time and noninvasive monitoring of plasma etching process.
我们开发了一种用于等离子体刻蚀过程的负载阻抗监测方法,该方法可以安装在量产设备的外部。该监测系统可以检测微弧放电,并监测工艺室内壁沉积膜的状况。在本研究中,我们对监测系统进行了升级,以提高精度、实用性和通用性。该系统可作为等离子体刻蚀过程实时、无创监测的有效手段。
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引用次数: 0
Application of Natural Language Processing in Semiconductor Manufacturing 自然语言处理在半导体制造中的应用
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10026893
Daisuke Kobayashi, Shunsaku Yasuda, Takashi Iuti, Shiho Ito
Recently, natural language processing has been making great progress in the AI field and is attracting attention. This paper describes the application of natural language processing in semiconductor manufacturing. No numerical or image data were used in any of the analyses. Using the natural language processing engine developed by SONY, we were able to analyze trends in quality troubles and extract features of manufacturing equipment from text data alone by performing various natural language processing represented by Bag-of-Ngrams and Chi-square test. By this, it can contribute to quality and productivity improvements from a different perspective.
近年来,自然语言处理在人工智能领域取得了很大的进展,引起了人们的关注。本文介绍了自然语言处理在半导体制造中的应用。在任何分析中都没有使用数值或图像数据。使用SONY开发的自然语言处理引擎,通过以Bag-of-Ngrams和卡方检验为代表的各种自然语言处理,我们能够单独从文本数据中分析质量故障的趋势,提取制造设备的特征。通过这种方式,它可以从不同的角度促进质量和生产力的提高。
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引用次数: 0
Maintenance Content Reduction and Digitalization for Performance Optimization 减少维修内容和数字化以优化性能
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10026947
Christopher Bode
One bedrock requirement within the semiconductor industry is the need for a comprehensive maintenance program to support reliable and predictable tool performance. While this is true, it is certainly not the case where “more is better,” but rather an effort to define the truly necessary actions and best-known methods in maintaining tools to optimize availability, productivity, and product quality. The ongoing development and integration of Smart Manufacturing solutions across the factory systems landscape is now playing a role toward these objectives in providing a foundation for defining, deploying, and managing optimized maintenance task workflows. This paper will present both the efforts of companies using FabRecover, a novel maintenance management decision support framework, and the resulting demonstrable improvements that were achieved through such investments.
半导体行业的一个基本要求是需要一个全面的维护计划,以支持可靠和可预测的工具性能。虽然这是对的,但这肯定不是“越多越好”的情况,而是在维护工具以优化可用性、生产力和产品质量方面定义真正必要的操作和最知名的方法的努力。智能制造解决方案在工厂系统领域的持续开发和集成正在为这些目标提供基础,为定义、部署和管理优化的维护任务工作流提供基础。本文将展示使用FabRecover(一种新的维护管理决策支持框架)的公司所做的努力,以及通过这种投资所实现的可证明的改进。
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引用次数: 0
Yield Prediction with Machine Learning and Parameter Limits in Semiconductor Production 半导体生产中基于机器学习和参数限制的良率预测
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10027006
R. Busch, Michael G. Wahl, P. Czerner, B. Choubey
Yield is an important cost factor in wafer production. Therefore, continuous data-driven yield monitoring and optimization provides opportunities to reduce production costs. Predicting yield during production would reveal its relationships with production parameters enabling dynamic optimization with a preventive and active increase in yield. In our investigations, we will first predict the yield based on one yield critical process step and later on with the data of four process steps. We will use different machine learning methods for this. Furthermore, we will look at whether the classification into good and bad yield values with these methods provides better results for the prediction. Another point of our investigations are the parameter limits of the individual methods. We show that these can be controlled by a simple method and optimised, if necessary.
良率是晶圆生产中一个重要的成本因素。因此,持续的数据驱动的产量监测和优化为降低生产成本提供了机会。在生产过程中预测产量将揭示其与生产参数的关系,从而实现动态优化,预防和主动增加产量。在我们的研究中,我们将首先根据一个产率关键工艺步骤预测产率,然后用四个工艺步骤的数据预测产率。我们将使用不同的机器学习方法。此外,我们将研究用这些方法对良莠产量值的分类是否能为预测提供更好的结果。我们研究的另一点是个别方法的参数极限。我们表明,这些可以通过一个简单的方法来控制,并在必要时进行优化。
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引用次数: 1
Application of Big Data Science in High Reliability Automotive Wafer Yield Management System and Failure Analysis 大数据科学在高可靠性汽车晶圆良率管理系统及失效分析中的应用
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10026887
Chia-Cheng Kuo, Po-Chih Chen, Chang-Tsun Tseng
The system automatically produces yield reports, shipping reports, real-time yield monitoring and statistics, abnormal cause statistics, Yield Chart, etc., to assist manufacturing, process, integration and other personnel to quickly Obtain the finished product/work in process yield report, and grasp the product yield information in real time, and find possible yield problems in real time. With the yield analysis tool provided by this system, we can quickly find the possible abnormal reasons to reduce the abnormal yield rate and the impact of production lines and shipments.
系统自动生成良率报表、出货报表、实时良率监控与统计、异常原因统计、良率图等,协助制造、工艺、集成等人员快速获取成品/在制品良率报表,实时掌握产品良率信息,实时发现可能存在的良率问题。通过本系统提供的良率分析工具,可以快速发现可能出现的异常原因,降低异常良率,降低对生产线和出货的影响。
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引用次数: 0
Advanced Process Control Model for Trench Shape of Power Devices 动力装置沟槽形状的先进过程控制模型
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10026901
Takumi Ito, Wang Xueting, Y. Oomuro, Kazutaka Nagashima
In the semiconductor manufacturing, the manufacturing equipment is managed via the quality control (QC). The shape of the pattern is checked whether it meets the specification. If the shape is out of the specification, some recipe parameters are modified so that the shape meets the specification. The calculation method of the recipe parameters depends on the know-how of the individual engineers, which causes difficulties in the QC. We develop the automatic calculation of the optimal recipe parameters with Advanced Process Control (APC) model in order to solve these problems.
在半导体制造中,通过质量控制(QC)对制造设备进行管理。检查图案的形状是否符合规格。如果形状不符合规格,则修改一些配方参数以使形状符合规格。配方参数的计算方法取决于工程师个人的专业知识,这给质量控制带来了困难。为了解决这些问题,我们开发了先进过程控制(APC)模型自动计算最优配方参数。
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引用次数: 0
Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture 基于Mesa架构的Ge-On-Si耗尽型晶体管工艺优化
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10027013
Sumit Choudhary, D. Schwarz, H. Funk, K. P. Sharma, S. Sharma, J. Schulze
The p-Ge layers are epitaxially grown by MBE over the n-Ge and strain-free Ge buffer layers on the Si substrate. The drain-source & channel mesa is patterned in the p-Ge layer to create the raised active channel. Post-plasma oxidation was carried out to improve the interface properties of Ge channel. The proposed process doesn't involve source-drain implants, ease channel patterning using MAPDST, a -ve tone resist with high etch resistance and selectivity w.r.t. Ge. The process flow scheme will utilize the “beyond Si” channel materials over Si substrates, concurrently exploiting the standard well, established state-of-art Si CMOS fabrication technology.
通过MBE在Si衬底上的n-Ge和无应变Ge缓冲层上外延生长p-Ge层。漏源&通道平台在p-Ge层中进行图案化,以创建凸起的有源通道。采用等离子体后氧化技术改善了锗通道的界面性能。所提出的工艺不涉及源漏植入物,使用MAPDST(一种具有高耐蚀性和选择性的- 5色调抗蚀剂)进行通道图形化。该工艺流程方案将利用硅衬底上的“超硅”通道材料,同时利用标准的、成熟的、最先进的硅CMOS制造技术。
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引用次数: 0
Ultra-Fast Etching of Photoresist by Reactive Atmospheric-Pressure Thermal Plasma Jet 反应常压热等离子体射流超快速刻蚀光刻胶
Pub Date : 2022-12-12 DOI: 10.1109/issm55802.2022.10027028
Hibiki Kato, H. Hanafusa, Takuma Sato, S. Higashi
We have developed a new plasma source, reactive atmospheric-pressure micro-thermal-plasma-jet (R-μTPJ) for ultra-fast etching of photoresist. R-μTPJ was generated by DC arc discharge of Ar and O2 with input power of 260 W. local heating and simultaneous supply of reactive oxygen species has achieved an etching rate as high as 46.3 μm/s.
我们开发了一种新的等离子体源——反应大气压微热等离子体射流(R-μTPJ),用于光刻胶的超快速刻蚀。采用输入功率为260 w的氩气和氧气直流电弧放电产生R-μTPJ,局部加热并同时提供活性氧,刻蚀速率高达46.3 μm/s。
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引用次数: 0
Preparation of Uniform SiO2 Insulating Layer on the Inner Wall of TSV by Thermal Oxidation 热氧化法制备TSV内壁均匀SiO2保温层
Pub Date : 2022-12-12 DOI: 10.1109/ISSM55802.2022.10027078
Guo Fengjie, Rang Yang, Wang Shuo, Ma Kui, Yang Fa Shun
SiO2 insulating layer is an indispensable part of a TSV. In the current process, the SiO2 insulating layer is commonly deposited on the inner wall of the TSV based on deep trench sputtering method. The thickness at different position (neck, middle, bottom) of the SiO2 insulating layer, deposited by deep trench sputtering, is non-uniform. In this paper, the thickness uniformity of SiO2 insulating layer prepared on the inner wall of TSV based on CVD&PVD process and thermal oxidation method is comparatively studied. The experimental results show that, based on the CVD&PVD process, the average thickness of the SiO2 insulating layer at middle and bottom position of the TSV has changed by - 54.02% and - 58.30% compared with that at the top position, respectively. Based on the thermal oxidation method, the average thickness of the SiO2 insulating layer at middle and bottom position of the TSV has changed by 1.17% and 0.26% compared with that at the top position, respectively. The thermal oxidation method can realize the SiO2 insulating layer with uniform thickness on the inner wall of TSV.
SiO2绝缘层是TSV不可缺少的组成部分。在目前的工艺中,通常采用深沟槽溅射法在TSV的内壁上沉积SiO2绝缘层。深沟溅射法沉积的SiO2保温层在不同位置(颈部、中部、底部)厚度不均匀。本文对基于CVD&PVD法和热氧化法制备的TSV内壁SiO2保温层的厚度均匀性进行了比较研究。实验结果表明,基于CVD&PVD工艺,TSV中部和底部SiO2保温层的平均厚度分别比顶部变化了- 54.02%和- 58.30%。采用热氧化法,TSV中部和底部SiO2保温层的平均厚度较顶部分别变化了1.17%和0.26%。热氧化法可以在TSV内壁上实现厚度均匀的SiO2保温层。
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2022 International Symposium on Semiconductor Manufacturing (ISSM)
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