Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871207
Zhiyi Han, N. Goldsman, Chung-Kai Lin
A new approach for simulating quantum transport in nanoscale semiconductor devices is presented. The method is based on the self-consistent solution of the Poisson and Wigner equations within a device. The spherical harmonic approach is used to transform the Wigner equation into a tractable expression. The results provide the distribution function and its averages throughout the device. The method has been applied to a MOSFET and a BJT. Inclusion of quantum effects reduces carrier concentrations near potential energy barriers, leading to reduced terminal current.
{"title":"2-D quantum transport device modeling by self-consistent solution of the Wigner and Poisson equations","authors":"Zhiyi Han, N. Goldsman, Chung-Kai Lin","doi":"10.1109/SISPAD.2000.871207","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871207","url":null,"abstract":"A new approach for simulating quantum transport in nanoscale semiconductor devices is presented. The method is based on the self-consistent solution of the Poisson and Wigner equations within a device. The spherical harmonic approach is used to transform the Wigner equation into a tractable expression. The results provide the distribution function and its averages throughout the device. The method has been applied to a MOSFET and a BJT. Inclusion of quantum effects reduces carrier concentrations near potential energy barriers, leading to reduced terminal current.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133817809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871258
M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, H. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, N. Nakayama
We present here the MOSFET model HiSIM (Hiroshima University Starc IGFET model). As HiSIM employs the drift-diffusion approximation and preserves correct modeling of the surface potential in the channel, it is not only accurate, but additionally, model parameter number is small, parameter interdependence is removed, and parameter extraction becomes easy. Measured current-voltage characteristics of advanced MOSFETs are thus reproduced with only 19 model parameters.
{"title":"HiSIM: a drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction","authors":"M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, H. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, N. Nakayama","doi":"10.1109/SISPAD.2000.871258","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871258","url":null,"abstract":"We present here the MOSFET model HiSIM (Hiroshima University Starc IGFET model). As HiSIM employs the drift-diffusion approximation and preserves correct modeling of the surface potential in the channel, it is not only accurate, but additionally, model parameter number is small, parameter interdependence is removed, and parameter extraction becomes easy. Measured current-voltage characteristics of advanced MOSFETs are thus reproduced with only 19 model parameters.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125550220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871223
Yoo-Hyon Kim, Kwang-Jae Yoo, Kyung-hyun Kim, Bo-Yeon Yoon, Young-Kwan Park, Sang-Rok Ha, J. Kong
Simulation of chemical-mechanical polishing is important because the chip-level planarity and wafer-level uniformity dependent on many dynamic factors are difficult to control. CHAMPS (chemical mechanical planarization simulator) has been developed for predicting and optimizing the thickness distribution after the CMP process using the chip level pattern density and an elastic spring model including equipment parameters. In this work, the results of CMP simulation are shown to agree well with the measured data. This simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve planarity and uniformity.
{"title":"CHAMPS (chemical-mechanical planarization simulator)","authors":"Yoo-Hyon Kim, Kwang-Jae Yoo, Kyung-hyun Kim, Bo-Yeon Yoon, Young-Kwan Park, Sang-Rok Ha, J. Kong","doi":"10.1109/SISPAD.2000.871223","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871223","url":null,"abstract":"Simulation of chemical-mechanical polishing is important because the chip-level planarity and wafer-level uniformity dependent on many dynamic factors are difficult to control. CHAMPS (chemical mechanical planarization simulator) has been developed for predicting and optimizing the thickness distribution after the CMP process using the chip level pattern density and an elastic spring model including equipment parameters. In this work, the results of CMP simulation are shown to agree well with the measured data. This simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve planarity and uniformity.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122497378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871241
M. Ancona, B. Biegel
Density-gradient theory enables engineering-oriented analyses of electronic devices in which quantum confinement and tunneling phenomena are significant (Ancona and Tiersten, 1987; Ancona, 1990; Ancona et al, 1999). A nonlinear three-point discretization of the density-gradient equations is presented. The new method, an exponential-fitting scheme, is evaluated using numerical examples involving both quantum confinement and tunneling. The nonlinear discretization is shown to perform far better than the conventional linear version allowing for a substantial easing in the mesh refinement, especially in tunneling problems.
密度梯度理论使面向工程的电子器件分析成为可能，其中量子约束和隧道现象是重要的(Ancona和Tiersten, 1987;安科纳,1990;Ancona et al, 1999)。提出了密度梯度方程的非线性三点离散化方法。用涉及量子约束和隧道效应的数值例子对指数拟合方法进行了评价。非线性离散化显示出比传统的线性版本执行得更好，允许在网格细化方面有实质性的缓解，特别是在隧道问题中。
{"title":"Nonlinear discretization scheme for the density-gradient equations","authors":"M. Ancona, B. Biegel","doi":"10.1109/SISPAD.2000.871241","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871241","url":null,"abstract":"Density-gradient theory enables engineering-oriented analyses of electronic devices in which quantum confinement and tunneling phenomena are significant (Ancona and Tiersten, 1987; Ancona, 1990; Ancona et al, 1999). A nonlinear three-point discretization of the density-gradient equations is presented. The new method, an exponential-fitting scheme, is evaluated using numerical examples involving both quantum confinement and tunneling. The nonlinear discretization is shown to perform far better than the conventional linear version allowing for a substantial easing in the mesh refinement, especially in tunneling problems.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129219593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871243
W. Schoenmaker, W. Magnus
A new formulation for gate-leakage currents due to quantum tunneling is presented. The resulting model has been inserted into software modules. The relative importance of various gate stack design parameters is investigated using DOE/RSM methods.
{"title":"Nuclear modeling of quantum gate leakage currents with sensitivity analysis","authors":"W. Schoenmaker, W. Magnus","doi":"10.1109/SISPAD.2000.871243","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871243","url":null,"abstract":"A new formulation for gate-leakage currents due to quantum tunneling is presented. The resulting model has been inserted into software modules. The relative importance of various gate stack design parameters is investigated using DOE/RSM methods.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124373595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871195
C. McAndrew
Predictive modeling of components in IC manufacturing technologies is an essential part of coupled technology and circuit development. TCAD simulation is often viewed as the best method to generate predictive simulations; however, it has some limitations. Engineering experience, extrapolated technology requirements, and compact models all must be invoked in the provision of predictive circuit level technology data. This paper describes the techniques and information required for effective and efficient engineering predictions of technology capability, including statistical variations, and notes deficiencies (and therefore opportunities) in the TCAD simulations that underlie compact modeling for predictive technology characterization.
{"title":"Predictive technology characterization, missing links between TCAD and compact modeling","authors":"C. McAndrew","doi":"10.1109/SISPAD.2000.871195","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871195","url":null,"abstract":"Predictive modeling of components in IC manufacturing technologies is an essential part of coupled technology and circuit development. TCAD simulation is often viewed as the best method to generate predictive simulations; however, it has some limitations. Engineering experience, extrapolated technology requirements, and compact models all must be invoked in the provision of predictive circuit level technology data. This paper describes the techniques and information required for effective and efficient engineering predictions of technology capability, including statistical variations, and notes deficiencies (and therefore opportunities) in the TCAD simulations that underlie compact modeling for predictive technology characterization.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121560001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871208
M. Ogawa, R. Tominaga, T. Miyoshi
We have studied quantum transport in a Si interband tunneling diode (ITD) based upon a tight-binding nonequilibrium Green's function method. In the simulation, an empirical tight-binding theory has been used to take into account realistic band structures. Comparison has been made between the results of our multiband (MB) model and those of conventional two-band (2B) model. It is found that the current-voltage (I-V) characteristics of the Si ITD have considerably smaller peak current density than the 2B model, since our MB model reflects the nature of indirect gap structure.
{"title":"Multi-band simulation of interband tunneling devices reflecting realistic band structure","authors":"M. Ogawa, R. Tominaga, T. Miyoshi","doi":"10.1109/SISPAD.2000.871208","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871208","url":null,"abstract":"We have studied quantum transport in a Si interband tunneling diode (ITD) based upon a tight-binding nonequilibrium Green's function method. In the simulation, an empirical tight-binding theory has been used to take into account realistic band structures. Comparison has been made between the results of our multiband (MB) model and those of conventional two-band (2B) model. It is found that the current-voltage (I-V) characteristics of the Si ITD have considerably smaller peak current density than the 2B model, since our MB model reflects the nature of indirect gap structure.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121573174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871229
M. Ieong, H.-S.P. Wong, Y. Taur, P. Oldiges, D. Frank
In this paper, the performance of 25 nm double-gate, back-gate and super-halo CMOS devices has been analyzed, including the self-consistent 2D quantization effect. The drive current is enhanced by the gate-to-body coupling effect for double-gate with ultra-thin body. The channel quantization effect can substantially degrade the drive current for asymmetric double-gate, back-gate, and bulk CMOS ICs. It is demonstrated that the exceptional SCE immunity in SDG offers substantial performance leverage over conventional MOSFET structures.
{"title":"DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS","authors":"M. Ieong, H.-S.P. Wong, Y. Taur, P. Oldiges, D. Frank","doi":"10.1109/SISPAD.2000.871229","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871229","url":null,"abstract":"In this paper, the performance of 25 nm double-gate, back-gate and super-halo CMOS devices has been analyzed, including the self-consistent 2D quantization effect. The drive current is enhanced by the gate-to-body coupling effect for double-gate with ultra-thin body. The channel quantization effect can substantially degrade the drive current for asymmetric double-gate, back-gate, and bulk CMOS ICs. It is demonstrated that the exceptional SCE immunity in SDG offers substantial performance leverage over conventional MOSFET structures.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125029784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871252
K. Matsuzawa, H. Kawashima, K. Ouchi
The lattice heat equation and the Schottky contact model were implemented in a device simulator to evaluate the influences of self-heating on inversion layer mobility /spl mu//sub inv/ and contact resistance R/sub co/ in scaled-down nMOSFETs. It is shown that the self-heating degrades /spl mu//sub inv/ and reduces R/sub co/ of source/drain silicide. As ambient temperature T/sub amb/ increases, the degradation of /spl mu//sub inv/ becomes more pronounced, because of the different contribution of the temperature dependence of the phonon scattering in the /spl mu//sub inv/ model. Conversely, the reduction of R/sub co/ by self-heating becomes more pronounced as T/sub amb/ decreases.
{"title":"Simulation of self-heating and contact resistance influences on nMOSFETs","authors":"K. Matsuzawa, H. Kawashima, K. Ouchi","doi":"10.1109/SISPAD.2000.871252","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871252","url":null,"abstract":"The lattice heat equation and the Schottky contact model were implemented in a device simulator to evaluate the influences of self-heating on inversion layer mobility /spl mu//sub inv/ and contact resistance R/sub co/ in scaled-down nMOSFETs. It is shown that the self-heating degrades /spl mu//sub inv/ and reduces R/sub co/ of source/drain silicide. As ambient temperature T/sub amb/ increases, the degradation of /spl mu//sub inv/ becomes more pronounced, because of the different contribution of the temperature dependence of the phonon scattering in the /spl mu//sub inv/ model. Conversely, the reduction of R/sub co/ by self-heating becomes more pronounced as T/sub amb/ decreases.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131333067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871228
S. Saxena, P. McNamara, A. Shibkov, V. Axelrad, C. Guardiani
System-on-chip designs require low cost integration of analog and digital blocks. Often, the analog requirements are not considered sufficiently early in the device design cycle, resulting in devices that are suboptimal for the analog components. This paper presents an innovative methodology for deriving comprehensive device specifications based upon a set of figure-of-merit circuits which account for both analog and digital requirements. By utilizing these specifications for device design, a more efficient codevelopment of mixed-signal processes, libraries and products is possible. The methodology is illustrated with an example based upon an advanced 120 nm CMOS technology.
{"title":"Circuit-device co-design for high performance mixed-signal technologies","authors":"S. Saxena, P. McNamara, A. Shibkov, V. Axelrad, C. Guardiani","doi":"10.1109/SISPAD.2000.871228","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871228","url":null,"abstract":"System-on-chip designs require low cost integration of analog and digital blocks. Often, the analog requirements are not considered sufficiently early in the device design cycle, resulting in devices that are suboptimal for the analog components. This paper presents an innovative methodology for deriving comprehensive device specifications based upon a set of figure-of-merit circuits which account for both analog and digital requirements. By utilizing these specifications for device design, a more efficient codevelopment of mixed-signal processes, libraries and products is possible. The methodology is illustrated with an example based upon an advanced 120 nm CMOS technology.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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