Pub Date : 2000-10-01DOI: 10.1109/SISPAD.2000.871242
S. Mudanai, Y.-Y. Fan, Q. Ouyang, A. Tasch, F. Register, D. Kwong, S. Banerjee
The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schrodinger's equation and allowing for wave function penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The WKB solution agrees well with the tunneling currents predicted by this technique. For the same effective oxide thickness (EOT), the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-k dielectrics as gate insulators, the interfacial oxide must be eliminated. We also present for the first time the C-V curves obtained assuming that the wave function penetrates into the oxide.
{"title":"Modeling of direct tunneling current through gate dielectric stacks","authors":"S. Mudanai, Y.-Y. Fan, Q. Ouyang, A. Tasch, F. Register, D. Kwong, S. Banerjee","doi":"10.1109/SISPAD.2000.871242","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871242","url":null,"abstract":"The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schrodinger's equation and allowing for wave function penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The WKB solution agrees well with the tunneling currents predicted by this technique. For the same effective oxide thickness (EOT), the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-k dielectrics as gate insulators, the interfacial oxide must be eliminated. We also present for the first time the C-V curves obtained assuming that the wave function penetrates into the oxide.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871238
S. Reggiani, A. Bertoni, P. Bordone, R. Brunetti, C. Jacoboni, M. Rudan, G. Baccarani
A solid-state implementation of a set of one- and two-qbit gates for quantum computing is proposed. The qbit is defined as the state of an electron running along two quantum wires, suitably coupled through a potential barrier with variable height and/or width. Single-qbit gates are implemented using the coupling between the two wires. The two-qbit gates have been designed using a Coulomb coupler to induce a mutual phase modulation of the two qbits. A number of runs have been performed using a time-dependent 2D Schrodinger solver.
{"title":"Two-qbit gates based on coupled quantum wires","authors":"S. Reggiani, A. Bertoni, P. Bordone, R. Brunetti, C. Jacoboni, M. Rudan, G. Baccarani","doi":"10.1109/SISPAD.2000.871238","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871238","url":null,"abstract":"A solid-state implementation of a set of one- and two-qbit gates for quantum computing is proposed. The qbit is defined as the state of an electron running along two quantum wires, suitably coupled through a potential barrier with variable height and/or width. Single-qbit gates are implemented using the coupling between the two wires. The two-qbit gates have been designed using a Coulomb coupler to induce a mutual phase modulation of the two qbits. A number of runs have been performed using a time-dependent 2D Schrodinger solver.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871196
S. Theiss, M. Caturla, T. Lenosky, B. Sadigh, T. Díaz de la Rubia, M. Giles, M. Foad
We present a kinetic Monte Carlo model for boron diffusion, clustering and activation in ion implanted silicon. The input to the model is based on a combination of experimental data and ab initio calculations. The model shows that boron diffusion and activation are low while vacancy clusters are present in the system. As the vacancy clusters dissociate, boron becomes substitutional and the active fraction increases rapidly. At the same time, the total boron diffusion length also increases rapidly while interstitial clusters ripen. The final burst of boron diffusion occurs as the large interstitial clusters dissolve, but most of the transient diffusion of the implanted boron has already taken place by this time. We show that these results are in excellent agreement with experimental data on annealed dopant profiles and dopant activation as function of annealing time.
{"title":"First-principles-based predictive simulations of B diffusion and activation in ion implanted Si","authors":"S. Theiss, M. Caturla, T. Lenosky, B. Sadigh, T. Díaz de la Rubia, M. Giles, M. Foad","doi":"10.1109/SISPAD.2000.871196","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871196","url":null,"abstract":"We present a kinetic Monte Carlo model for boron diffusion, clustering and activation in ion implanted silicon. The input to the model is based on a combination of experimental data and ab initio calculations. The model shows that boron diffusion and activation are low while vacancy clusters are present in the system. As the vacancy clusters dissociate, boron becomes substitutional and the active fraction increases rapidly. At the same time, the total boron diffusion length also increases rapidly while interstitial clusters ripen. The final burst of boron diffusion occurs as the large interstitial clusters dissolve, but most of the transient diffusion of the implanted boron has already taken place by this time. We show that these results are in excellent agreement with experimental data on annealed dopant profiles and dopant activation as function of annealing time.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127349185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871221
M. Hioki, T. Endoh, H. Sakuraba, M. Lenski, F. Masuoka
The floating channel type surrounding gate transistor (FC-SGT) flash memory cell realizes high-speed bipolarity program and erase operations. In this investigation, the time dependence of the surface potential in the floating channel region, which strongly affects program and erase performance, is studied during program and erase operation. By analyzing the carrier generation processes in the floating channel region, the program and erase operation for FC-SGT flash memory cells is clarified.
{"title":"An analysis of program and erase operation for FC-SGT flash memory cells","authors":"M. Hioki, T. Endoh, H. Sakuraba, M. Lenski, F. Masuoka","doi":"10.1109/SISPAD.2000.871221","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871221","url":null,"abstract":"The floating channel type surrounding gate transistor (FC-SGT) flash memory cell realizes high-speed bipolarity program and erase operations. In this investigation, the time dependence of the surface potential in the floating channel region, which strongly affects program and erase performance, is studied during program and erase operation. By analyzing the carrier generation processes in the floating channel region, the program and erase operation for FC-SGT flash memory cells is clarified.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134011498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871197
J. Bude
Physically-based full band Monte-Carlo simulations are compared with drift-diffusion simulations for channel lengths from 150 nm to 40 nm. Errors in the drift diffusion simulated I/sub ON/, g/sub m/ and channel velocities are quantified through comparison with Monte-Carlo simulations under realistic surface scattering conditions. Suggestions for improving the drift-diffusion results are also discussed.
{"title":"MOSFET modeling into the ballistic regime","authors":"J. Bude","doi":"10.1109/SISPAD.2000.871197","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871197","url":null,"abstract":"Physically-based full band Monte-Carlo simulations are compared with drift-diffusion simulations for channel lengths from 150 nm to 40 nm. Errors in the drift diffusion simulated I/sub ON/, g/sub m/ and channel velocities are quantified through comparison with Monte-Carlo simulations under realistic surface scattering conditions. Suggestions for improving the drift-diffusion results are also discussed.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132784680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871212
R. Iverson, Y. Le Coz, B. Kleveland, S.S. Wong
We have developed and demonstrated a 3D multi-scale thermal-analysis methodology for multiple and stacked-chip configurations. This approach employs a global-local problem-domain discretization in conjunction with the floating RW (random walk) method. Emphasis has been placed on capturing complex thermal effects due to interconnect layers. We have analyzed a hypothetical stacked-chip geometry derived from a Stanford interconnect test chip. 2D gdsII layout data was automatically processed and converted into a 3D problem domain. On a 400 MHz Apple PowerBook G3/sup TM/, execution time was about three minutes per temperature data point. Temperature at each evaluated point was computed with 1000 RWs, yielding a 1-/spl sigma/ statistical error of about 5%. Based on heuristic formulas that we have deduced, a local window of /spl plusmn/20 /spl mu/m relative to the RW start point achieved a reasonable global-local discretization error.
{"title":"A multi-scale random-walk thermal-analysis methodology for complex IC-interconnect systems","authors":"R. Iverson, Y. Le Coz, B. Kleveland, S.S. Wong","doi":"10.1109/SISPAD.2000.871212","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871212","url":null,"abstract":"We have developed and demonstrated a 3D multi-scale thermal-analysis methodology for multiple and stacked-chip configurations. This approach employs a global-local problem-domain discretization in conjunction with the floating RW (random walk) method. Emphasis has been placed on capturing complex thermal effects due to interconnect layers. We have analyzed a hypothetical stacked-chip geometry derived from a Stanford interconnect test chip. 2D gdsII layout data was automatically processed and converted into a 3D problem domain. On a 400 MHz Apple PowerBook G3/sup TM/, execution time was about three minutes per temperature data point. Temperature at each evaluated point was computed with 1000 RWs, yielding a 1-/spl sigma/ statistical error of about 5%. Based on heuristic formulas that we have deduced, a local window of /spl plusmn/20 /spl mu/m relative to the RW start point achieved a reasonable global-local discretization error.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115629749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871255
R. Thalhammer, F. Hille, G. Wachutka
The carrier distribution in the interior of power devices can be determined from free carrier absorption measurements. In this work, a physically rigorous simulation of the entire measurement process is performed to investigate the effects which arise from the wave propagation of the probing beam and the sample preparation. Quantitative results for optimization of the optical set-up and the sample geometries which minimize the unavoidable experimental errors are presented.
{"title":"Optimizing free carrier absorption measurements for power devices by physically rigorous simulation","authors":"R. Thalhammer, F. Hille, G. Wachutka","doi":"10.1109/SISPAD.2000.871255","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871255","url":null,"abstract":"The carrier distribution in the interior of power devices can be determined from free carrier absorption measurements. In this work, a physically rigorous simulation of the entire measurement process is performed to investigate the effects which arise from the wave propagation of the probing beam and the sample preparation. Quantitative results for optimization of the optical set-up and the sample geometries which minimize the unavoidable experimental errors are presented.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115040141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871259
Y. Tosaka, S. Satoh
Although it has been shown that cosmic ray neutrons play an important role in soft error (SE) phenomena, some important issues in neutron-induced SE phenomena are still to be clarified. In this paper, neutron-induced multiple-bit SEs in 16 Mb DRAMs are investigated numerically using the Neutron-Induced Soft Error Simulator (NISES), and simulated results are compared to experimental data. Scaling effects on multiple-bit SEs, effects of configuration patterns on double-bit SE rates, and the influence of multiple-bit SEs on an error correction code are discussed.
{"title":"Simulation of multiple-bit soft errors induced by cosmic ray neutrons in DRAMs","authors":"Y. Tosaka, S. Satoh","doi":"10.1109/SISPAD.2000.871259","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871259","url":null,"abstract":"Although it has been shown that cosmic ray neutrons play an important role in soft error (SE) phenomena, some important issues in neutron-induced SE phenomena are still to be clarified. In this paper, neutron-induced multiple-bit SEs in 16 Mb DRAMs are investigated numerically using the Neutron-Induced Soft Error Simulator (NISES), and simulated results are compared to experimental data. Scaling effects on multiple-bit SEs, effects of configuration patterns on double-bit SE rates, and the influence of multiple-bit SEs on an error correction code are discussed.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125074547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871198
F.M. Bufler, A. Schenk, W. Fichtner
A single-particle approach to Monte Carlo device simulation is presented where the simulation is stopped when the error for the drain, substrate or gate current is below a predefined error bar. This is achieved by alternating an ensemble simulation in the contact elements, used for the injection of a carrier, with a single-particle simulation in the active device area, thus enabling stochastically independent current estimates. Together with efficient Monte Carlo techniques, leading to CPU times of typically one hour per bias point, this makes full-band Monte Carlo "affordable" for the simulation of submicron MOSFETs.
{"title":"Efficient Monte Carlo device simulation with automatic error control","authors":"F.M. Bufler, A. Schenk, W. Fichtner","doi":"10.1109/SISPAD.2000.871198","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871198","url":null,"abstract":"A single-particle approach to Monte Carlo device simulation is presented where the simulation is stopped when the error for the drain, substrate or gate current is below a predefined error bar. This is achieved by alternating an ensemble simulation in the contact elements, used for the injection of a carrier, with a single-particle simulation in the active device area, thus enabling stochastically independent current estimates. Together with efficient Monte Carlo techniques, leading to CPU times of typically one hour per bias point, this makes full-band Monte Carlo \"affordable\" for the simulation of submicron MOSFETs.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126266394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871202
C. Jungemann, B. Neinhus, B. Meinerzhagen
Transit times and cut-off frequency of a silicon/germanium heterojunction bipolar transistor (SiGe HBT) are investigated by consistent drift-diffusion (DD), hydrodynamic (HD), and full-band Monte Carlo (FB-MC) simulations. Good agreement of all three transport models is found for the collector transit time. The quasiballistic transport in the base is well described by the HD model and yields the same transit time as the FB-MC model, whereas the DD model yields a much larger transit time, because it does not include any velocity overshoot effects. Surprisingly, in the emitter region, the FB-MC model yields the largest transit time, leading to a peak cut-off frequency for the special device structure under investigation which is even smaller than the DD peak value. The strong anisotropy of the strained band structure in the base, which is not captured in full detail by the DD and HD models, is identified as a possible reason for this unexpected behavior.
{"title":"Spatial analysis of the electron transit time in a silicon/germanium heterojunction bipolar transistor by drift-diffusion, hydrodynamic, and full-band Monte Carlo device simulation","authors":"C. Jungemann, B. Neinhus, B. Meinerzhagen","doi":"10.1109/SISPAD.2000.871202","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871202","url":null,"abstract":"Transit times and cut-off frequency of a silicon/germanium heterojunction bipolar transistor (SiGe HBT) are investigated by consistent drift-diffusion (DD), hydrodynamic (HD), and full-band Monte Carlo (FB-MC) simulations. Good agreement of all three transport models is found for the collector transit time. The quasiballistic transport in the base is well described by the HD model and yields the same transit time as the FB-MC model, whereas the DD model yields a much larger transit time, because it does not include any velocity overshoot effects. Surprisingly, in the emitter region, the FB-MC model yields the largest transit time, leading to a peak cut-off frequency for the special device structure under investigation which is even smaller than the DD peak value. The strong anisotropy of the strained band structure in the base, which is not captured in full detail by the DD and HD models, is identified as a possible reason for this unexpected behavior.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114158688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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