Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871227
N. Kusunoki, T. Shimizu, H. Hazama, N. Aoki
We proposed a novel model to enable accurate and practical simulations for a growth of oxynitride film on a Si substrate. In the growth of the oxynitride film, oxidation of the Si surface and the incorporation of nitrogen atoms in the oxynitride film occur simultaneously. Due to the nitrogen atoms in the oxynitride film, the growth rate of the oxynitride film is quite different from that of SiO/sub 2/ film. We extended an oxidant diffusion model that depends on the nitrogen concentration in the oxynitride film. In this model, the oxidant diffusivity is a function of the nitrogen concentration. We apply the model to the simulations of several oxynitride processes and re-oxidation of the oxynitride films. The simulation results show good agreement with experimental results.
{"title":"A novel simulation method for oxynitridation and re-oxidation","authors":"N. Kusunoki, T. Shimizu, H. Hazama, N. Aoki","doi":"10.1109/SISPAD.2000.871227","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871227","url":null,"abstract":"We proposed a novel model to enable accurate and practical simulations for a growth of oxynitride film on a Si substrate. In the growth of the oxynitride film, oxidation of the Si surface and the incorporation of nitrogen atoms in the oxynitride film occur simultaneously. Due to the nitrogen atoms in the oxynitride film, the growth rate of the oxynitride film is quite different from that of SiO/sub 2/ film. We extended an oxidant diffusion model that depends on the nitrogen concentration in the oxynitride film. In this model, the oxidant diffusivity is a function of the nitrogen concentration. We apply the model to the simulations of several oxynitride processes and re-oxidation of the oxynitride films. The simulation results show good agreement with experimental results.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122115553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871224
Won-young Chung, Jae-joon Oh, Tai-kyung Kim, J. Shin, K. Seo, Young-Kwan Park, J. Kong
An integrated procedure including the plasma equipment and profile modeling is developed and applied to the contact etching process for the DRM (dipole ring magnet) reactor. In this simulation scheme, the static magnetic field solver, HPEM (hybrid plasma equipment model) and the topography simulator based on the level-set algorithm are used one by one to reproduce etch rates and profiles in terms of the equipment operating parameters such as the gas composition ratio and power. We investigated the contact etching of SiO/sub 2/ and Si/sub 3/N/sub 4/ in the DRM plasma reactor with CHF/sub 3/-CO-O/sub 2/ gas mixture. In terms of etch rates at the wafer center, the results show agreement with experimental values with less than 6% errors. The uniformities of the etch rate and contact profile also agree with those of experiments. These agreements show the possibility of the systematic simulation method in developing and optimizing a dry etching process.
{"title":"Integrated simulation of equipment and topography for plasma etching in the DRM reactor","authors":"Won-young Chung, Jae-joon Oh, Tai-kyung Kim, J. Shin, K. Seo, Young-Kwan Park, J. Kong","doi":"10.1109/SISPAD.2000.871224","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871224","url":null,"abstract":"An integrated procedure including the plasma equipment and profile modeling is developed and applied to the contact etching process for the DRM (dipole ring magnet) reactor. In this simulation scheme, the static magnetic field solver, HPEM (hybrid plasma equipment model) and the topography simulator based on the level-set algorithm are used one by one to reproduce etch rates and profiles in terms of the equipment operating parameters such as the gas composition ratio and power. We investigated the contact etching of SiO/sub 2/ and Si/sub 3/N/sub 4/ in the DRM plasma reactor with CHF/sub 3/-CO-O/sub 2/ gas mixture. In terms of etch rates at the wafer center, the results show agreement with experimental values with less than 6% errors. The uniformities of the etch rate and contact profile also agree with those of experiments. These agreements show the possibility of the systematic simulation method in developing and optimizing a dry etching process.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"1953 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871254
V. Palankovski, S. Selberherr, R. Quay, R. Schultheis
We present two-dimensional simulations of one-finger power InGaP-GaAs heterojunction bipolar transistors (HBTs) before and after both electrical and thermal stress aging. It is well known that GaAs-HBTs with InGaP emitter material can be improved in terms of reliability if the emitter material covers the complete p-doped base layer forming the so-called InGaP ledge outside the active emitter. We analyze the influence of the ledge thickness and of the surface charges on the device performance and its impact on reliability. The possibility of explaining device degradation mechanisms by means of numerical simulation is of high practical importance.
{"title":"Analysis of HBT behavior after strong electrothermal stress","authors":"V. Palankovski, S. Selberherr, R. Quay, R. Schultheis","doi":"10.1109/SISPAD.2000.871254","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871254","url":null,"abstract":"We present two-dimensional simulations of one-finger power InGaP-GaAs heterojunction bipolar transistors (HBTs) before and after both electrical and thermal stress aging. It is well known that GaAs-HBTs with InGaP emitter material can be improved in terms of reliability if the emitter material covers the complete p-doped base layer forming the so-called InGaP ledge outside the active emitter. We analyze the influence of the ledge thickness and of the surface charges on the device performance and its impact on reliability. The possibility of explaining device degradation mechanisms by means of numerical simulation is of high practical importance.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132405977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871251
K. Matsuzawa, N. Sano, K. Natori, M. Mukai, N. Nakayama
Current fluctuation at an actual contact was studied using the Monte Carlo method. The metal/semiconductor interface was treated as the Schottky contact, because the interface inevitably becomes the Schottky contact. Simulations were carried out for n/sup +/n structures to investigate asymmetry of current fluctuation at both contacts. It was found that the current fluctuation at each contact depended on bias, impurity concentration around the contact, length of contact region, and the Schottky barrier height.
{"title":"Monte Carlo simulation of current fluctuation at actual contact","authors":"K. Matsuzawa, N. Sano, K. Natori, M. Mukai, N. Nakayama","doi":"10.1109/SISPAD.2000.871251","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871251","url":null,"abstract":"Current fluctuation at an actual contact was studied using the Monte Carlo method. The metal/semiconductor interface was treated as the Schottky contact, because the interface inevitably becomes the Schottky contact. Simulations were carried out for n/sup +/n structures to investigate asymmetry of current fluctuation at both contacts. It was found that the current fluctuation at each contact depended on bias, impurity concentration around the contact, length of contact region, and the Schottky barrier height.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871216
Sukin Yoon, O. Kwon, S. Yoon, T. Won
This paper reports a methodology and its application for extracting the capacitance of a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitance in a stacked DRAM cell, we employed the finite element method (FEM), and to generate a complicated three-dimensional mesh structure, we used a graphic user interface, a topography simulator and three dimensional grid generator. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 /spl mu/m was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance values with 4 cell capacitance values were extracted from a stacked DRAM cell structure.
{"title":"An extracting capacitance in a stacked DRAM cell by numerical method","authors":"Sukin Yoon, O. Kwon, S. Yoon, T. Won","doi":"10.1109/SISPAD.2000.871216","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871216","url":null,"abstract":"This paper reports a methodology and its application for extracting the capacitance of a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitance in a stacked DRAM cell, we employed the finite element method (FEM), and to generate a complicated three-dimensional mesh structure, we used a graphic user interface, a topography simulator and three dimensional grid generator. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 /spl mu/m was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance values with 4 cell capacitance values were extracted from a stacked DRAM cell structure.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SISPAD.2000.871209
Xin Wang, D. Kencke, K.C. Liu, A. Tasch, L. Register, S. Banerjee
We report for the first time on the electron transport properties of simple orthorhombically-strained silicon studied by density-functional theory and Monte Carlo simulation. The six degenerate valleys near X points in bulk silicon break into three pairs with different energy minima due to the orthorhombic strain. The degeneracy lifting causes electron redistribution among these valleys at low and intermediate electric fields. Thus the drift velocity is enhanced under an electric field transverse to the long-axis of the lowest valleys. The simple orthorhombically-strained Si grown on a Si-Si/sub 0.6/Ge/sub 0.4/ sidewall has a low-field mobility almost twice that of bulk Si and an electron saturation velocity approximately 20% higher.
{"title":"Electron transport properties in novel orthorhombically-strained silicon material explored by the Monte Carlo method","authors":"Xin Wang, D. Kencke, K.C. Liu, A. Tasch, L. Register, S. Banerjee","doi":"10.1109/SISPAD.2000.871209","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871209","url":null,"abstract":"We report for the first time on the electron transport properties of simple orthorhombically-strained silicon studied by density-functional theory and Monte Carlo simulation. The six degenerate valleys near X points in bulk silicon break into three pairs with different energy minima due to the orthorhombic strain. The degeneracy lifting causes electron redistribution among these valleys at low and intermediate electric fields. Thus the drift velocity is enhanced under an electric field transverse to the long-axis of the lowest valleys. The simple orthorhombically-strained Si grown on a Si-Si/sub 0.6/Ge/sub 0.4/ sidewall has a low-field mobility almost twice that of bulk Si and an electron saturation velocity approximately 20% higher.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SISPAD.2000.871257
K. Eikyu, H. Takashino, M. Kidera, A. Teramoto, H. Umeda, K. Ishikawa, N. Kotani, M. Inuishi
The physical oxide thickness of ultrathin oxides is extracted using the tunneling current characteristics of MOS capacitors. An extraction tool has been developed for the semiautomatic extraction. The tool implements a nonlinear least square solver and GUIs. A tunneling current model is incorporated into the MIDSIP-T device simulator and it is used as a core simulator of the extraction system. It is found that the transition layer should be considered in the extraction of very thin oxide thickness below 4 nm. A unified parameter set, /spl phi//sub b/=3.3 eV and m/sub c//sup *//m/sub 0/=0.41, is obtained after the extraction of various samples.
{"title":"Extraction of the physical oxide thickness using the electrical characteristics of MOS capacitors","authors":"K. Eikyu, H. Takashino, M. Kidera, A. Teramoto, H. Umeda, K. Ishikawa, N. Kotani, M. Inuishi","doi":"10.1109/SISPAD.2000.871257","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871257","url":null,"abstract":"The physical oxide thickness of ultrathin oxides is extracted using the tunneling current characteristics of MOS capacitors. An extraction tool has been developed for the semiautomatic extraction. The tool implements a nonlinear least square solver and GUIs. A tunneling current model is incorporated into the MIDSIP-T device simulator and it is used as a core simulator of the extraction system. It is found that the transition layer should be considered in the extraction of very thin oxide thickness below 4 nm. A unified parameter set, /spl phi//sub b/=3.3 eV and m/sub c//sup *//m/sub 0/=0.41, is obtained after the extraction of various samples.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117216046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SISPAD.2000.871230
Q. Ouyang, X.D. Chen, S. Mudanai, D. Kencke, X. Wang, A. Tasch, L. Register, S. Banerjee
Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction pMOSFETs with strained SiGe in the source and/or drain have substantially suppressed short-channel effects, including field-induced barrier lowering in the devices with high-k gate dielectrics/spacers. Despite the source-side velocity overshoot, the drive currents in these devices are reduced due to the hetero-barriers in the channel. This drawback can be eliminated by the use of a thin Si or SiGe cap layer. Finally, a novel pMOSFET with a SiGe source/drain and a SiGe quantum well channel is proposed. It has reduced SCE and enhanced drive current.
{"title":"Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability","authors":"Q. Ouyang, X.D. Chen, S. Mudanai, D. Kencke, X. Wang, A. Tasch, L. Register, S. Banerjee","doi":"10.1109/SISPAD.2000.871230","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871230","url":null,"abstract":"Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction pMOSFETs with strained SiGe in the source and/or drain have substantially suppressed short-channel effects, including field-induced barrier lowering in the devices with high-k gate dielectrics/spacers. Despite the source-side velocity overshoot, the drive currents in these devices are reduced due to the hetero-barriers in the channel. This drawback can be eliminated by the use of a thin Si or SiGe cap layer. Finally, a novel pMOSFET with a SiGe source/drain and a SiGe quantum well channel is proposed. It has reduced SCE and enhanced drive current.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114442382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SISPAD.2000.871226
A. Asenov, S. Kaya
In this paper we use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the quantum mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples.
{"title":"Effect of oxide interface roughness on the threshold voltage fluctuations in decanano MOSFETs with ultrathin gate oxides","authors":"A. Asenov, S. Kaya","doi":"10.1109/SISPAD.2000.871226","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871226","url":null,"abstract":"In this paper we use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the quantum mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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