Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871248
C. Pladdy, I. Avci, M. Law
This paper presents a method for optimum placement of nodes in grid generation for process simulation together with an algorithm for updating the grid after each addition of a new node to ensure that the Delaunay property is satisfied. Placement of nodes is decided by considering the optimum error in evaluating the integral /spl int//sub V/ C(x)dx. The best error estimate is obtained when the node coincides with the centroid (the center of mass) of its own Voronoi region and moreover when the Voronoi region is symmetric. After addition of a node, the grid is updated to maintain the Delaunay property using the Delaunay-Voronoi algorithm.
{"title":"Optimum node positioning in adaptive grid refinement and the Delaunay-Voronoi algorithm [semiconductor process simulation]","authors":"C. Pladdy, I. Avci, M. Law","doi":"10.1109/SISPAD.2000.871248","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871248","url":null,"abstract":"This paper presents a method for optimum placement of nodes in grid generation for process simulation together with an algorithm for updating the grid after each addition of a new node to ensure that the Delaunay property is satisfied. Placement of nodes is decided by considering the optimum error in evaluating the integral /spl int//sub V/ C(x)dx. The best error estimate is obtained when the node coincides with the centroid (the center of mass) of its own Voronoi region and moreover when the Voronoi region is symmetric. After addition of a node, the grid is updated to maintain the Delaunay property using the Delaunay-Voronoi algorithm.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134340712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871200
T. Ezaki, H. Nakasato, T. Yamamoto, M. Hane
We have investigated the relationship between the currents of hot holes injected into silicon dioxides and the time to breakdown (T/sub BD/) characteristics. The hot hole currents were calculated by combining a tunnel current simulator and a silicon full-band Monte Carlo (FBMC) simulator. Our results show that the hot hole current seems to be responsible for oxide degradation and breakdown. Moreover, the additional impact ionization process where electrons are relaxed into the valence bands plays an important role in hot hole generation in the low-gate-voltage region.
{"title":"Simulation of hot hole currents in ultra-thin silicon dioxides: the relationship between time to breakdown and hot hole currents","authors":"T. Ezaki, H. Nakasato, T. Yamamoto, M. Hane","doi":"10.1109/SISPAD.2000.871200","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871200","url":null,"abstract":"We have investigated the relationship between the currents of hot holes injected into silicon dioxides and the time to breakdown (T/sub BD/) characteristics. The hot hole currents were calculated by combining a tunnel current simulator and a silicon full-band Monte Carlo (FBMC) simulator. Our results show that the hot hole current seems to be responsible for oxide degradation and breakdown. Moreover, the additional impact ionization process where electrons are relaxed into the valence bands plays an important role in hot hole generation in the low-gate-voltage region.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132654318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871239
A. Abramo, L. Selmi, Z. Yu, R. Dutton
This paper presents the two-dimensional quantum mechanical simulation of scaled "well-tempered MOSFETs" (Assad et al, IEDM Tech. Dig., p. 547, 1999, and IEEE trans. Electron Dev. vol. 47, p. 232, 2000) featuring different effective channel lengths in the deep sub-micron range. The simulation results were obtained by means of a two-dimensional Schrodinger solver that had been previously applied to idealized MOS structures. Comparison between one- and two dimensional approaches is presented, and the difference between the two models are highlighted.
本文介绍了缩放“良调质mosfet”的二维量子力学模拟(阿萨德等人，IEDM Tech. Dig)。， p. 547, 1999, and IEEE trans。电子发展，vol. 47, p. 232, 2000)在深亚微米范围内具有不同的有效通道长度。模拟结果是通过二维薛定谔求解器得到的，该方法已经应用于理想的MOS结构。给出了一维和二维方法的比较，并强调了两种模型之间的差异。
{"title":"Well-tempered MOSFETs: 1D versus 2D quantum analysis","authors":"A. Abramo, L. Selmi, Z. Yu, R. Dutton","doi":"10.1109/SISPAD.2000.871239","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871239","url":null,"abstract":"This paper presents the two-dimensional quantum mechanical simulation of scaled \"well-tempered MOSFETs\" (Assad et al, IEDM Tech. Dig., p. 547, 1999, and IEEE trans. Electron Dev. vol. 47, p. 232, 2000) featuring different effective channel lengths in the deep sub-micron range. The simulation results were obtained by means of a two-dimensional Schrodinger solver that had been previously applied to idealized MOS structures. Comparison between one- and two dimensional approaches is presented, and the difference between the two models are highlighted.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125071026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871217
Jin-Kyu Park, Keun-Ho Lee, Joo-Hee Lee, Young-Kwan Park, J. Kong
This paper presents an exhaustive method to characterize the interconnect capacitances while taking the floating dummy-fills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-difference solver and its computational efficiency is compared with the industry-standard RAPHAEL. Furthermore, the overall flow for extracting the parasitic capacitance considering the dummy-fills at the full-chip level is discussed and the underlying assumption is examined.
{"title":"An exhaustive method for characterizing the interconnect capacitance considering the floating dummy-fills by employing an efficient field solving algorithm","authors":"Jin-Kyu Park, Keun-Ho Lee, Joo-Hee Lee, Young-Kwan Park, J. Kong","doi":"10.1109/SISPAD.2000.871217","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871217","url":null,"abstract":"This paper presents an exhaustive method to characterize the interconnect capacitances while taking the floating dummy-fills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-difference solver and its computational efficiency is compared with the industry-standard RAPHAEL. Furthermore, the overall flow for extracting the parasitic capacitance considering the dummy-fills at the full-chip level is discussed and the underlying assumption is examined.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114816188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871260
J. Goo, Kwang-Hoon Oh, Chang-hoon Choi, Zhiping Yu, Thomas H. Lee, Robert W. Dutton
The first stage of a receiver is typically an LNA (low noise amplifier) which must provide sufficient gain while introducing as little noise as possible. Recently proposed noise optimization techniques for CMOS RF circuits permit greater flexibility in selection of device geometries as well as matching elements and biasing conditions to minimize the noise figure for a specified gain or power dissipation (Shaeffer and Lee, 1997). Nevertheless, such approaches still have ambiguity because intrinsic noise is assumed to be bias-independent. To utilize the new degrees of freedom in noise figure optimization, more complete intrinsic noise information on MOSFETs across the entire bias range is needed. A recent study has reported extensive experimental noise results of the 0.75 /spl mu/m SOI MOSFET technology (Dambrine et al, 1999) but provided limited guidance for actual LNA design. A physical noise simulator has been developed using two-dimensional device simulation; successful noise simulation results have been reported for MOSFETs with channel lengths down to 0.25 /spl mu/m for the first time (Goo et al, Proc. Symp. VLSI Tech., p. 153, 1999). Based on intrinsic high frequency noise simulation results, this paper presents explicit design guidelines for a CMOS tuned LNA with power constraints.
接收器的第一级通常是LNA(低噪声放大器)，它必须提供足够的增益，同时引入尽可能少的噪声。最近提出的CMOS射频电路的噪声优化技术允许更大的灵活性选择器件几何形状，以及匹配元件和偏置条件，以最小化指定增益或功耗的噪声系数(Shaeffer和Lee, 1997)。然而，这种方法仍然具有模糊性，因为固有噪声被认为是与偏差无关的。为了在噪声系数优化中利用新的自由度，需要在整个偏置范围内对mosfet进行更完整的固有噪声信息。最近的一项研究报道了0.75 /spl mu/m SOI MOSFET技术的大量实验噪声结果(Dambrine et al .， 1999)，但对实际LNA设计提供的指导有限。利用二维器件仿真技术开发了物理噪声模拟器;首次报道了沟道长度降至0.25 /spl mu/m的mosfet的成功噪声模拟结果(Goo et al .， Proc. Symp.)。VLSI Tech, p. 153, 1999)。基于固有高频噪声仿真结果，给出了具有功率约束的CMOS调谐LNA的明确设计准则。
{"title":"Guidelines for the power constrained design of a CMOS tuned LNA","authors":"J. Goo, Kwang-Hoon Oh, Chang-hoon Choi, Zhiping Yu, Thomas H. Lee, Robert W. Dutton","doi":"10.1109/SISPAD.2000.871260","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871260","url":null,"abstract":"The first stage of a receiver is typically an LNA (low noise amplifier) which must provide sufficient gain while introducing as little noise as possible. Recently proposed noise optimization techniques for CMOS RF circuits permit greater flexibility in selection of device geometries as well as matching elements and biasing conditions to minimize the noise figure for a specified gain or power dissipation (Shaeffer and Lee, 1997). Nevertheless, such approaches still have ambiguity because intrinsic noise is assumed to be bias-independent. To utilize the new degrees of freedom in noise figure optimization, more complete intrinsic noise information on MOSFETs across the entire bias range is needed. A recent study has reported extensive experimental noise results of the 0.75 /spl mu/m SOI MOSFET technology (Dambrine et al, 1999) but provided limited guidance for actual LNA design. A physical noise simulator has been developed using two-dimensional device simulation; successful noise simulation results have been reported for MOSFETs with channel lengths down to 0.25 /spl mu/m for the first time (Goo et al, Proc. Symp. VLSI Tech., p. 153, 1999). Based on intrinsic high frequency noise simulation results, this paper presents explicit design guidelines for a CMOS tuned LNA with power constraints.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126838121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871234
S. Chakravarthi, S. Dunham
Boron transient enhanced diffusion (TED) is characterized by enhanced tail diffusion coupled with an electrically inactive immobile peak associated with the clustering of boron in the presence of excess interstitials. A consistent model for process simulation has to account for the formation of a variety of agglomerates associated with the excess point defect concentrations following ion implantation. These include interstitial clusters (e.g. {311} defects), vacancy clusters and dopant/interstitial clusters (e.g. boron interstitial clusters). In addition to the chemical profiles (SIMS), it is essential to also predict electrical activation behavior. Hence, in this work we investigate models for boron deactivation and subsequent activation during annealing.
{"title":"Modeling of boron deactivation/activation kinetics during ion implant annealing","authors":"S. Chakravarthi, S. Dunham","doi":"10.1109/SISPAD.2000.871234","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871234","url":null,"abstract":"Boron transient enhanced diffusion (TED) is characterized by enhanced tail diffusion coupled with an electrically inactive immobile peak associated with the clustering of boron in the presence of excess interstitials. A consistent model for process simulation has to account for the formation of a variety of agglomerates associated with the excess point defect concentrations following ion implantation. These include interstitial clusters (e.g. {311} defects), vacancy clusters and dopant/interstitial clusters (e.g. boron interstitial clusters). In addition to the chemical profiles (SIMS), it is essential to also predict electrical activation behavior. Hence, in this work we investigate models for boron deactivation and subsequent activation during annealing.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871262
P. Moens, M. Tack, H. Van Hove, M. Vermandel, D. Bolognesi
A new medium voltage (40-60 V) pDMOS device has been developed and optimized through the use of a design of experiment (DOE) approach based on TCAD simulations and experimental verification. Layout parameters are varied and the electrical characteristics of the device (e.g. V/sub bd/, specific on-resistance, etc.) together with hot carrier behaviour, are studied as responses. In this way, an optimal device was selected.
{"title":"Development of an optimised 40 V pDMOS device by use of a TCAD design of experiment methodology","authors":"P. Moens, M. Tack, H. Van Hove, M. Vermandel, D. Bolognesi","doi":"10.1109/SISPAD.2000.871262","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871262","url":null,"abstract":"A new medium voltage (40-60 V) pDMOS device has been developed and optimized through the use of a design of experiment (DOE) approach based on TCAD simulations and experimental verification. Layout parameters are varied and the electrical characteristics of the device (e.g. V/sub bd/, specific on-resistance, etc.) together with hot carrier behaviour, are studied as responses. In this way, an optimal device was selected.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127675417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871245
I. Avci, H. Rueda, M. E. Law
A single statistical point defect based model for the evolution of dislocation loops during oxidation and annealing under an inert ambient is developed. The model assumes that the radius and the density of the dislocation loops follow a log normal distribution. The capture or emission rate of interstitials bounded by the dislocation is proportional to the rates of emission and absorption of point defects at the loop boundaries modulated by a log normal loop distribution function. The model also incorporates the stress due to dislocation loops. Published data on loop evolution and distribution under oxidation and inert ambient annealing conditions are used to calibrate the loop model.
{"title":"Model for the evolution of dislocation loops in silicon","authors":"I. Avci, H. Rueda, M. E. Law","doi":"10.1109/SISPAD.2000.871245","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871245","url":null,"abstract":"A single statistical point defect based model for the evolution of dislocation loops during oxidation and annealing under an inert ambient is developed. The model assumes that the radius and the density of the dislocation loops follow a log normal distribution. The capture or emission rate of interstitials bounded by the dislocation is proportional to the rates of emission and absorption of point defects at the loop boundaries modulated by a log normal loop distribution function. The model also incorporates the stress due to dislocation loops. Published data on loop evolution and distribution under oxidation and inert ambient annealing conditions are used to calibrate the loop model.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130978268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871244
K. Rajendran, W. Schoenmaker, S. Decoutere, M. Caymax
This paper describes a simple and accurate model for boron diffusion in SiGe that was successfully implemented in TAURUS (PMEI). The comparison of the Si/sub 1-x/Ge/sub x/ samples to Si samples after rapid thermal and furnace annealing revealed a retarded B diffusion inside the strained Si/sub 1-x/Ge/sub x/ layers. The influence of the Ge content on the dopant diffusion was also measured and simulated, demonstrating that the B diffusion was found to decrease with the Ge alloy content. The model fits for various Ge percentages (both box and graded profiles) and thermal budgets. The simulation results of various Ge percentages and thermal budgets show good agreement with measurement data and the predicted B diffusivity show a reasonably low value.
{"title":"Simulation of boron diffusion in strained Si/sub 1-x/Ge/sub x/ epitaxial layers","authors":"K. Rajendran, W. Schoenmaker, S. Decoutere, M. Caymax","doi":"10.1109/SISPAD.2000.871244","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871244","url":null,"abstract":"This paper describes a simple and accurate model for boron diffusion in SiGe that was successfully implemented in TAURUS (PMEI). The comparison of the Si/sub 1-x/Ge/sub x/ samples to Si samples after rapid thermal and furnace annealing revealed a retarded B diffusion inside the strained Si/sub 1-x/Ge/sub x/ layers. The influence of the Ge content on the dopant diffusion was also measured and simulated, demonstrating that the B diffusion was found to decrease with the Ge alloy content. The model fits for various Ge percentages (both box and graded profiles) and thermal budgets. The simulation results of various Ge percentages and thermal budgets show good agreement with measurement data and the predicted B diffusivity show a reasonably low value.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126034652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-06DOI: 10.1109/SISPAD.2000.871218
T. Ohta, M. Fujinaga, M. Kimura, T. Wada, K. Nishi
We have developed a total interconnect simulation system including a CMP model. The capacitance variation due to pattern width difference from focus effects on a globally nonuniform surface by CMP is simulated with this system. The paper also shows a way to reduce the capacitance variation due to CMP processes derived from these simulations.
{"title":"A simulation system for capacitance variation by CMP process including defocus effect","authors":"T. Ohta, M. Fujinaga, M. Kimura, T. Wada, K. Nishi","doi":"10.1109/SISPAD.2000.871218","DOIUrl":"https://doi.org/10.1109/SISPAD.2000.871218","url":null,"abstract":"We have developed a total interconnect simulation system including a CMP model. The capacitance variation due to pattern width difference from focus effects on a globally nonuniform surface by CMP is simulated with this system. The paper also shows a way to reduce the capacitance variation due to CMP processes derived from these simulations.","PeriodicalId":132609,"journal":{"name":"2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126227948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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