Hybrid computing-in-memory (CIM) has recently gained significant attention due to its ability to leverage the strengths of both digital CIM (DCIM) and analog CIM (ACIM). The multibit fusion (MF) scheme enhances energy efficiency by fusing low-bit results, which typically require multiple read-out cycles, into a single-cycle read out. However, the relationship between hybrid INT-CIM circuit design and network performance based on the MF scheme has not yet been systematically explored. In addition, we investigate how different MF configurations affect the performance of various neural networks. To address this gap, we first propose a less-significant group quantization (LSGQ) model, which defines and explores the design space of hybrid INT-CIM. Second, we develop a FastFuse-Search (FFS) algorithm, which optimizes configurations for different networks to strike a better balance between model accuracy and energy efficiency. Based on the experimental results, some key considerations on hybrid CIM design are derived. FFS yields a $1.72times $ energy-efficiency boost with negligible accuracy loss. Finally, we fabricate a 28-nm hybrid INT-CIM test chip, achieving 59.74 TOPS/W and 0.96 TOPS/mm2, with performance metrics of 23.21 perplexity for GPT-2, 68.69% accuracy for ResNet18, and 80.53% accuracy for ViT.
{"title":"An LSGQ-FFS Framework for Adaptive Optimization of Hybrid INT-CIM Architecture","authors":"Shaochen Li;Xi Chen;Yujia Xiong;Yuhan Liu;Lingyi Kong;He Wang;Tianhui Jiao;Xing Wang;Xiaomin Li;Yan Yan;Yuchen Ma;Xin Si","doi":"10.1109/TVLSI.2025.3627654","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3627654","url":null,"abstract":"Hybrid computing-in-memory (CIM) has recently gained significant attention due to its ability to leverage the strengths of both digital CIM (DCIM) and analog CIM (ACIM). The multibit fusion (MF) scheme enhances energy efficiency by fusing low-bit results, which typically require multiple read-out cycles, into a single-cycle read out. However, the relationship between hybrid INT-CIM circuit design and network performance based on the MF scheme has not yet been systematically explored. In addition, we investigate how different MF configurations affect the performance of various neural networks. To address this gap, we first propose a less-significant group quantization (LSGQ) model, which defines and explores the design space of hybrid INT-CIM. Second, we develop a FastFuse-Search (FFS) algorithm, which optimizes configurations for different networks to strike a better balance between model accuracy and energy efficiency. Based on the experimental results, some key considerations on hybrid CIM design are derived. FFS yields a <inline-formula> <tex-math>$1.72times $ </tex-math></inline-formula> energy-efficiency boost with negligible accuracy loss. Finally, we fabricate a 28-nm hybrid INT-CIM test chip, achieving 59.74 TOPS/W and 0.96 TOPS/mm<sup>2</sup>, with performance metrics of 23.21 perplexity for GPT-2, 68.69% accuracy for ResNet18, and 80.53% accuracy for ViT.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"677-681"},"PeriodicalIF":3.1,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1109/TVLSI.2025.3629045
Xu Fang;Xiaofeng Zhao
Through silicon via (TSV), serving as the vertical signal path in 3-D integrated circuits (3D-ICs), must be tested prior to die bonding (pre-bond). Most conventional pre-bond TSV test methods are often limited in terms of leakage fault detection range, hybrid fault detection capability, and fault parameter diagnosability. To address these challenges, we propose a pre-bond TSV test method based on ring oscillator (RO) circuits using a variable discharge path, capable of detecting and diagnosing a wide range of TSV faults, including open, leakage, and hybrid open-leakage faults with high resolution. The entire DfT framework employs standard digital cells to construct all test structures, facilitating its application in diverse testing scenarios. The effectiveness of the proposed method is evaluated through HSPICE simulations. The simulation results demonstrate that, in the presence of PVT variation, the proposed method can effectively detect and diagnose open faults occurring within the first 96.7% tail section of TSV with a maximum diagnosing error of 3.71 fF. Additionally, it can accurately identify leakage faults exceeding 2.5 nS with a maximum diagnosing error of 13.5%.
{"title":"A Wide Fault Coverage Pre-Bond TSV Test Method Based on Ring Oscillator Using Variable Discharge Path","authors":"Xu Fang;Xiaofeng Zhao","doi":"10.1109/TVLSI.2025.3629045","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3629045","url":null,"abstract":"Through silicon via (TSV), serving as the vertical signal path in 3-D integrated circuits (3D-ICs), must be tested prior to die bonding (pre-bond). Most conventional pre-bond TSV test methods are often limited in terms of leakage fault detection range, hybrid fault detection capability, and fault parameter diagnosability. To address these challenges, we propose a pre-bond TSV test method based on ring oscillator (RO) circuits using a variable discharge path, capable of detecting and diagnosing a wide range of TSV faults, including open, leakage, and hybrid open-leakage faults with high resolution. The entire DfT framework employs standard digital cells to construct all test structures, facilitating its application in diverse testing scenarios. The effectiveness of the proposed method is evaluated through HSPICE simulations. The simulation results demonstrate that, in the presence of PVT variation, the proposed method can effectively detect and diagnose open faults occurring within the first 96.7% tail section of TSV with a maximum diagnosing error of 3.71 fF. Additionally, it can accurately identify leakage faults exceeding 2.5 nS with a maximum diagnosing error of 13.5%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"648-661"},"PeriodicalIF":3.1,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1109/TVLSI.2025.3627560
Yu Lu;Pengfei Jiang;Qingsong Zhang;Tianyue Sun;Wenjun Gong;Yuxin Liao;Hao Min
This brief presents a reconfigurable multichannel noise-shaping (NS) SAR analog-to-digital converter (ADC) with crosstalk suppression. All nonmemory blocks are multiplexed among all channels assisted by the proposed timing control scheme, enabling reconfiguration with negligible power and hardware cost. A novel approach to determine the design parameters of nonideal loop filters is proposed, and a crosstalk suppressed multichannel fully passive loop filter is developed based on this method. A memoryless binary dynamic element matching (DEM) is also adopted to suppress the nonlinearity of each channel. The ADC achieves a typical SNDR of 77.49/72.17/66.62 dB with a 20-kHz bandwidth under one-/two-/four-channel modes, respectively, realizing typical Schreier FoMs of 169.54, 167.20, and 164.64 dB. Averaged interchannel crosstalks are −79.17 and −77.37 dB with −2.5-dBFS inputs in all input channels under two- and four-channel modes.
{"title":"A Crosstalk Suppressed Reconfigurable Fully Passive Multichannel Noise-Shaping SAR ADC","authors":"Yu Lu;Pengfei Jiang;Qingsong Zhang;Tianyue Sun;Wenjun Gong;Yuxin Liao;Hao Min","doi":"10.1109/TVLSI.2025.3627560","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3627560","url":null,"abstract":"This brief presents a reconfigurable multichannel noise-shaping (NS) SAR analog-to-digital converter (ADC) with crosstalk suppression. All nonmemory blocks are multiplexed among all channels assisted by the proposed timing control scheme, enabling reconfiguration with negligible power and hardware cost. A novel approach to determine the design parameters of nonideal loop filters is proposed, and a crosstalk suppressed multichannel fully passive loop filter is developed based on this method. A memoryless binary dynamic element matching (DEM) is also adopted to suppress the nonlinearity of each channel. The ADC achieves a typical SNDR of 77.49/72.17/66.62 dB with a 20-kHz bandwidth under one-/two-/four-channel modes, respectively, realizing typical Schreier FoMs of 169.54, 167.20, and 164.64 dB. Averaged interchannel crosstalks are −79.17 and −77.37 dB with −2.5-dBFS inputs in all input channels under two- and four-channel modes.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"682-686"},"PeriodicalIF":3.1,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TVLSI.2025.3627973
Teng-Shen Yang;Liang-Hung Lu
This brief presents a tri-band, two-stage compact low-noise amplifier (LNA) that simultaneously enhances linearity, gain, and noise performance for WiFi applications. The second stage adopts a dual-path architecture, consisting of a main amplifier and an additional amplifier. The additional amplifier, biased in the subthreshold region, suppresses third-order nonlinearity and enhances gain without increasing power consumption. The first-stage LNA reduces the noise contribution from the second stage, improving overall noise performance. To further minimize power consumption, an inverter-based topology is employed. Fabricated in a 90-nm CMOS process, the proposed LNA achieves an $S_{11}$ below −5 dB at 2.4, 5, and 6 GHz, covering key WiFi bands. At 6-GHz band, it delivers 13.5-dB gain, 3.2-dBm third-order input intercept point (IIP3), and 3.1-dB noise figure (NF). At 5-GHz band, it achieves 15-dB gain, 0.7-dBm IIP3, and 2.76-dB NF. At 2.4-GHz band, it provides 20.66-dB gain, −7-dBm IIP3, and 2.7-dB NF. The circuit consumes only 3 mW of dc power. Measurements at 6 GHz show that the dual-path technique in the second stage improves IIP3 by 8.6 dB, increases gain by 1.5 dB, and reduces NF by 0.6 dB, all without additional power or area overhead.
{"title":"A Tri-Band Two-Stage LNA With Simultaneous Linearity and Gain Enhancement for WiFi","authors":"Teng-Shen Yang;Liang-Hung Lu","doi":"10.1109/TVLSI.2025.3627973","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3627973","url":null,"abstract":"This brief presents a tri-band, two-stage compact low-noise amplifier (LNA) that simultaneously enhances linearity, gain, and noise performance for WiFi applications. The second stage adopts a dual-path architecture, consisting of a main amplifier and an additional amplifier. The additional amplifier, biased in the subthreshold region, suppresses third-order nonlinearity and enhances gain without increasing power consumption. The first-stage LNA reduces the noise contribution from the second stage, improving overall noise performance. To further minimize power consumption, an inverter-based topology is employed. Fabricated in a 90-nm CMOS process, the proposed LNA achieves an <inline-formula> <tex-math>$S_{11}$ </tex-math></inline-formula> below −5 dB at 2.4, 5, and 6 GHz, covering key WiFi bands. At 6-GHz band, it delivers 13.5-dB gain, 3.2-dBm third-order input intercept point (IIP3), and 3.1-dB noise figure (NF). At 5-GHz band, it achieves 15-dB gain, 0.7-dBm IIP3, and 2.76-dB NF. At 2.4-GHz band, it provides 20.66-dB gain, −7-dBm IIP3, and 2.7-dB NF. The circuit consumes only 3 mW of dc power. Measurements at 6 GHz show that the dual-path technique in the second stage improves IIP3 by 8.6 dB, increases gain by 1.5 dB, and reduces NF by 0.6 dB, all without additional power or area overhead.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"687-691"},"PeriodicalIF":3.1,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-04DOI: 10.1109/TVLSI.2025.3624380
Vinh T. Nguyen;Wei-Che Liang;Thai N. Nguyen;Shao-I Chu;Bing-Hong Liu;Chen-Yang Hong;Shao-Tong Chen
This brief presents the area-time efficient decoding algorithm and architecture for the double error correcting $(63,51)$ Bose–Chaudhuri–Hocquenghem (BCH) code with applications to wireless body area networks (WBANs). The formula for finding the roots of an error locator polynomial (ELP) is rederived to reduce the decoding complexity. The trace constraint for this formula is also taken into consideration to avoid the performance loss of bit error rate (BER). Hardware implementation results reveal that the proposed architecture surpasses the well-known Chien search-based and searchless decoders by the improvements of at least 50.89% and 29.35%, respectively, in terms of area-time complexity.
{"title":"Area-Time Efficient Formula-Based BCH Decoder With Trace Mechanism for WBAN Applications","authors":"Vinh T. Nguyen;Wei-Che Liang;Thai N. Nguyen;Shao-I Chu;Bing-Hong Liu;Chen-Yang Hong;Shao-Tong Chen","doi":"10.1109/TVLSI.2025.3624380","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3624380","url":null,"abstract":"This brief presents the area-time efficient decoding algorithm and architecture for the double error correcting <inline-formula> <tex-math>$(63,51)$ </tex-math></inline-formula> Bose–Chaudhuri–Hocquenghem (BCH) code with applications to wireless body area networks (WBANs). The formula for finding the roots of an error locator polynomial (ELP) is rederived to reduce the decoding complexity. The trace constraint for this formula is also taken into consideration to avoid the performance loss of bit error rate (BER). Hardware implementation results reveal that the proposed architecture surpasses the well-known Chien search-based and searchless decoders by the improvements of at least 50.89% and 29.35%, respectively, in terms of area-time complexity.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"667-671"},"PeriodicalIF":3.1,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a low-power 9T static random access memory (SRAM) with enhanced read sensing margin and read performance. The read decoupled port of the proposed 9T SRAM cell achieves the enhanced sensing margin by mitigating the read bitline (RBL) leakage and improves the read performance through using one-transistor read path. The multithreshold voltage devices are used in SRAM cell for improving the leakage power and performance of SRAM. Additionally, an interleaved write wordline (WWL) structure is implemented to address the write half-select issue. The measurement results of the test chip fabricated in the 22-nm FDSOI technology demonstrate that the designed 9T SRAM achieves a minimum operation voltage of 0.31 V at 1.05 MHz and can operate at 60.5 MHz when the supply voltage is 0.5 V. The minimum active energy of 18.56 fJ/access-bit is obtained at 0.33 V. Furthermore, the designed SRAM exhibits a minimum leakage power of 0.11 pW/bitcell in the retention mode.
{"title":"A 0.31-V 16-Kb 9T SRAM With Enhanced Sensing Margin and Read Performance for Low-Power Applications","authors":"Pengyuan Zhao;Huidong Zhao;Linnan Li;Zhi Li;Minglong Jia;Xiang Li;Shushan Qiao","doi":"10.1109/TVLSI.2025.3624842","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3624842","url":null,"abstract":"This brief presents a low-power 9T static random access memory (SRAM) with enhanced read sensing margin and read performance. The read decoupled port of the proposed 9T SRAM cell achieves the enhanced sensing margin by mitigating the read bitline (RBL) leakage and improves the read performance through using one-transistor read path. The multithreshold voltage devices are used in SRAM cell for improving the leakage power and performance of SRAM. Additionally, an interleaved write wordline (WWL) structure is implemented to address the write half-select issue. The measurement results of the test chip fabricated in the 22-nm FDSOI technology demonstrate that the designed 9T SRAM achieves a minimum operation voltage of 0.31 V at 1.05 MHz and can operate at 60.5 MHz when the supply voltage is 0.5 V. The minimum active energy of 18.56 fJ/access-bit is obtained at 0.33 V. Furthermore, the designed SRAM exhibits a minimum leakage power of 0.11 pW/bitcell in the retention mode.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"672-676"},"PeriodicalIF":3.1,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-31DOI: 10.1109/TVLSI.2025.3624325
Atri Chatterjee;Habibur Rahaman;Swarup Bhunia
The horizontal business model of modern semiconductors—where design, fabrication, and testing are handled by separate entities across a global supply chain—exposes integrated circuits (ICs) to various security threats throughout their lifecycle. Physical unclonable functions (PUFs) have emerged as effective hardware security primitives for device identification and attestation. However, integrating PUFs into existing designs is often manual, labor-intensive, and incurs high overhead in area, power, and design time. Moreover, traditional PUFs are typically localized to small regions of a chip, limiting entropy extraction from the full design surface. To address these limitations, we propose ASTRA, an automated framework that integrates PUF-based entropy sources into digital logic circuits in a distributed and timing-aware fashion. ASTRA enhances the conventional logic synthesis flow by inserting memory-in-logic PUFs (MeLPUFs), which are constructed using standard cell elements and offer high entropy. By distributing MeLPUF primitives across the circuit, ASTRA maximizes response randomness while minimizing area and power overhead. It can also reuse existing logic elements and supports multiple MeLPUF templates. ASTRA ensures timing constraints are respected and enables validation of both functional and logic equivalence checking (LEC) between the original and PUF-inserted designs. Experimental results show that ASTRA achieves near-ideal PUF quality metrics, demonstrating its effectiveness and scalability for secure hardware design.
{"title":"ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication","authors":"Atri Chatterjee;Habibur Rahaman;Swarup Bhunia","doi":"10.1109/TVLSI.2025.3624325","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3624325","url":null,"abstract":"The horizontal business model of modern semiconductors—where design, fabrication, and testing are handled by separate entities across a global supply chain—exposes integrated circuits (ICs) to various security threats throughout their lifecycle. Physical unclonable functions (PUFs) have emerged as effective hardware security primitives for device identification and attestation. However, integrating PUFs into existing designs is often manual, labor-intensive, and incurs high overhead in area, power, and design time. Moreover, traditional PUFs are typically localized to small regions of a chip, limiting entropy extraction from the full design surface. To address these limitations, we propose ASTRA, an automated framework that integrates PUF-based entropy sources into digital logic circuits in a distributed and timing-aware fashion. ASTRA enhances the conventional logic synthesis flow by inserting memory-in-logic PUFs (MeLPUFs), which are constructed using standard cell elements and offer high entropy. By distributing MeLPUF primitives across the circuit, ASTRA maximizes response randomness while minimizing area and power overhead. It can also reuse existing logic elements and supports multiple MeLPUF templates. ASTRA ensures timing constraints are respected and enables validation of both functional and logic equivalence checking (LEC) between the original and PUF-inserted designs. Experimental results show that ASTRA achieves near-ideal PUF quality metrics, demonstrating its effectiveness and scalability for secure hardware design.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"634-647"},"PeriodicalIF":3.1,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/TVLSI.2025.3621796
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2025.3621796","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3621796","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 11","pages":"C3-C3"},"PeriodicalIF":3.1,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222779","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145398666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/TVLSI.2025.3619126
Zirui Cui;Yiqun Shi;Qingqing Sun;Hao Zhu
Analog-to-digital converters (ADCs) with a wide input range and power efficiency are highly desired in various applications like robust industrial sensor data acquisition and bioelectrical signal monitoring, where successive approximation register (SAR) ADCs fabricated in mature process nodes account for a large proportion. This brief presents a buffer-in-loop (BIL) noise-shaping (NS) SAR ADC with a proposed CDAC sharing (CS)-error-feedback (EF) structure and kT/$C$ cancellation method in 180 nm. Compared with traditional EF methods, this CS-EF NS scheme takes advantage of the simple BIL structure and reduces the input signal degradation problem due to charge sharing with the input signal or parasitic capacitor of the series EF capacitor in the signal path, and enhances the system robustness. Combined with the kT/$C$ cancellation and coarse-to-fine conversion techniques, this BIL NS-SAR reduces the noise from sampling, buffer, and pre-amp. The measured peak signal-to-noise-and-distortion ratio (SNDR) is 74.9 dB with a bandwidth of 0.6 MHz, and this ADC consumes $218.7~mu $ W without the buffer.
{"title":"A Buffer-in-Loop NS-SAR ADC With CDAC Sharing-Error Feedback Structure and kT/C Noise Cancellation in 0.18-μm CMOS Technology","authors":"Zirui Cui;Yiqun Shi;Qingqing Sun;Hao Zhu","doi":"10.1109/TVLSI.2025.3619126","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3619126","url":null,"abstract":"Analog-to-digital converters (ADCs) with a wide input range and power efficiency are highly desired in various applications like robust industrial sensor data acquisition and bioelectrical signal monitoring, where successive approximation register (SAR) ADCs fabricated in mature process nodes account for a large proportion. This brief presents a buffer-in-loop (BIL) noise-shaping (NS) SAR ADC with a proposed CDAC sharing (CS)-error-feedback (EF) structure and <italic>kT</i>/<inline-formula> <tex-math>$C$ </tex-math></inline-formula> cancellation method in 180 nm. Compared with traditional EF methods, this CS-EF NS scheme takes advantage of the simple BIL structure and reduces the input signal degradation problem due to charge sharing with the input signal or parasitic capacitor of the series EF capacitor in the signal path, and enhances the system robustness. Combined with the <italic>kT</i>/<inline-formula> <tex-math>$C$ </tex-math></inline-formula> cancellation and coarse-to-fine conversion techniques, this BIL NS-SAR reduces the noise from sampling, buffer, and pre-amp. The measured peak signal-to-noise-and-distortion ratio (SNDR) is 74.9 dB with a bandwidth of 0.6 MHz, and this ADC consumes <inline-formula> <tex-math>$218.7~mu $ </tex-math></inline-formula>W without the buffer.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"327-331"},"PeriodicalIF":3.1,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/TVLSI.2025.3610232
Qun Zhou;Kang Zeng;Weiwei Yue;Qing Hua
This addresses errors in the Early Access version of [1]. Due to a publisher error, the terms Q1, Q2, and Q3 were used (with subscripts) instead of Q1, Q2, and Q3 (no subscript). They represent nodes on the schematic, not variables.
{"title":"Erratum to “An Ultralow-Energy Voltage Level Shifter With an Output-Cycle-Based Dynamic Biasing Scheme in a 130-nm CMOS Technology”","authors":"Qun Zhou;Kang Zeng;Weiwei Yue;Qing Hua","doi":"10.1109/TVLSI.2025.3610232","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3610232","url":null,"abstract":"This addresses errors in the Early Access version of [1]. Due to a publisher error, the terms Q1, Q2, and Q3 were used (with subscripts) instead of Q1, Q2, and Q3 (no subscript). They represent nodes on the schematic, not variables.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 11","pages":"3206-3206"},"PeriodicalIF":3.1,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222851","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145398665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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