Pub Date : 2024-12-11DOI: 10.1109/TVLSI.2024.3493512
Jari Nurmi;Snorre Aunet;Alireza Saberkari
{"title":"Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023","authors":"Jari Nurmi;Snorre Aunet;Alireza Saberkari","doi":"10.1109/TVLSI.2024.3493512","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3493512","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2169-2172"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10791332","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TVLSI.2024.3508673
Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta
Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by $15times $ to over $23.8times $ depending on performance level. Alternatively, LT improves performance by $2.4times $ (high-power, high-performance) $- 7.0times $ (low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in $V_{text {th}}$ variation to leverage benefits at cryogenic temperatures.
{"title":"A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation","authors":"Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta","doi":"10.1109/TVLSI.2024.3508673","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3508673","url":null,"abstract":"Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by \u0000<inline-formula> <tex-math>$15times $ </tex-math></inline-formula>\u0000 to over \u0000<inline-formula> <tex-math>$23.8times $ </tex-math></inline-formula>\u0000 depending on performance level. Alternatively, LT improves performance by \u0000<inline-formula> <tex-math>$2.4times $ </tex-math></inline-formula>\u0000 (high-power, high-performance) \u0000<inline-formula> <tex-math>$- 7.0times $ </tex-math></inline-formula>\u0000 (low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 variation to leverage benefits at cryogenic temperatures.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"102-113"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TVLSI.2024.3494293
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3494293","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3494293","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10791312","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TVLSI.2024.3504856
Mahipal Dargupally;Lomash Chandra Acharya;Arvind K. Sharma;Sudeb Dasgupta;Anand Bulusu
In this article, we propose a method for sizing an arbitrary combinational datapath to minimize its energy consumption. Our method involves deriving expressions for the components of energy consumption at both the stage and path levels. In this work, we identify overshoot energy ($E_{text {OS}}$ ) consumption as a previously unreported component contributing to energy consumption, particularly significant in the near/sub-threshold voltage regime. We determine that this $E_{text {OS}}$ consumption is proportional to the input and output transition times and size of a logic gate at a particular stage of a datapath. We also observe that, for a given number of stages (N) and path effort, the total energy consumption is optimized when the stage effort (f) in a datapath is kept constant. Based on our observations and derivations of all the energy components and the requirement for a constant “f” in the datapath, we develop a method to minimize the energies of a logic circuit while maintaining the timing closure requirement. We determine that the non-critical paths (NCPs) must be sized to a minimum “f” while maintaining the timing requirements. We verified our models on several ISCAS and EPFL benchmark circuits with an average reduction of 28.1% (41.2%) and 19.2% (28.4%) in energy consumption [figure of merit (FoM)], respectively. The proposed methodology predicts the total energy consumption at a stage and path level of N-stage logic, with only one-time SPICE simulation on a single stage, with a maximum error of 1.3% and 1.62%, respectively, against SPICE simulations. The simulations are performed in Synopsys HSPICE environment with ST Microelectronics 65 nm CMOS and 28 nm FDSOI technology nodes, resulting in a very good agreement with the developed methodology.
{"title":"A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime","authors":"Mahipal Dargupally;Lomash Chandra Acharya;Arvind K. Sharma;Sudeb Dasgupta;Anand Bulusu","doi":"10.1109/TVLSI.2024.3504856","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3504856","url":null,"abstract":"In this article, we propose a method for sizing an arbitrary combinational datapath to minimize its energy consumption. Our method involves deriving expressions for the components of energy consumption at both the stage and path levels. In this work, we identify overshoot energy (<inline-formula> <tex-math>$E_{text {OS}}$ </tex-math></inline-formula>) consumption as a previously unreported component contributing to energy consumption, particularly significant in the near/sub-threshold voltage regime. We determine that this <inline-formula> <tex-math>$E_{text {OS}}$ </tex-math></inline-formula> consumption is proportional to the input and output transition times and size of a logic gate at a particular stage of a datapath. We also observe that, for a given number of stages (N) and path effort, the total energy consumption is optimized when the stage effort (f) in a datapath is kept constant. Based on our observations and derivations of all the energy components and the requirement for a constant “f” in the datapath, we develop a method to minimize the energies of a logic circuit while maintaining the timing closure requirement. We determine that the non-critical paths (NCPs) must be sized to a minimum “f” while maintaining the timing requirements. We verified our models on several ISCAS and EPFL benchmark circuits with an average reduction of 28.1% (41.2%) and 19.2% (28.4%) in energy consumption [figure of merit (FoM)], respectively. The proposed methodology predicts the total energy consumption at a stage and path level of N-stage logic, with only one-time SPICE simulation on a single stage, with a maximum error of 1.3% and 1.62%, respectively, against SPICE simulations. The simulations are performed in Synopsys HSPICE environment with ST Microelectronics 65 nm CMOS and 28 nm FDSOI technology nodes, resulting in a very good agreement with the developed methodology.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"771-779"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TVLSI.2024.3494295
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3494295","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3494295","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10791330","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TVLSI.2024.3504313
{"title":"IEEE Foundation - Reflecting on 50 Years of Impact","authors":"","doi":"10.1109/TVLSI.2024.3504313","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3504313","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2408-2408"},"PeriodicalIF":2.8,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10791339","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TVLSI.2024.3508079
Hyoseok Song;Kwangmin Kim;Gain Kim;Byungsub Kim
We propose a fast algorithm to optimize on-chip equalizing link design utilizing a particle swarm optimization (PSO) method. Finding the optimal design parameters of an equalizing link requires too much computation time, because the dependency between design parameters and performances is too complex, while design space is too large. The proposed algorithm greatly reduces the optimization time by utilizing the superior efficiency of PSO in heuristic search. In experiment, on average, the proposed algorithm optimized a link design $168times $ faster than the previous state-of-the-art result, requiring only 1/256 evaluation counts, and reduced computation time from about 2 h to 45 s.
{"title":"A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization","authors":"Hyoseok Song;Kwangmin Kim;Gain Kim;Byungsub Kim","doi":"10.1109/TVLSI.2024.3508079","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3508079","url":null,"abstract":"We propose a fast algorithm to optimize on-chip equalizing link design utilizing a particle swarm optimization (PSO) method. Finding the optimal design parameters of an equalizing link requires too much computation time, because the dependency between design parameters and performances is too complex, while design space is too large. The proposed algorithm greatly reduces the optimization time by utilizing the superior efficiency of PSO in heuristic search. In experiment, on average, the proposed algorithm optimized a link design \u0000<inline-formula> <tex-math>$168times $ </tex-math></inline-formula>\u0000 faster than the previous state-of-the-art result, requiring only 1/256 evaluation counts, and reduced computation time from about 2 h to 45 s.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"1-9"},"PeriodicalIF":2.8,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TVLSI.2024.3505920
Anawin Opasatian;Makoto Ikeda
Modular multiplication is a fundamental operation in many cryptographic systems, with its efficiency playing a crucial role in the overall performance of these systems. Since many cryptographic systems operate with a fixed modulus, we propose an enhancement to the fixed modulus lookup table (LuT) method used for modular reduction, which we refer to as the manipulated LuT (MLuT) method. Our approach applies to any modulus and has demonstrated comparable performance compared with some specialized reduction algorithms designed for specific moduli. The strength of our proposed method in terms of circuit performance is shown by implementing it on Virtex7 and Virtex Ultrascale+ FPGA as the LUT-based MLuT modular multiplier (LUT-MLuTMM) with generalized parallel counters (GPCs) used in the summation step. In one-stage implementations, our proposed method achieves up to a 90% reduction in area and a 50% reduction in latency compared with the generic LuT method. In multistage implementations, our approach offers the best area-interleaved time product, with improvements of 39%, 13%, and 29% over the current state-of-the-art for ~256-bit, SIKE434, and BLS12-381 modular multipliers, respectively. These results demonstrate the potential of our method for high-performance cryptographic accelerators employing a fixed modulus.
{"title":"Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier","authors":"Anawin Opasatian;Makoto Ikeda","doi":"10.1109/TVLSI.2024.3505920","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3505920","url":null,"abstract":"Modular multiplication is a fundamental operation in many cryptographic systems, with its efficiency playing a crucial role in the overall performance of these systems. Since many cryptographic systems operate with a fixed modulus, we propose an enhancement to the fixed modulus lookup table (LuT) method used for modular reduction, which we refer to as the manipulated LuT (MLuT) method. Our approach applies to any modulus and has demonstrated comparable performance compared with some specialized reduction algorithms designed for specific moduli. The strength of our proposed method in terms of circuit performance is shown by implementing it on Virtex7 and Virtex Ultrascale+ FPGA as the LUT-based MLuT modular multiplier (LUT-MLuTMM) with generalized parallel counters (GPCs) used in the summation step. In one-stage implementations, our proposed method achieves up to a 90% reduction in area and a 50% reduction in latency compared with the generic LuT method. In multistage implementations, our approach offers the best area-interleaved time product, with improvements of 39%, 13%, and 29% over the current state-of-the-art for ~256-bit, SIKE434, and BLS12-381 modular multipliers, respectively. These results demonstrate the potential of our method for high-performance cryptographic accelerators employing a fixed modulus.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"114-127"},"PeriodicalIF":2.8,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10777922","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TVLSI.2024.3507714
Jhe-En Lin;Shen-Iuan Liu
This article presents a 40-Gb/s (25.6-GBaud) three-level pulse amplitude modulation (PAM-3) baud-rate receiver with one-tap decision-feedback equalize (DFE). A baud-rate phase detector (BRPD) that locks at the point with zero first postcursor is proposed. In addition, by reusing the BRPD’s error samplers, a weighting coefficient calibration is presented to select the DFE weighting coefficient that maximizes the top level of the eye diagram, thereby improving eye height across different channel losses. An inductorless continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA) are also included. The VGA adjusts the output common-mode resistance to control data swing, reducing power consumption when the required swing is small. Furthermore, by using the modified summer-merged slicers, the capacitance from the slicers to the VGA is reduced. Finally, a digital clock/data recovery (CDR) circuit is presented, which includes a demultiplexer (DeMUX) with a short delay time to reduce the loop latency. The 40-Gb/s PAM-3 receiver is fabricated in 28-nm CMOS technology. For a 25.6-Gbaud pseudorandom ternary sequence of $3^{7}$ –1, the measured bit error rate (BER) is below $10^{-12}$ for channel losses of 9 and 17.5 dB. At a 9-dB loss, total power consumption is 35-mW with a calculated FoM of 0.875-pJ/bit. At 17.5-dB loss, total power consumption is 38-mW with a calculated FoM of 0.95-pJ/bit.
{"title":"A 0.875–0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE","authors":"Jhe-En Lin;Shen-Iuan Liu","doi":"10.1109/TVLSI.2024.3507714","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3507714","url":null,"abstract":"This article presents a 40-Gb/s (25.6-GBaud) three-level pulse amplitude modulation (PAM-3) baud-rate receiver with one-tap decision-feedback equalize (DFE). A baud-rate phase detector (BRPD) that locks at the point with zero first postcursor is proposed. In addition, by reusing the BRPD’s error samplers, a weighting coefficient calibration is presented to select the DFE weighting coefficient that maximizes the top level of the eye diagram, thereby improving eye height across different channel losses. An inductorless continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA) are also included. The VGA adjusts the output common-mode resistance to control data swing, reducing power consumption when the required swing is small. Furthermore, by using the modified summer-merged slicers, the capacitance from the slicers to the VGA is reduced. Finally, a digital clock/data recovery (CDR) circuit is presented, which includes a demultiplexer (DeMUX) with a short delay time to reduce the loop latency. The 40-Gb/s PAM-3 receiver is fabricated in 28-nm CMOS technology. For a 25.6-Gbaud pseudorandom ternary sequence of \u0000<inline-formula> <tex-math>$3^{7}$ </tex-math></inline-formula>\u0000–1, the measured bit error rate (BER) is below \u0000<inline-formula> <tex-math>$10^{-12}$ </tex-math></inline-formula>\u0000 for channel losses of 9 and 17.5 dB. At a 9-dB loss, total power consumption is 35-mW with a calculated FoM of 0.875-pJ/bit. At 17.5-dB loss, total power consumption is 38-mW with a calculated FoM of 0.95-pJ/bit.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"168-178"},"PeriodicalIF":2.8,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TVLSI.2024.3507567
Ken Li;Tian Xie;Tzu-Han Wang;Shaolan Li
This article presents VSAGE, an agile end-to-end automated voltage-controlled oscillator (VCO)-based $Delta Sigma $ analog-to-digital converter (ADC) generator. It exploits time-domain architectures and design mindset, so that the design flow is highly oriented around digital standard cells in contrast to the transistor-level-focused approach in conventional analog design. Through this, it speeds up and simplifies both the synthesis phase and layout phase. Combined with an efficient knowledge-machine learning (ML)-guided synthesis flow, it can translate input specifications to a full system layout with reliable performance within minutes. This work also features a compact oscillator and system modeling method that facilitates light-resource accurate computation and network training. The generator is verified with 12 design cases in 65-nm and 28-nm processes, proving its capability of generating competitive design with good process portability.
{"title":"VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator","authors":"Ken Li;Tian Xie;Tzu-Han Wang;Shaolan Li","doi":"10.1109/TVLSI.2024.3507567","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3507567","url":null,"abstract":"This article presents VSAGE, an agile end-to-end automated voltage-controlled oscillator (VCO)-based \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 analog-to-digital converter (ADC) generator. It exploits time-domain architectures and design mindset, so that the design flow is highly oriented around digital standard cells in contrast to the transistor-level-focused approach in conventional analog design. Through this, it speeds up and simplifies both the synthesis phase and layout phase. Combined with an efficient knowledge-machine learning (ML)-guided synthesis flow, it can translate input specifications to a full system layout with reliable performance within minutes. This work also features a compact oscillator and system modeling method that facilitates light-resource accurate computation and network training. The generator is verified with 12 design cases in 65-nm and 28-nm processes, proving its capability of generating competitive design with good process portability.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"128-139"},"PeriodicalIF":2.8,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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