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46-nA High-PSR CMOS Buffered Voltage Reference With 1.2–5 V and $-$40 $^{circ}$C to 125 $^{circ}$C Operating Range 46-nA 高PSR CMOS 缓冲电压基准,工作范围为 1.2-5 V 和 $-$40 $^{circ}$C 至 125 $^{circ}$C
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-17 DOI: 10.1109/tvlsi.2024.3455428
Chiara Venezia, Andrea Ballo, Alfio Dario Grasso, Alessandro Rizzo, Calogero Ribellino, Salvatore Pennisi
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引用次数: 0
Architectural Exploration for Waferscale Switching System 晶圆级交换系统架构探索
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-17 DOI: 10.1109/tvlsi.2024.3455332
Zhiquan Wan, Zhipeng Cao, Shunbin Li, Peijie Li, Qingwen Deng, Weihao Wang, Kun Zhang, Guandong Liu, Ruyun Zhang, Qinrang Liu
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引用次数: 0
Effective Parallel Redundancy Analysis Using GPU for Memory Repair 利用 GPU 对内存修复进行有效的并行冗余分析
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-13 DOI: 10.1109/tvlsi.2024.3454286
Seung Ho Shin, Hayoung Lee, Sungho Kang
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引用次数: 0
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V Sophon:基于 RISC-V 的可重复时间和低延迟嵌入式实时系统架构
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-11 DOI: 10.1109/tvlsi.2024.3447279
Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang
{"title":"Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V","authors":"Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang","doi":"10.1109/tvlsi.2024.3447279","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3447279","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142194447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling CR-DRAM:利用子阵列间电荷回收提高 DRAM 刷新能效
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-11 DOI: 10.1109/tvlsi.2024.3445631
Haitao Du, Hairui Zhu, Song Chen, Yi Kang
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引用次数: 0
A Novel TriNet Architecture for Enhanced Analog IC Design Automation 用于增强模拟集成电路设计自动化的新型 TriNet 架构
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-10 DOI: 10.1109/TVLSI.2024.3452032
Arunkumar P Chavan;Shrish Shrinath Vaidya;Sanket M. Mantrashetti;Abhishek Gurunath Dastikopp;Kishan S. Murthy;H. V. Ravish Aradhya;Prakash Pawar
Analog integrated circuit (IC) design and its automation pose significant challenges due to the time-consuming mathematical computations and complexity of circuit design. Though efforts have been made to automate the analog design flow, the current approach falls short in meeting the exact design requirements and plagued by inaccuracies, highlighting the necessity for a more robust approach capable of accurately predicting circuits. In addition, there is a need for an improved dataset collection technique to enhance the overall performance of the automation process. The power management unit (PMU) is a crucial block in any IC that requires the design of low-dropout regulator (LDO) for which amplifiers are fundamental blocks. This research harnesses the capabilities of deep neural networks (DNNs) to automate essential amplifier blocks, such as the differential amplifier (DiffAmp) and two-stage operational amplifier (OpAmp). In addition, it proposes an automation framework for the higher level circuitry of the LDO. This article introduces a novel “TriNet” architecture designed for various parameters of amplifiers, including gain, bandwidth, and power facilitating precise predictions for DiffAmp and OpAmp, and presents a decoder architecture tailored for LDO. A notable aspect is the development of an efficient technique for acquiring larger datasets in a condensed timeframe. The presented methodologies demonstrate high accuracy rates, achieving 97.3% for DiffAmp and OpAmp circuits and 94.3% for LDO design.
由于耗时的数学计算和电路设计的复杂性,模拟集成电路 (IC) 设计及其自动化面临巨大挑战。尽管人们一直在努力实现模拟设计流程的自动化,但目前的方法无法满足精确的设计要求,而且存在误差,这就凸显出需要一种能够准确预测电路的更强大的方法。此外,还需要改进数据集收集技术,以提高自动化流程的整体性能。电源管理单元(PMU)是任何集成电路中的关键模块,需要设计低压差稳压器(LDO),而放大器是其基本模块。本研究利用深度神经网络(DNN)的功能来自动化重要的放大器模块,如差分放大器(DiffAmp)和两级运算放大器(OpAmp)。此外,它还为 LDO 的高层电路提出了一个自动化框架。本文介绍了针对放大器各种参数(包括增益、带宽和功率)设计的新型 "TriNet "架构,有助于对 DiffAmp 和 OpAmp 进行精确预测,并提出了专为 LDO 量身定制的解码器架构。一个值得注意的方面是开发了一种高效技术,可在较短的时间内获取较大的数据集。所介绍的方法具有很高的准确率,DiffAmp 和 OpAmp 电路的准确率达到 97.3%,LDO 设计的准确率达到 94.3%。
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引用次数: 0
A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic 具有快速转换前景时间校准和基于比较的控制逻辑的双通道交错 ADC
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-09 DOI: 10.1109/TVLSI.2024.3449293
Xiang Yan;Kefan Qin;Xinyue Zheng;Weibo Hu;Wei Ma;Haitao Cui
A dual-channel interleaved analog-to-digital converter (ADC) operating at 320 MS/s is prototyped to validate a fast-converging foreground time calibration algorithm that is independent of ADC offset errors. An input polarity switching technique is introduced to eliminate the impact of sub-ADC offset mismatches during foreground time calibration. After foreground calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) are improved by 8.6 and 18.4 dB, respectively. In the sub-ADC design, a comparison functionality is enabled in the digital circuits to prevent metastability and expedite data conversion. The single-channel conversion rates reach 160 MS/s. The ADC is implemented via 40-nm digital CMOS technology, achieving a 52.01 dB signal-to-noise plus distortion ratio (SNDR) at near-Nyquist input while sampling at 320 MS/s. The overall power consumption is 3.65 mW, which includes an on-chip reference buffer and a clock circuit.
对工作频率为 320 MS/s 的双通道交错模数转换器 (ADC) 进行了原型验证,以验证独立于 ADC 偏移误差的快速转换前景时间校准算法。在前景时间校准过程中,引入了一种输入极性切换技术,以消除次 ADC 偏移失配的影响。前景校准后,信噪比和失真比 (SNDR) 以及无杂散动态范围 (SFDR) 分别提高了 8.6 和 18.4 dB。在次级 ADC 设计中,数字电路启用了比较功能,以防止不稳定性并加快数据转换。单通道转换速率达到 160 MS/s。ADC 采用 40 纳米数字 CMOS 技术实现,在接近奈奎斯特输入时达到 52.01 dB 的信噪比加失真比 (SNDR),同时采样率为 320 MS/s。总体功耗为 3.65 mW,其中包括一个片上基准缓冲器和一个时钟电路。
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引用次数: 0
Multiobjective Optimization of Class-F Oscillators F 类振荡器的多目标优化
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-05 DOI: 10.1109/tvlsi.2024.3449567
Zhan Qu, Zhenjiao Chen, Xingqiang Shi, Ya Zhao, Guohe Zhang, Feng Liang
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引用次数: 0
A Post-Bond ILV Test Method in Monolithic 3-D ICs 单片三维集成电路中的粘接后 ILV 测试方法
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-05 DOI: 10.1109/tvlsi.2024.3450452
Xu Fang, Xiaofeng Zhao
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引用次数: 0
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors 带校准电路的双数据率纹波计数器,用于 CMOS 图像传感器中的相关多重采样
IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-09-04 DOI: 10.1109/tvlsi.2024.3449320
Wanbin Zha, Jiangtao Xu, Kaiming Nie, Zhiyuan Gao
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引用次数: 0
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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